ii
Copyright 19982001 by LSI Logic Corporation. All rights reserved.
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB14-000036-04, Fifth Edition (May 2001)
This document describes the LSI Logic Corporation 1394 Physical Layer (PHY)
Core and will remain the official reference source for all revisions/releases of this
product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright 19982001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, CoreWare, FlexStream, G12, GigaBlaze, and
Right-First-Time are registered trademarks or trademarks of LSI Logic
Corporation. All other brand and product names may be trademarks of their
respective companies.
MJB
phybook.book Page ii Thursday, May 31, 2001 11:14 AM
Preface
iii
Copyright 19982001 by LSI Logic Corporation. All rights reserved.
Preface
This book is the primary reference and technical manual for the
1394 Physical Layer (PHY) core. It contains preliminary information
regarding the functional description of the 1394 PHY core.
Audience
This document assumes that you have some familiarity with the
IEEE 1394 high-performance serial bus and related support devices, and
that you have read the IEEE Std 1394 - 1995 and IEEE Std 1394a - 2000
specifications. The people who benefit from this book are:
Engineers and managers who are evaluating the core for possible
use in a chip
Engineers who are designing the core into a chip
Organization
This document has the following chapters and appendixes:
Chapter 1, Introduction
, summarizes the key features and
applications of the 1394 PHY core.
Chapter 2, Register Descriptions
, describes the registers within the
1394 PHY core.
Chapter 3, Signal Descriptions
, describes the signals that make up
the external interface of the 1394 PHY core.
Chapter 4, 1394 PHY Core Operation
, provides functional
waveforms, which show the operation of the 1394 PHY core.
Chapter 5, Test Modes
, describes most of the test modes for the
1394 PHY core.
phybook.book Page iii Thursday, May 31, 2001 11:14 AM
iv
Preface
Copyright 19982001 by LSI Logic Corporation. All rights reserved.
Related Publications
IEEE Standard for a High Performance Serial Bus (IEEE Std
1394 - 1995)
IEEE Standard for a High Performance Serial Bus Amendment 1
(IEEE Std 1394a - 2000)
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix "0x" --for example,
0x32CF. Binary numbers are indicated by the prefix "0b" --for example,
0b0011.0010.1100.1111.
Abbreviations
1394
The high-speed serial bus defined by IEEE Std 1394 - 1995
and IEEE Std 1394a - 2000 specifications
PHY
Physical Layer
phybook.book Page iv Thursday, May 31, 2001 11:14 AM
Contents
v
Copyright 19982001 by LSI Logic Corporation. All rights reserved.
Contents
Chapter 1
Introduction
1.1
1394 PHY Core Overview
1-1
1.2
Features
1-3
1.3
CoreWare
Program
1-4
Chapter 2
Register Descriptions
2.1
Register Access
2-1
2.2
Extended PHY Register Map
2-2
2.2.1
Register Address 0x00
2-3
2.2.2
Register Address 0x01
2-3
2.2.3
Register Address 0x02
2-4
2.2.4
Register Address 0x03
2-4
2.2.5
Register Address 0x04
2-4
2.2.6
Register Address 0x05
2-5
2.2.7
Register Address 0x06
2-7
2.2.8
Register Address 0x07
2-7
2.2.9
Register Address 0x08
-
0x0F
2-8
2.3
Port Status Page
2-8
2.3.1
Register Address 0x08
2-9
2.3.2
Register Address 0x09
2-10
2.4
Vendor Identification Page
2-10
2.4.1
Register Address 0x08
2-11
2.4.2
Register Address 0x09
2-11
2.4.3
Register Addresses 0x0A
-
0x0C
2-11
2.4.4
Register Addresses 0x0D
-
0x0F
2-12
2.5
Vendor-Dependent Page
2-12
2.5.1
Register Address 0x08
2-12
2.5.2
Register Address 0x09
-
0x0F
2-13
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