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Электронный компонент: 80C300

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80C300
4-1
1
MD400145/G
98012
80C300
Full Duplex CMOS Ethernet
10/100 Mega Bit/Sec Data Link Controller
Features
s
Low Power CMOS Technology
s
10/100 MBit Ethernet Controller Optimized for
Switching Hub, Multiport Bridge/Router, &
Server Applications
s
Meets ANSI/IEEE 802.3 and ISO 8802-3 Standards
for Ethernet (10Base-5) Thin Net (10Base-2)
(10Base-T) and the Proposed 100Base-T4,
100Base-TX Standards
s
10 MHz Serial/Parallel Conversion in 10 MBit/sec
Serial Mode.
s
Standard 10MBit/sec Serial Mode or
Programmable MII Ethernet Interface for 10/100
MBit/sec Applications
s
Programmability of Double Word Threshold
Count for Space Available/Data Available Ready
Condition for Transmit/Receive FIFOs
s
Auto Retransmit Upon Collision Sense
s
Preamble Generation and Removal
s
Automatic 32-Bit FCS (CRC) Generation and
Checking
s
Collision Handling, Transmission Deferral and
Retransmission with Automatic Jam and
Backoff Functions
s
Error Interrupt and Status Generation
s
Selectable Little Endian/Big Endian Transmit Byte
Ordering for FIFO Interface for Intel/Motorola
Compatibility
s
Single 5 V
5% Power Supply
s
Standard CPU and Peripheral Interface
Control Signals
s
128/128 Byte Independent Transmit/Receive FIFOs
with 32 Bit Data Path Interface
- 1 G Bits/sec (133 M Bytes/sec) Peak Data Rate
in 32 Bit Mode.
s
Loopback Capability for Diagnostics
s
32 Bit FIFO Data Path
Hurricane is a trademark of SEEQ Technology Inc.
s
Inputs and Outputs TTL Compatible
s
The Following Additional Features can be
Programmed for the 80C300
- 64 bit Multicast Filter
- Reports Status of "SQE" During Transmits
- Transmit No CRC Mode
- Transmit No Preamble Mode
- Transmit Packet Autopadding Mode
- Receive CRC Mode
- Disable Self-Receive on Transmit Mode
- Disable Further Transmissions when Both
Transmit Status Registers are Full
- Disable Loading the Transmit Status for
Successfully Transmitted Packets
- Disable the Receive Interrupts Independent
of the Receive Command Register Setting
- Successful Packet Transmit Completion
Feature
s
Full Duplex Operation
- Provides 20/200 Mbps Bandwidthfor
Switched Networks
- Supports AutoDUPLEX Mode for Automatic
Full Duplex Operation
s
Transmit Status on a Per Packet Basis Reports the
Following
- Occurrence of a Transmit FIFO Underflow
- Transmit Collision Occurrence
- 16 Collision Occurrence
- Carrier Sense Error During Transmission
- 10/100 Mbit/sec Transmit Clock Detect
- Late Collision Occurrence
- Transmission Successful
- Transmission Deferred
Full Duplex
HURRICANE
TM
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
80C300
4-2
2
MD400145/G
s
Management Counters for
- Alignment Errors
- FCS Errors
- Runt Receive Frames
- Short Receive Events
- Oversized Receive Packets
- Transmit Collisions
- Receive Collisions
- Very Long Transmit Events
- Excessive Transmit Deferral
- Late Transmit Collisions
- Transmit Excessive Collisions
- Symbol Errors (100 MBit/sec Ethernet Only)
- Total Octets Received
- Total Octets Transmitted
- Receive FIFO Overflows
- Total Rx Multicast, Unicast and Broadcast
Frames
- Total Tx Multicast, Unicast and Broadcast
Frames
- Tx Defer Count
- Number of Retransmit Attempts
s
128 Pin PQFP package
80C300
4-3
3
MD400145/G
Illustrations
Figure 1. Functional Block Diagram of the 80C300
Figure 2. 80C300 Pin Configuration
Figure 3. Typical Application Example
Table of Contents
1.0 Pin Description
2.0 Introduction
3.0 Functional Description
3.1 Frame Format
3.2 Packet Transmission
3.2.1 Controlling Transmit Packet
Encapsulation
3.2.2 Transmission Initiation/Deferral
3.2.3 Collision on Transmit
3.2.4 Transmit Termination Conditions
3.2.5 Error Conditions That Will Cause
TXRET to go HIGH
3.2.6 Detection and Clearing of a Transmit
Retry Condition
3.3 Packet Reception
3.3.1 Preamble Processing
3.3.2 Address Matching
3.3.3 Conditions of Receive Termination
3.3.4 Using Rxabort to Terminate Reception
3.3.5 Receive Discard Conditions
3.4 System Interface
3.5 FIFO Interface
3.5.1 Little and Big Endian Format
3.5.2 Transmit FIFO Interface
3.5.3 Receive FIFO Interface
3.5.4 Special Conditions on RXRD_TXWR
Clock Input
3.6 Register Interface
3.6.1 Internal Channel Register
Addressing Table
3.6.2 Station Address Register
3.6.3 Transmit Command Register
3.6.4 Receive Command Register
3.6.5 Transmit Status Register
3.6.6 Receive Status Register
3.6.7 Configuration Registers
3.6.8 FIFO Threshold Register
3.6.8.1 FIFO Threshold Register
Address Settings Table
3.6.9 Defer Register Calculations for 80C300
3.7 Management Interface of the MII
3.8 Counters
4.0 DC Characteristics
5.0 AC Characteristics
5.01 Command/Status Interface Read Timing
5.02 Command/Status Interface Write Timing
6.0 Ethernet Transmit and Receive
Interface Timing
6.01 Ethernet Transmit Interface Timing
6.02 Ethernet Receive Interface Timing
7.0 Transmit Data Interface Timing
7.01 Transmit Data Interface Write Timing 1
7.02 Transmit Data Interface Write Timing 2
8.0 Receive Data Interface Timing
8.01 Receive Data Interface Read Timing 1
8.02 Receive Data Interface Read Timing 2
9.0 Transmit Data Interface Timing on
Exception Conditions
10.0 Receive Data Interface Timing on
Exception Conditions
11.0 Reset Timing
80C300
4-4
4
MD400145/G
TRANSMIT
BYTE
COUNTER
CRC
STRIPPER
CLOCK
DRIVERS
TXNOCRC
TXINTEN
RXINTEN
RXRDEN
TXWREN
CLRTXERR
TXEN
TXRET
COLL
TXRDY
RXTXEOF
RXTXBE [3:0]
RXTXDATA [31:0]
RXRD_TXWR
RXRDY
SPDTAVL
ATTEMPT
COUNTER
TRANSMIT
BYTE
CONTROL
CSN
BACKOFF
CONTROLLER
TRI-STATE
CONTROL & FIFO
INTERFACE LOGIC
TRI-STATECONT
ROL LOGIC
SPACE
LOGIC
128 BYTE
RECEIVE
FIFO
128 BYTE
TRANSMIT
FIFO
BYTE TO
DOUBLE WORD
PACKER
BIT/NIBBLE
TO BYTE
CONVERTER
PARALLEL
/SERIAL
DOUBLE
WORD TO
NIBBLE
CRC
CHECKER
ADDRESS
CHECKER
RECEIVE
COUNTER
RECEIVE
BYTE
CONTROL
FRAMING
AND ERROR
CONTROL
CRC
GENERATOR
M
U
X
TXC
RXD [3:1]
CSN
RX_DV
RXINTEN
RXABORT
RXDC
RXC
RXD0
M
U
X
CONTROL
REGISTER
FILE
RXNOCRC
TXD [3:1]
M
U
X
INTERRUPT
AND
CONTROL
TXDO
INT
REGISTER
INTERFACE
& TRI-STATE
LOGIC
WR
CDST [15:0]
RD
A [5:0]
CRC/DATA SELECT
MODE 100
Figure 1. 80C300 Functional Block Diagram
T16COLL
BUSMODE
RXOVF
RXBYT12
BUSSIZE
BE1
BE0
ENREGIO
80C300
4-5
5
MD400145/G
CDST5
CDST6
CDST7
CDST4
VDD
A3
A2
A4
VDD
GND
CDST8
CDST9
CDST10
A5
CDST11
CDST12
CDST13
GND
CDST14
CDST15
CLRTXERR
CLRRXERR
TXWREN
TXINTEN
RXINTEN
RXTXBE0
RXTXBE1
VDD
VDD
TXRET
INT
RXABORT
RXDC
RXRDY
TXRDY
TXNOCRC
RXTXEOF
SPDTAVL
RESET
RXRDEN
RXRD_TXWR
RXTXDATA10
RXTXDATA11
RXTXDATA9
RXTXDATA8
VDD
RXTXDATA6
RXTXDATA5
RXTXDATA4
RXTXDATA3
RXTXDATA2
GND
RXTXDATA7
GND
VDD
RXTXDATA16
RXTXDATA15
RXTXDATA14
RXTXDATA13
RXTXDATA12
RXTXDATA21
RXTXDATA20
RXTXDATA19
RXTXDATA18
RXTXDATA17
GND
RXC
GND
GND
RXTXDATA1
RXTXDATA0
GND
ADUPLX
MDC
TXD2
TXD1
TXD0
TXEN
COLL
MDIO
TXD3
TXC
RXD3
RXD0
CSN
RX_DV
RD
WR
BE1
BE0
T16COLL
RXOVF
RXBYT12
RX_ER
1
6
5
4
3
2
7
12
11
10
9
8
13
18
17
16
15
14
19
24
23
22
21
20
28
27
26
25
29
34
33
32
31
30
38
37
36
35
A1
A0
CDST1
CDST2
CDST3
CDST0
BUSMODE
BUSSIZE
ENREGI0
RXTXBE3
GND
VDD
RXTXBE2
GND
39
45
44
43
42
41
40
46
52
51
50
49
48
47
55
54
53
56
62
61
60
59
58
57
64
63
VDD
GND
65
71
70
69
68
67
66
72
78
77
76
75
74
73
81
80
79
82
88
87
86
85
84
83
91
90
89
92
98
97
96
95
94
93
101
100
99
102
RXTXDATA22
GND
RXTXDATA26
RXTXDATA25
RXTXDATA24
RXTXDATA23
RXTXDATA27
RXTXDATA28
GND
GND
RXTXDATA31
RXTXDATA30
RXTXDATA29
103
107
106
105
104
108
112
111
110
109
113
117
116
115
114
118
122
121
120
119
123
127
126
125
124
DAISY_OUT
128
RXD2
RXD1
GND
GND
Figure 2. 80C300 Pin Configuration
80C300
128 PQFP