ii
Copyright 20002001 by LSI Logic Corporation. All rights reserved.
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB14-000123-04, Fourth Edition (November 2001)
This document describes revision/release 1 of the LSI Logic Corporation
8101/8104 Gigabit Ethernet Controller and will remain the official reference
source for all revisions/releases of this product until rescinded by an update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright 20002001 by LSI Logic Corporation. All rights reserved. Portions
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design is a registered trademark of LSI Logic Corporation. All
other brand and product names may be trademarks of their respective
companies.
IF
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8101/8104 Gigabit Ethernet Controller
iii
Copyright 20002001 by LSI Logic Corporation. All rights reserved.
Preface
This book is the primary reference and technical manual for the
8101/8104 Gigabit Ethernet Controller. It contains a complete functional
description and includes complete physical and electrical specifications
for the 8101/8104.
The 8104 is functionally the same as the 8101, except that the 8104 is
in a 208-pin Ball Grid Array (BGA) package and the 8101 is in a 208-pin
Plastic Quad Flat Pack (PQFP) package
Audience
This document assumes that you have some familiarity with application
specific integrated circuits and related support devices. The people who
benefit from this book are:
Engineers and managers who are evaluating the 8101/8104 Gigabit
Ethernet Controller for possible use in a system
Engineers who are designing the 8101/8104 Gigabit Ethernet
Controller into a system
Organization
This document has the following chapters:
Chapter 1, Introduction
, describes the 8101/8104 Gigabit Ethernet
Controller, its basic features and benifits. This chapter also describes
the differences between the 8101 and 8104.
Chapter 2, Functional Description
, provides a high level
description of the 8101/8104 Gigabit Ethernet Controller.
iv
Preface
Copyright 20002001 by LSI Logic Corporation. All rights reserved.
Chapter 3, Signal Descriptions
, provides a description of the
signals used and generated by the 8101/8104 Gigabit Ethernet
Controller.
Chapter 4, Registers
, provides a description of the register
addresses and definitions.
Chapter 5, Application Information
, provides application
considerations.
Chapter 6, Specifications
, describes the specifications of the
8101/8104 Gigabit Ethernet Controller.
Abbreviations Used in This Manual
100BASE-FX
100 Mbit/s Fiber Optic Ethernet
100BASE-TX
100 Mbit/s Twisted-Pair Ethernet
10BASE-T
10 Mbit/s Twisted-Pair Ethernet
4B5B
4-Bit 5-Bit
BGA
Ball Grid Array
CLK
Clock
CRC
Cyclic Redundancy Check
CRS
Carrier Sense
CSMA
Carrier Sense Multiple Access
CWRD
Codeword
DA
Destination Address
ECL
Emitter-Coupled Logic
EOF
End of Frame
ESD
End of Stream Delimiter
FCS
Frame Check Sequence
FDX
Full-Duplex
FEF
Far End Fault
FLP
Fast Link Pulse
FX
Fiber
HDX
Half-Duplex
HIZ
High Impedance
I/G
Individual/Group
IETF
Internet Engineering Task Force
IPG
Interpacket Gap
IREF
Reference Current
L/T
Length and Type
LSB
Least Significant Bit
Preface
v
Copyright 20002001 by LSI Logic Corporation. All rights reserved.
MIB
Management Information Base
MLT3
Multilevel Transmission (3 levels)
MSB
Most Significant Bit
mV
millivolt
NLP
Normal Link Pulse
NRZI
Nonreturn to Zero Inverted
NRZ
Nonreturn to Zero
OP
Opcode
PCB
Printed Circuit Board
pF
picofarad
PRE
Preamble
R/LH
Read Latched High
R/LHI
Read Latched High with Interrupt
R/LL
Read Latched Low
R/LLI
Read Latched Low with Interrupt
R/LT
Read Latched Transition
R/LTI
Read Latched Transition with Interrupt
R/WSC
Read/Write Self Clearing
RFC
Request for Comments
RJ-45
Registered Jack-45
RMON
Remote Monitoring
SA
Start Address or Station Address
SFD
Start of Frame Delimiter
SNMP
Simple Network Management Protocol
SOI
Start of Idle
Split-32
Independent 32-bit input and output busses; one for
transmit and one for receive
SSD
Start of Stream Delimiter
STP
Shielded Twisted Pair
TP
Twisted Pair
H
microHenry
P
microprocessor
UTP
Unshielded Twisted Pair
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
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