8502
4-1
MD400157/D
1
98210
8502
44L PLCC
Top View
Pin Configuration
Features
s
Single Chip Connecting MII and AUI Interfaces
s
AUI Interface to Ethernet Transceiver
s
MII Interface to Ethernet Controller
s
MI Interface for Configuration & Status
s
Few External Components
s
Meets All Applicable IEEE 802.3 Standards
s
Interface to External E
2
PROM for Automatic
Preloading of MI Serial Port Bits
s
Many User Features and Options
- Full Duplex
- Powerdown
- Transmitter Disable/Powerdown
- Loopback
- MII Disable
- Link and Jabber Status Passthrough
- Multiple Register Access
s
LED Outputs
- Activity, Transmit, Receive
- Collision
- Link
- User Programmable
s
44L PLCC
8502
Ethernet MII to AUI
Interface Adapter
Description
The 8502 is a interface IC that provides a single chip link
between an Ethernet AUI (Attachment Unit Interface) and
an Ethernet MII (Media Independent Interface). The 8502
is in a 44L package.
The 8502 consists of Manchester encoder, AUI transmit-
ter, AUI receiver, Manchester decoder, Media Independ-
ent Interface (MII) to an external controller, and Manage-
ment Interface (MI) serial port.
The 8502 can access five 16 bit registers though the MI
serial port. These registers contain configuration inputs,
status outputs, and device capabilities.
The 8502 is ideal for external PHY's that connect AUI or
other media to MII. They are also ideal as an AUI interface
to MII based Ethernet controllers in adapter cards,
motherboards, and hubs.
10
9
8
7
11
15
14
13
12
16
17
RXD1
EE_DI
RXD0
EE_DO/RCV_LED
NC
COL
CRS
RX_DV
RX_CLK
EE_CLK/XMT_LED
21
20
19
18
22
26
25
24
23
27
28
NC
VCC2
CI
CI+
DI
DI+
RBIAS
NC
DO
DO+
GND2
44
1
2
3
43
4
5
6
42
41
40
TX_EN
MDC
GND1
NC
OSCIN
NC
RXD2
PLED1
VCC1
RXD3
PLED0
36
37
38
39
35
31
32
33
34
30
29
LINKI
MDIO
NC
EE_CS
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
8502
4-2
MD400157/D
2
8502 Table of Contents
1.0 Pin Description
2.0 Block Diagram
3.0 Functional Description
3.1 General
3.2 Media Independent Interface (MII)
3.2.1 General
3.2.2 MII Disable
3.3 Manchester Encoder
3.4 Manchester Decoder
3.5 AUI Transmitter
3.5.1 Transmitter
3.5.2 Transmit Activity Indication
3.5.3 Transmit Disable
3.5.4 Transmit Powerdown
3.6 AUI Receiver
3.6.1 Receiver
3.6.2 Squelch
3.6.3 Receive Activity Indication
3.7 Collision
3.7.1 General
3.7.2 Collision Detect Algorithm
3.7.3 Collision Indication
3.7.4 Collision Test
3.8 SOI (Start of Idle)
3.9 Full Duplex Mode
3.10 Loopback
3.11 Link
3.11.1 General
3.11.2 Link Algorithm
3.11.3 Link Indication
3.12 Jabber
3.13 Reset
3.14 Powerdown
3.15 Oscillator
3.16 LED Drivers
3.17 MI Serial Port
3.17.1 Signal Description
3.17.2 Timing
3.17.3 Multiple Register Access
3.17.4 Bit Types
3.17.5 Frame Structure
3.17.6 Register Structure
3.17.7 Link Status Bit
3.17.8 Jabber Detect Bit
3.18 Register Description
3.19 External EEPROM Interface (EEI)
3.19.1 General
3.19.2 Signal Description
3.19.3 Frame Structure
3.19.4 EE_CS Cycle Structure
3.19.5 Timing
4.0 Application Information
4.1 Example Schematics
4.2 AUI Transmit Interface
4.3 AUI Receive Interface
4.4 Controller Interface
4.4.1 General
4.4.2 Output Drivers
4.4.3 MII Disable
4.5 MI Serial Port
4.5.1 General
4.5.2 Multiple Register Access
4.5.3 Serial Port Addressing
4.6 Reset
4.7 External EEPROM
4.8 Oscillator
4.9 Programmable Led Drivers
4.10 Link Passthrough
4.11 Jabber Passthrough
4.12 Power Supply Decoupling
5.0 Specifications
8502
4-3
MD400157/D
3
Pin #
Pin Name
I/O
Description
44L
8502
2
VCC2
--
Positive Supply. +5 +/-5% Volts.
23
VCC1
1
GND2
--
Ground. 0 Volts.
24
GND1
25
DO+
O
AUI Transmit Output, Positive.
26
DO-
O
AUI Transmit Output, Negative.
19
DI+
I
AUI Receive Input, Positive.
20
DI-
I
AUI Receive Input, Negative.
21
CI+
I
AUI Collision Input, Positive.
22
CI-
I
AUI Collision Input, Negative.
28
RBIAS
--
Internal Bias Current Set. An external resistor connected between
this pin and GND will create a reference current for the internal
bias circuits.
43
OSCIN
I
Clock Oscillator Input. There must be either a 20 MHz crystal or a
20 MHz clock tied between this pin and GND. TX_CLK output clock
is generated from this input.
30
TX_CLK
O
Transmit Clock Output. This Media Independent Interface output
provides a clock to the controller. Transmit data from the controller
on TXD and TX_EN is clocked in on rising edges of TX_CLK and
OSCIN.
40
TX_EN
I
Transmit Enable Input. This Media Independent Interface input has
to be asserted active high to indicate that data on TXD is valid and
is clocked in on rising edges of TX_CLK and OSCIN.
34
TXD3
I
Transmit Data Input. These Media Independent Interface inputs contain
33
TXD2
input nibble data to be transmitted on the AUI outputs and are clocked in
32
TXD1
on rising edges of TX_CLK and OSCIN.
31
TXD0
13
RX_CLK
O
Receive Clock Output. This Media Independent Interface output
provides a clock to the controller. Receive data on RXD and RX_DV
is clocked out to the controller on falling edges of RX_CLK.
15
CRS
O
Carrier Sense Output. This Media Independent Interface output is
asserted when valid data is detected on the AUI inputs
and is clocked out on falling edges of RX_CLK.
14
RX_DV
O
Receive Data Valid Output. This Media Independent Interface output is
asserted active high when valid decoded data is present on the RXD
outputs and is clocked out on falling edges of RX_CLK.
3
RXD3
O
Receive Data Output. These Media Independent Interface outputs
6
RXD2
contain receive nibble data from the AUI input and are clocked out on
7
RXD1
falling edges of RX_CLK.
8
RXD0
1.0 Pin Description
8502
4-4
MD400157/D
4
1.0 Pin Description continued
Pin #
Pin Name
I/O
Description
44L
8502
16
COL
O
Collision Output. This Media Independent Interface output is asserted
when collision between transmit and receive data is detected.
41
MDC
I
Management Interface Clock Input. This Management Interface clock
shifts serial data into and out of MDIO on rising edges.
35
MDIO
I/O
Management Interface Data Input/Output. This bidirectional pin contains
serial Management Interface data that is clocked in and out on rising
edges of the MDC clock.
36
LINKI
I
Link Input. The value on this pin is either passed through to the internal
Pullup
MI serial port Link Status output bit In Register 1 or it enables the internal
To
Link algorithm.
VCC/2
1
= Link Status Bit Is Set To 0 (Link Fail)
float = Link Status Bit Determined By The Internal Link Algorithm
0
= Link Status Bit Is Set To 1 (Link Pass)
In 28L 8501, the Link Status Bit is always forced to 1 (Link Pass).
37
JABI
I
Jabber Input. The value on this pin is passed through to the internal MI
Pullup
serial port Jabber Detect output bit In Register 1.
1 = Jabber Detect Bit Is Set To 0 (No Jabber Detect)
0 = Jabber Detect Bit Is Set To 1 (Jabber Detect)
In 28L 8501, the Jabber Detect Bit is always forced to 0 (No Jabber Detect).
9
EE_CS
O
External EEPROM Chip Select Output. During powerup or reset, this
pin is a chip select output to an external EEPROM that can preload the
MI serial port input bits to values other than the defaults.
11
EE_CLK/
O
External EEPROM Clock Output/Transmit LED. During powerup or reset,
XMT_LED
this pin is serial data clock output to an external EEPROM that can preload the
MI serial port input bits to values other than the defaults. Data is shifted
in and out on EE_DI and EE_DO, respectively, on rising edges of
the EE_CLK clock.
During normal operation, this pin can be used as Transmit LED and can
drive an LED to GND.
0 = No Detect
1 = Transmit Activity Detected, On for 50 mS
10
EE_DI
I
External EEPROM Data Input. During powerup or reset, this pin is a
Pullup
data input from an external EEPROM that can preload the MI serial port
input bit to values other than the defaults.
12
EE_DO/
O
External EEPROM Data Output/Receive LED. During powerup or reset,
RCV_LED
this pin is a data output to an external EEPROM that can preload the MI
serial port input bit to values other than the defaults.
During normal operation, this pin can be used as Receive LED and can
drive an LED to GND.
0 = No Detect
1 = Receive Activity Detected, On for 50 mS
8502
4-5
MD400157/D
5
5
PLED1
I/O
Programmable LED Output/Management Interface Address Input. This
(MDA1)
O.D.
pin can be programmed through the MI serial port to be either a Collision
Pullup
Detect output or a user select output. This pin can drive an LED from VCC.
During powerup or reset, this pin is high impedance and the value on this pin
is latched in as an address for the MI serial port.
When programmed as Collision Detect Output:
1 = No Detect
0 = Collision Detected, On For 50 mS
4
PLED0
I/O
Programmable LED Output/Management Interface Address Input. This
(MDA0)
O.D.
pin can be programmed through the MI serial port to be either a Activity
Pullup
Detect output or a user select output. This pin can drive an LED from VCC.
During powerup or reset, this pin is high impedance and the value on this pin
is latched in as an address for the MI serial port.
When programmed as Activity Detect Output:
1 = No Detect
0 = Activity Detected, On For 50 mS
17
NC
--
No Connect. These pins are not connected but should be tied to GND to
18
minimize noise.
27
29
38
39
42
1.0 Pin Description continued
Pin #
Pin Name
I/O
Description
44L
8502
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