The
Communications
Company
TM
O V E R V I E W
The CW001100 processor core is a 200 MHz implementation of the popu-
lar ARM946E-STM, synthesized onto LSI Logic's G12P 0.18 micron high perfor-
mance process technology.
The ARM946E-S, which is based on the five stage pipeline ARM9E-S
TM
Harvard architecture processor, also contains a complete memory subsystem of
instruction and data caches (16 kBytes each), and configurable tightly coupled
instruction and data memories (TCMs). The core also includes an Embedded
Trace Macrocell (ETM) interface, and an AMBA
TM
(Advanced Microprocessor
Bus Architecture) AHB (Advanced High performance Bus) interface unit. This
high level of integration helps ease the task of integrating the core into your
System-on-Chip (SoC) design.
CW001100 - 200 MHz Synthesized
ARM946E-S
TM
Core with Cache Memories
ARM946E-S Block Diagram
F E A T U R E S A N D B E N E F I T S
200 MHz operating frequency
(worst case commercial conditions)
Implemented on LSI Logic's G12P
0.18 micron, 1.8 V process
1.9 mW/MHz power dissipation,
(with 0 kBytes TCMs)
ARM946E-S industry standard
architecture
16 kByte instruction and data
caches (4-way set associative)
Configurable TCMs
Synthesized core for optimal timing
accuracy and ASIC compatible
design flow
Regional ARM CoreWare design
support
The
Communications
Company
TM
The inclusion of both cache memories and TCMs gives this core the flexibility
to address a very broad range of system applications. The cache memories offer
a convenient cost-effective solution for handling applications with large memory
requirements, and the TCMs are ideal for highly deterministic code where
precise memory cycle counts are required. The AHB interface provides a write
buffer capable of burst transfers and split transactions. The ETM interface, when
used with the optional ETM core, provides extensive real-time trace capabilities.
The ARM946E-S has full support for the ARMv5TE instruction set including
all of the ARM9E-S family DSP instruction extensions. The core has full support
for both the ARM
32-bit and Thumb
16-bit instruction sets, making it
upwardly code-compatible with both the ARM7TDMI
TM
and ARM9TDMI
TM
families.
The ability to switch on the fly between ARM
and Thumb
instruction sets
allows the user to trade between high performance and code density.
The built in AMBA bus interface of the ARM946E-S core is an ideal stan-
dard bus for building a complete CPU subsystem design. LSI Logic offers both an
AMBA subsystem reference design, and a library of popular AMBA CPU
peripherals for use by customers on SoC designs. Customers can also incorporate
their own AMBA-based blocks into this widely used industry standard bus.
The ARM946E-S is supported by a wide array of software development
tools available from ARM Limited as well as third party vendors.
The core is implemented in LSI Logic's G12P high performance 0.18
micron (drawn) process, giving a maximum speed of 200 MHz (worst case
commercial conditions) and making it ideal for high performance applica-
tions. Power consumption for the core is 1.9 mW/MHz (including cache
memories but excluding TCMs).
The CW001100 core is synthesized onto the G12P SoC cell library and
is provided complete with highly accurate timing models that fully support
Static Timing Analysis (STA) through the core. This can be a significant benefit
for achieving timing closure on high performance designs. The core is fully
compatible with LSI Logic's entire FlexStream
TM
SoC ASIC design flow making
it straightforward to integrate into complex customer designs. The core comes
complete with built-in full scan chains for good testability, and is provided
with a comprehensive set of deliverables including design files, STA and
ATPG scripts, and detailed integration guidelines. To further assist customers
with their designs, LSI Logic provides specialized ARM CoreWare
integration
support through our team of regionally based field CoreWare engineers.
For more information please call:
LSI Logic Corporation
North American Headquarters
Milpitas, CA
Tel: 800 574 4286
LSI Logic Europe Ltd.
European Headquarters
United Kingdom
Tel: 44 1344 426544
Fax: 44 1344 481039
LSI Logic KK Headquarters
Tokyo, Japan
Tel: 81 3 5463 7165
Fax: 81 3 5463 7820
LSI Logic web site:
www.lsilogic.com
LSI Logic logo design, CoreWare and FlexStream
are registered trademarks and G12 is a trade-
mark of LSI Logic Corporation. ARM and Thumb
are registered trademarks of ARM Limited.
ARM966E-S, ARM9E-S, AMBA, ARM7TDMI, and
ARM9TDMI are trademarks of ARM Limited. All
other brand and product names may be trade-
marks of their respective companies.
LSI Logic Corporation reserves the right to make
changes to any products and services herein at
any time without notice. LSI Logic does not assume
any responsibility or liability arising out of the
application or use of any product or service
described herein, except as expressly agreed to in
writing by LSI Logic; nor does the purchase, lease,
or use of a product or service from LSI Logic con-
vey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual
property rights of LSI Logic or of third parties.
Copyright 2001 by LSI Logic Corporation.
All rights reserved.
Order No. R20050.A
1201.1k.SR.XX - Printed in USA
200 MHz ARM946E-STM Core
PDF 
ZIP