November 2000

DPS9245
High-Resolution ADC
with PGA

Datasheet

The DPS9245 is a versatile, analog front end that combines a high-
resolution 5 megasamples per second (MS/s) 16-bit Analog-to-Digital
Converter (ADC), a built-in reference, and a Programmable Gain
Amplifier (PGA) with resistive input impedance in a 44-pin package.

Figure 1

DPS9245 Block Diagram

The chip includes a digitally-calibrated, pipeline ADC that is calibrated
upon assertion of a simple reset signal. The combination of a low-noise,
high-linearity, high-input impedance buffer (with programmable gain),
wideband S/H, on-board voltage references, and simple digital interface
(16-bit parallel output word synchronous with the master sampling clock),
makes the chip extremely easy to use in a wide variety of systems. The
analog inputs should be driven differentially, and can be AC-coupled or
DC-coupled to a source. Typical applications include high-performance
data acquisition systems, automatic test equipment, and wideband digital
communications receivers present in systems such as wireless
basestations. The performance of the device with respect to linearity and
noise should be considered separately, as indicated by the THD and
SNR specifications provided in this document.

ADC

Low-Noise PGA

Differential

Analog In

(7 Settings)

OVR_RNG

REFCLK

VREF

(INP, INM)

GAIN[2:0]

RESETB

Data

S/H and

AD[15:0]

DPS9245 High-Resolution ADC with PGA

Features

16-bit 5 MS/s ADC with on-board voltage reference, programmable
gain amplifier and S/H

Minimal external components: one precision resistor and decoupling
capacitors

5 V peak-to-peak differential input range

Resistive inputs > 1 k

easy to drive, without any switched-

capacitor kickback transient

Low-frequency DNL:

0.5 LSB at 16 bits

Low-frequency INL:

1.25 LSB at 16 bits

Programmable gain amplifier preceding ADC with up to 20 dB of gain
(7 settings: 0dB, +3dB, +6dB, +12dB, +15dB, +18dB, +20dB)

PGA input-referred noise floor at peak gain: 8 nV/

Higher performance upgrade from AD9260, AD9240, AD9241, or
AD9243

5 V 5% power supply; 3.3-V supply for all digital I/O

User-programmable power dissipation depending on sample rate
and linearity required

230 mW at 2.5 MS/s

465 mW at 5 MS/s

44-pin LQFP plastic package

Operating temperature range:

C to +85

Electrical Specifications

Table 1

provides the electrical specifications for the DPS9245. Unless

otherwise stated, the following conditions apply:

Operating temperature range:

C to +85

VDD_ADC = VDDD_ADC = 5.0 V

VDD_ADIO = 3.3 V

DPS9245 High-Resolution ADC with PGA

5.0 MS/s

REXT = 1.43 kW

Table 1

Electrical Specifications

Parameter

Min

Typ

Max

Units

Notes/Conditions

Resolution

15.9

bits

See

"Digital Code Range and

Out-of-Range Detection,"
page 17

Maximum conversion rate

5.0

MS/s

Power Supplies

VDD_ADC, VDDD_ADC

4.75

5.0

5.25

VDD_ADIO

3.0

3.3

5.25

Supply for the ADC digital
outputs

VDD_ADC, VDDD_ADC
combined supply current

103

With REXT = 1.43 k

PGA Specifications

Input-referred noise floor

45.0

8.0

nV/

PGA gain = 0dB
PGA gain = 20dB
At frequencies > 300 kHz

PGA gain

0.0

GAIN[2:0] = 000

2.9

GAIN[2:0] = 001

5.8

GAIN[2:0] = 010

11.8

GAIN[2:0] = 011

14.8

GAIN[2:0] = 100

17.5

GAIN[2:0] = 101

19.5

GAIN[2:0] = 110

PGA gain accuracy

0.3

+0.3

Input resistance

On pins INP, INM

Input capacitance

On pins INP, INM

DPS9245 High-Resolution ADC with PGA

DC Specifications

ADC differential reference

2.375

2.5

2.625

Voltage between ADC_REFP
(pin 37) and ADC_REFM
(pin 36)

ADC positive reference

3.65

Voltage between ADC_REFP
(pin 37) and GND

ADC negative reference

1.15

Voltage between ADC_REFM
(pin 36) and GND

Input common mode refer-
ence (RXCMIN)

2.275

2.400

2.525

Minimum load 50 k

to ground

Gain Accuracy Specifications

Gain error

7.5

+7.5

%FSR

Total gain error of PGA and
ADC (using internal references)
compared to ideal quantizer
with perfect 5.0 V full-scale
range preceded by an ideal
PGA with gain equal to the
nominal values (i.e., 0 dB,
2.9 dB, 5.8 dB, 11.8 dB,
14.8 dB, 17.5 dB, 19.5 dB)

Static Linearity Specifications

DNL

0.5

LSB

At 16-bit level

INL

1.25

LSB

At 16-bit level

1. Not tested in production, but guaranteed by design or characterization.
2. In the remainder of this document, the PGA gains are often rounded to the nearest integer value.

For example, the GAIN[2:0] = 110 setting is referred to as 15 dB even though its typical value is
14.8 dB.

Table 1

Electrical Specifications (Cont.)

Parameter

Min

Typ

Max

Units

Notes/Conditions

DPS9245 High-Resolution ADC with PGA

Note:

For all digital outputs, the V

specification of VDD-0.5V

refers to the VDD_ADIO supply (pin 6). The exception is
the BUSYB output (pin 33), whose output HIGH level is ref-
erenced to the VDDD_ADC power supply (pins 3, 4).

Dynamic Linearity Specifications for Sinusoidal Differential Analog
(SDA) Input

Table 3

provides the dynamic linearity specifications for SDA input. The

conditions are:

VDD_ADC = VDDD_ADC = 5.0 V

VDD_ADIO = 3.3 V

REXT = 1.43 k

The following notes apply:

The signal level relative to full-scale (dBFS) is given at the ADC input
that is,

after the PGA in order to show the dependence on PGA

gain.

0 dBFS is 5.0V peak-to-peak differential.

Second harmonic distortion (HD2), 3rd harmonic distortion (HD3),
total harmonic distortion up to and including the 9th harmonic
(THD_9), and spurious free dynamic range (SFDR), are given in dB
below the fundamental (carrier).

Table 2

Digital I/O DC Electrical Characteristics

Parameter

Min

Typ

Max

Units

Notes/Conditions

(High-level output voltage)

VDD-0.5

At I

2 mA

(Low-level output voltage)

0.5

At I

= 2 mA

(Input leakage current)

+10

(High-level input voltage)

2.4

(Low-level input voltage)

0.8

DPS9245 High-Resolution ADC with PGA

Dynamic Linearity Specifications for Two-Tone Differential Analog Input

Table 4

provides the dynamic linearity specifications for two-tone

differential analog input. The following conditions apply:

VDD_ADC = VDDD_ADC = 5.0 V

VDD_ADIO = 3.3 V

REXT = 1.43 k

The following notes apply:

The composite signal level relative to full-scale (dBFS) is given at the
ADC input that is,

after the PGA in order to show the dependence

on PGA gain.

0 dBFS is 5.0V peak-to-peak differential.

Table 3

Dynamic Linearity Specifications for Sinusoidal Differential Analog Input

Sample

Rate

[MS/s]

Signal

Frequency

[kHz]

PGA

Setting

[dB]

Composite

Signal

Level at

ADC Input

[dBFS]

1. dBFS is dB below full scale signal level, which is 5 V peak-to-peak differential.

HD2

HD3

THD_9

SFDR

5.0

0.5

94 dB max

85 dB max

84 dB max

85 dB min

5.0

0.5

103 dB typ

97 dB typ

92 dB typ

94 dB typ

5.0

0.5

101 dB typ

93 dB typ

90 dB typ

92 dB typ

8.8

0.5

103 dB typ

97 dB typ

92 dB typ

94 dB typ

5.0

900

11.0

104 dB typ

97 dB typ

94 dB typ

97 dB typ

5.0

900

8.1

104 dB typ

94 dB typ

91 dB typ

94 dB typ

5.0

900

5.4

103 dB typ

88 dB typ

5.0

900

3.4

101 dB typ

85 dB typ

84 dB typ

85 dB typ

5.0

900

1.1

99 dB typ

84 dB typ

82 dB typ

84 dB typ

DPS9245 High-Resolution ADC with PGA

Third-order and 5th-order intermodulation distortion, IM3 and IM5
respectively, are given in dB below carrier that is, dB below one
tone of the two-tone signal.

SNR Specifications for Balanced Differential Analog Input

Table 5

provides SNR specifications for balanced differential analog

input. The following conditions apply:

5 MS/s

VDD = 5.0 V

VDD_ADIO = 3.3 V

Table 4

Dynamic Linearity Specifications for Two-Tone Differential Analog Input

Sample

Rate

[MS/s]

Signal

Frequencies

PGA

Setting

[dB]

Composite

Signal Level at

ADC Input

[dBFS]

IM3

IM5

4.4

100 kHz, 110 kHz

0.8

98 dB typ

101 dB typ

4.4

100 kHz, 110 kHz

0.3

96 dB typ

99 dB typ

8.8

100 kHz, 110 kHz

1.8

97 dB typ

8.8

100 kHz, 110 kHz

1.3

96 dB typ

98 dB typ

4.4

400 kHz, 410 kHz

0.7

94 dB typ

95 dB typ

4.4

400 kHz, 410 kHz

0.2

92 dB typ

95 dB typ

8.8

400 kHz, 410 kHz

1.8

93 dB typ

96 dB typ

8.8

400 kHz, 410 kHz

1.3

93 dB typ

96 dB typ

4.4

890 kHz, 900 kHz

1.9

89 dB typ

97 dB typ

8.8

890 kHz, 900 kHz

3.0

89 dB typ

98 dB typ

8.8

890 kHz, 900 kHz

1.4

87 dB typ

94 dB typ

5.0

1.03 MHz, 1.04 MHz

2.4

82 dB max

89 dB max

5.0

1.03 MHz, 1.04 MHz

2.4

87 dB typ

97 dB typ

5.0

1.03 MHz, 1.04 MHz

0.8

84 dB typ

95 dB typ

DPS9245 High-Resolution ADC with PGA

REXT = 1.43 k

Note:

Table 5

, the signal level is given both at the PGA input

(the chip input) and at the ADC input that is,

after the

PGA in order to show the dependence on PGA gain or
input signal level.

Extrapolated Dynamic Range (EDR) is a measure of overall converter
sensitivity. It is obtained from a plot of SNR versus signal amplitude at
the chip input, extrapolated to 0 dB. EDR can also be calculated for a
given scenario by adding the SNR to the amount in dB by which signal
level is below full scale.

Table 5

SNR Specifications for Balanced Differential Analog Input

Signal

Type

Signal

Frequency

[kHz}

PGA
Gain

[dB]

Composite

Signal Level

at PGA Input

[dBFS]

Composite

Signal Level

at ADC Input

[dBFS]

SNR

Extrapolated

Dynamic

Range

Sinusoid

78 dB min

79 dB min

Sinusoid

81 dB typ

82 dB typ

Sinusoid

19.5

20.5

76 dB typ

96.5 dB typ

Sinusoid

59.5

25 dB typ

84.5 dB typ

Sinusoid

19.5

40.5

38.5 dB typ

98.5 dB typ

Sinusoid

900

80 dB typ

81 dB typ

Sinusoid

900

45.5 dB typ

85.5 dB typ

DPS9245 High-Resolution ADC with PGA

DPS9245 Pinouts

Figure 2

provides a pinout diagram of the DPS9245.

Figure 2

DPS9245 Pinout Diagram

Pin Descriptions

Table 6

provides a functional definition of each signal pin listed in

numerical order.

DPS9245

44 Pin LQFP

Top View

VDD_ADC

GAIN0

INM

INP

GAIN1

RXCMIN

GND_ADC

ADC_REFP

ADC_REFM

REXT_RX

RXBGCAP

BUSYB
NC
NC
RESETB
GND_ADC
VDD_ADC
GAIN2
NC
OVR_RNG
AD15
AD14

GND_ADC

GNDD_ADC

VDDD_ADC
VDDD_ADC

GND_ADIO

VDD_ADIO

REFCLK

AD0
AD1
AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

10 mm X 10 mm

1.4 mm thick

DPS9245 High-Resolution ADC with PGA

Table 6

Pin Signal Functions

Pin Number

Pin Name

Type

Pin Function Description

1, 29, 38

GND_ADC

Analog ground

GNDD_ADC

Digital ground

3,4

VDDD_ADC

Digital +5.0 V supply

GND_ADIO

Ground for digital I/O

VDD_ADIO

Power supply for ADC outputs (+3.3 V or +5 V)

REFCLK

Master reference clock

Output enable (active HIGH)

9-24

AD0-AD15

Data output bits
AD0 is LSB; AD15 is MSB

OVR_RNG

Over range indicator bit (active HIGH)

No connect

27, 40, 43,

GAIN[2:0]

3-bit PGA gain control

28, 44

VDD_ADC

Analog +5.0 V supply

RESETB

Resets internal state of chip (active LOW)

31, 32

No connects

BUSYB

Initialization in progress indicator (active LOW)

RXBGCAP

External bias capacitor connection

REXT_RX

External bias resistor connection

36, 37

ADC_REFM,
ADC_REFP

ADC reference voltage outputs

RXCMIN

Common-mode reference voltage output

41, 42

INP, INM

Analog inputs to the ADC

1. Type definitions:

AI = analog input
AIO = analog I/O
AO = analog output

DI = digital input
DIO = digital I/O
DO = digital output
S = supply (VDD or GND)

DPS9245 High-Resolution ADC with PGA

IC Operation and Functionality

The following sections describe in greater detail the individual blocks and
functions of the DPS9245:

Overview

Chip Startup/Initialization Sequence

Analog Input Interfacing

External Connections

ADC Digital Output Timing

ADC References

Other ADC Functions

Programmable Gain Amplifier

Overview

The incoming analog differential signal (maximum level 5 V peak-to-peak
differential) enters the chip at the INP/INM pins. The analog signal path
is partitioned into a programmable gain amplifier (PGA) and an ADC. The
PGA has maximum gain of +20 dB; the gain is set by the digital control
signals GAIN[2:0]. The output of the PGA is fed directly to the ADC,
which samples at a rate equal to the REFCLK frequency and outputs a
16-bit wide parallel word.

The ADC uses a pipeline multistage architecture. Latency is 6 clock
cycles.

The chip requires a single low-jitter clock to be applied at the REFCLK
pin, with nominal 50% duty cycle. All clock generation is performed
internally and all converter and S/H clocks in the ADC path are directly
derived from REFCLK.

Chip Startup/Initialization Sequence

Warning:

This initialization sequence is

required. Without it, the chip

will not work.

DPS9245 High-Resolution ADC with PGA

Note that the analog blocks on the chip require significant time to power
on and come up to their quiescent dc states; for example, the voltage
reference power-on time depends on the value of the external reference
decoupling capacitance. Allowance may also be needed for thermal time
constants associated with the package/board.

On power-up, RESETB should be held LOW for at least three cycles of
the clock signal, REFCLK, as shown in

Figure 3

below. The power supply

voltages applied to the chip must be stable during this time. REFCLK
must be running for at least three clock cycles prior to the rising edge of
RESETB, and must continue running.

The initialization phase begins on the rising edge of RESETB. No more
than two full REFCLK cycles after the rising edge of RESETB, BUSYB,
an active LOW signal (pin 33), is driven LOW. An internal sequencer
performs the ADC calibration while BUSYB is LOW. When the
initialization is complete, BUSYB is driven HIGH and the chip is ready for
normal operation. The duration of the initialization phase, (the time
BUSYB is LOW) is 150 ms, assuming a 5 MS/s sampling rate.

Notes:

The digital output BUSYB cannot be 3-stated: it is always driven
either HIGH or LOW.

The REFCLK clock must be constantly running throughout the
initialization phase until BUSYB goes HIGH.

Initialization will restart whenever RESETB is cycled; thus, for
initialization to complete correctly, RESETB should not be cycled
while BUSYB is LOW.

Although typically the chip is initialized when power is first applied,
the initialization only occurs when the RESETB is cycled. There is
no "power-on-reset" circuitry on the chip.

DPS9245 High-Resolution ADC with PGA

Figure 3

Chip Initialization Timing

Analog Input Interfacing

The differential analog inputs (INP, INM) have a resistive input impedance
of 1k

minimum. For best performance, the input source should be

capacitively coupled into the chip, as shown below in

Figure 4

. To avoid

clipping, signal swing at the inputs should not exceed 5 V peak-to-peak
differential (2.5 V peak-to-peak single ended). The chip provides its own
common-mode voltage (on the pin marked RXCMIN), and the input
common mode is established internally.

Figure 4

Recommended Analog Input Interface Using An
AC-Coupling Approach

Alternatively, the inputs may be dc-coupled by using an external network
to reference the input common mode to the voltage on pin RXCMIN.

REFCLK

ADC

Outputs

RESETB

BUSYB

3 Cycles Min

Typically 0.15 s with

Calibration Ends

Calibration Starts

5 MHz REFCLK

AD[n]

AD[n+1] AD[n+2]

AD[n+5]

AD[n+4]

AD[n+3]

INP (41)

INM (42)

DPS9245

RXCMIN (39)

39 nF

Differential

Source

DPS9245 High-Resolution ADC with PGA

Output drive capability of RXCMIN is a maximum of 47

A (50 k

ground). Output impedance of the RXCMIN voltage reference is typically
1 k

and hence the 1

F decoupling capacitor should always be

present, as shown in

Figure 4

External Connections

The connections to the two pins {REXT_RX, RXBGCAP} are critical and
should be routed very carefully on the board. The connections are as
shown in

Figure 5

below. The traces to/from these pins should be as

short as possible.

Figure 5

Recommended Connection for Pins 3435

External Resistor (REXT)

REXT, shown in

Figure 5

above, sets the power dissipation of the chip

and may be used to trade off power dissipation against linearity at high
sample rates, and/or at high input frequencies. Nominally, at 5 MS/s,
REXT=1.43 k

is recommended. If linearity for large signal levels at an

analog bandwidth of 2 MHz is critical, the value should be decreased to
REXT=1.24 k

; and for even higher-frequency analog inputs,

REXT=1.0 k

can be used. At lower sample rates (for example 2 MS/s),

and lower analog input frequencies, the value may be increased to
REXT=2 k

. The section,

"Typical Performance Characteristics"

(on

page 18

) contains performance characteristics that show how dynamic

linearity depends on the REXT value.

REXT_RX (35)

RXBGCAP (34)

DPS9245

1.43 kW (1%)

F (X7R, Low ESR)

DPS9245 High-Resolution ADC with PGA

As a general guideline, REXT should always be in the range 800

2.5 k

. Contact LSI Logic for the most up-to-date recommended values

for a given application.

External Capacitor (CEXT)

CEXT is used only for noise filtering of an internal voltage associated
with the references. Its value is not critical. 1

F is recommended.

ADC Digital Output Timing

The chip implements a simple interface: the 16 ADC outputs appear on
the pins AD[15:0] as a parallel word synchronous with the ADC sampling
clock. AD0 is the LSB and AD15 is the MSB. The timing diagram for the
ADC digital outputs is shown in

Figure 6

. The ADC sampling clock is at

the same frequency as REFCLK.

Figure 6

Waveform for ADC Outputs

The data changes on the rising edge of REFCLK and can be latched by
a DSP on the falling edge. The latency through the ADC from the PGA
output to the digital outputs is 6 clock cycles of the ADC clock. The
voltage levels on the AD[15:0] lines are CMOS levels. The HIGH level is
determined by the power supply voltage on the VDD_ADIO pin, which
can be set independently of the other supply pins on the chip over the
range from 3.0 V to 5.25 V. Typically, VDD_ADIO should be +3.3 V, which
ensures that the ADC outputs are both TTL-compatible and 3.3 V-CMOS
compatible.

ADC References

The ADC full scale range is set by reference voltages generated on chip.
These two reference voltages appear on pins ADC_REFP and
ADC_REFM; nominally their difference is 2.5 V. The references are not
designed to be overdriven. The ADC_REFP and ADC_REFM pins

REFCLK

ADC

Outputs

ADC[n]

ADC[n+1]

DPS9245 High-Resolution ADC with PGA

Output Format

The output format of the ADC digital data is offset binary. Therefore, for
the nominal differential range of 5 V peak-to-peak differential, the
following values apply:

Digital Code Range and Out-of-Range Detection

Due to the calibration algorithm used, there is a slight loss in digital code
range from the ADC. So, instead of FFFFH and 0000H at the extremes
of the range, the actual maximum and minimum codes are less than that
by a few percentage points, and vary from chip to chip. Effectively, this
is a loss in dynamic range of a few tenths of a dB, and is negligible in
many applications. The out-of-range function is defined accordingly, and
sets the state of the active HIGH digital output, OVR_RNG, as follows:

OVR_RNG is HIGH if the ADC digital code is greater-than-or-equal-to
FC00H or less-than-or-equal-to 03FFH.

Programmable Gain Amplifier

From the block diagram in

Figure 1

, there is a programmable gain

amplifier (PGA), that precedes the ADC inputs. The differential inputs,
which are resistive, are at pins INP and INM. The maximum input range
is 5V peak-to-peak differential (2.5 V peak-to-peak single ended). To
achieve maximum overall system noise performance, the source driving
these inputs needs to be as low-noise as possible, while maintaining the
required distortion performance.

The internal 0 dB analog signal level and ADC full-scale reference level
is 5 V peak-to-peak differential (2.5 V peak-to-peak single ended). Thus,
if the ADC input level does not exceed 5 V peak-to-peak differential, the
PGA may be used to provide gain.

Output

Corresponds to

0000H

2.5 V differential

8000H

0 V differential

FFFFH

+2.5 V differential

DPS9245 High-Resolution ADC with PGA

The gain of the PGA can be programmed using a three bit control,
available at pins GAIN[2:0].

Table 7

provides a gain chart.

Important:

The GAIN[2:0] = 111 setting is not allowed. Note that the
input resistance is a function of the gain setting.

Typical Performance Characteristics

Figure 8

shows the Spurious Free Dynamic Range (SFDR), in dB below

the carrier, plotted as a function of ADC input amplitude, (post-PGA), in
dB below full scale, at 5 V and 25

The ADC sample rate is 10 MS/s

throughout. The data is given for sinusoidal inputs at 3 frequencies:
0.9 MHz, 2 MHz, and 3 MHz. For each frequency, the SFDR is given for
3 bias conditions: (i) low, using REXT = 1.43 k

;

(ii) medium, using

REXT = 1.24 k

, and (iii) high, using REXT = 1 k

. The corresponding

chip power supply currents for these three bias conditions are 96 mA,
109 mA, and 129 mA, respectively. Note that 0 dBFS corresponds to 5.0
V peak-to-peak differential.

Table 7

PGA Gain Control

GAIN2

GAIN1

GAIN0

Nominal PGA

Gain [dB]

Input

Resistance

]

Comments

5.57

Min. gain

4.65

3.97

2.23

1.66

1.25

1.00

Max. gain

Forbidden

DPS9245 High-Resolution ADC with PGA

Figure 11

shows a zoomed-in portion of the ADC output spectrum for a

890 kHz/900 kHz two-tone input, at 25

C. The sample rate is 4.4 MS/s;

at the ADC input (i.e., post PGA) the signal level of each tone is 8.0
dBFS and the composite signal level is

2.0 dBFS; REXT = 1.43 k

; the

PGA is set to 6 dB. The spectrum is generated by averaging multiple
FFTs in order to indicate clearly the intermodulation distortion products.

Figure 11

Zoomed-in Portion of ADC Output Spectrum
(890/900 kHz Two-Tone Input)

800

820

840

860

880

900

920

940

960

980

1000

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

Frequency [kHz]

[dBFS]

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Alpharetta
Tel: 770.753.6146
Fax: 770.753.6147

Illinois
Oakbrook Terrace
Tel: 630.954.2234
Fax: 630.954.2235

Kentucky
Bowling Green
Tel: 270.793.0010
Fax: 270.793.0040

Maryland
Bethesda
Tel: 301.897.5800
Fax: 301.897.8389

Massachusetts
Waltham

Tel: 781.890.0180
Fax: 781.890.6158

Burlington - Mint Technology
Tel: 781.685.3800
Fax: 781.685.3801

Minnesota
Minneapolis

Tel: 612.921.8300
Fax: 612.921.8399

New Jersey
Red Bank
Tel: 732.933.2656
Fax: 732.933.2643

Cherry Hill - Mint Technology
Tel: 856.489.5530
Fax: 856.489.5531

New York
Fairport
Tel: 716.218.0020
Fax: 716.218.9010

North Carolina
Raleigh
Tel: 919.785.4520
Fax: 919.783.8909

Oregon
Beaverton
Tel: 503.645.0589
Fax: 503.645.6612

Texas
Austin
Tel: 512.388.7294
Fax: 512.388.4171

Plano

Tel: 972.244.5000
Fax: 972.244.5001

Houston
Tel: 281.379.7800
Fax: 281.379.7818

Canada
Ontario
Ottawa

Tel: 613.592.1263
Fax: 613.592.3253

INTERNATIONAL

France
Paris
LSI Logic S.A.
Immeuble Europa

Tel: 33.1.34.63.13.13
Fax: 33.1.34.63.13.19

Germany
Munich
LSI Logic GmbH

Tel: 49.89.4.58.33.0
Fax: 49.89.4.58.33.108

Stuttgart

Tel: 49.711.13.96.90
Fax: 49.711.86.61.428

Italy
Milan
LSI Logic S.P.A.

Tel: 39.039.687371
Fax: 39.039.6057867

Japan
Tokyo
LSI Logic K.K.

Tel: 81.3.5463.7821
Fax: 81.3.5463.7820

Osaka

Tel: 81.6.947.5281
Fax: 81.6.947.5287

Korea
Seoul
LSI Logic Corporation of
Korea Ltd
Tel: 82.2.528.3400
Fax: 82.2.528.2250

The Netherlands
Eindhoven
LSI Logic Europe Ltd
Tel: 31.40.265.3580
Fax: 31.40.296.2109

Singapore
Singapore
LSI Logic Pte Ltd
Tel: 65.334.9061
Fax: 65.334.4749

Sweden
Stockholm
LSI Logic AB

Tel: 46.8.444.15.00
Fax: 46.8.750.66.47

Taiwan
Taipei
LSI Logic Asia, Inc.
Taiwan Branch
Tel: 886.2.2718.7828
Fax: 886.2.2718.8869

United Kingdom
Bracknell
LSI Logic Europe Ltd

Tel: 44.1344.426544
Fax: 44.1344.481039

Sales Offices with
Design Resource Centers

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DPS9245

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DPS9245

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DPS9245