80C24
1
MD400119/J
80C24
AutoDUPLEX
TM
CMOS Ethernet Interface Adapter
96345
MCC and AutoDUPLEX are trademarks of SEEQ Technology, Inc.
General Description
The SEEQ 80C24 is a CMOS single chip Ethernet serial
interface adapter with a completely integrated Manchester
Code Converter (MCC), AUI & 10Base-T transceiver with
wave shaping & filters eliminating the need for external
filters. The 80C24 is designed to interface directly with
SEEQ's family of Ethernet data link controllers- 8003,
80C03, 8005, 80C04, Intel, AMD & National's controllers.
The chip provides automatic polarity correction, automatic
port selection, support for cables longer than 100m, UTP/
STP cable selection, power down mode, separate analog
& digital ground pins & a link disable feature. It also
provides a selectable coded link pulse to implement Au-
toDUPLEX function together with SEEQ's 80C03, 80C04
& NCORE controllers allowing seamless full duplex opera-
tion in switched network implementations doubling net-
work bandwidth to 20 Mbps in 10Base-T. The 80C24 is
typically suitable for adapter boards, motherboards and
stand-alone TP transceiver designs & switching hubs.
Functional Features
s
Low Power CMOS Technology Ethernet Serial
Interface Adapter with Integrated Manchester
Code Converter (MCC
TM
), AUI and 10Base-T
Transceiver with Output Wave Shaping and on
chip filters.
s
Meets IEEE 802.3 10Base-5, 10Base-2, 10Base-T
Standards
s
Direct Interface to SEEQ, INTEL, AMD &
NATIONAL LAN Controllers
s
Automatic or Manual Selection of AUI/10Base-T
Interface
s
Provides AutoDUPLEX
TM
Detect Function for
SEEQ LAN Controllers and Doubles Bandwidth
to 20 MBits/sec for Switched Networks
s
Status Indicators: Link, Transmit & Receive,
Port Selection-AUI/TP, TP Cable Polarity
s
Diagnostic Loopback Support
s
Power On Reset with Power Down Mode to
Conserve System Power
s
Separate Analog/Digital Power and Ground Pins
to Minimize Noise
Interface Features
s
Meets IEEE 10Base-T Standards and IEEE 802.3
standards for AUI.
s
On Chip Transmit Wave Shaping and Low Pass
Filter Circuits - No External Filters Required
s
Selectable Termination Impedance to Support
UTP and STP Cables, (100 ohms, 150 ohms)
s
Long Cable Mode Support > 100 Meters
s
Automatic Polarity Correction
s
Link Integrity Test Disable, Selectable Coded
Link Pulse for AutoDUPLEX Mode
s
Low differential and common mode noise on TP
transmit outputs.
s
Differential Transmit Drivers to support 50 Meters
of AUI Cable Lengths.
s
Direct AUI interface to the Manchester Code
Converter.
Note: Refer to Appendix B for the
Thin Quad Flat Package (TQFP).
Pin Configuration
80C24
TOP VIEW
PLCC
CSN
4
3
2
1
44
43
42
41
40
5
PDN
MODE 1
AUI/APT
GND
UTP/STP
APOL
LONG
7
8
9
10
11
12
13
14
15
16
17
LNK_DIS
6
TP/APT
18
19
20
21
22
23
24
25
26
27
28
39
38
37
36
35
34
33
32
31
30
29
FDPLX_DET
SQE_DIS/LPBK/FDPLX
FLTR_DIS
TPO
TPO+
TXC
COLL
X1
X2
RXC
RXD
BIAS_RES
TPI+
TPI
TXEN
TXD
V
ADPLX/JAB_DIS
MODE 2
CI
CI+
RX
RX+
TX
TX +
AUI_TP_LED
LNK_LED
TX_RX_LED
GND
4
V
CC4
V
CC3
GND
3
GND
2
V
CC2
1
CC1
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
80C24
2
MD400119/J
Pin
Name
I/O
Description
1
V
CC1
--
Power supply pin. +5V
5%.
2
AUI/APT
Input
AUI Port/autoport select input.
Pulldown
[1]
AUI/APT TP/APT
0
0
Automatic port selection enabled when LNK_DIS=1
0
1
TP port selected
1
0
AUI port selected
1
1
Invalid
3,4
MODE2,
Inputs
Controller interface mode select input. These pins
MODE1
Pulldown
select one of four possible controller interfaces.
Controller
MODE2
MODE1
SEEQ
0
0
NSC
0
1
INTEL
1
0
AMD
1
1
5
PDN
Input
Powerdown input. When PDN = 0, all functions are disabled
Pulldown
and power consumption is reduced to a minimum.
6
TP/APT
Input
TP Port/autoport select input. See AUI/APT.
Pullup
[2]
7
TX+
Output
AUI transmit output, positive.
8
TX
Output
AUI transmit output, negative.
9
V
CC4
--
Power supply pin. +5V
5%.
10
GND
4
--
Ground pin.
11
CI
Input
AUI collision input, negative.
12
CI+
Input
AUI collision input, positive.
13
RX
Input
AUI receive input, negative.
14
RX+
Input
AUI receive input, positive.
15
AUI_TP_LED
Output
Port select indication output. This pin is an open drain output
and is capable of driving an LED from V
CC
. This pin also
indicates reverse polarity on the twisted pair inputs by blinking
on and off when the polarity is reversed.
AUI_TP_LED
= High Z
AUI port selected.
=
0
TP port selected.
16
TX_RX_LED
Output
Transmit and receive activity output. This output goes low and stays
low for a minimum of 0.2 sec, when there is packet transmission or
reception on the TP or AUI port. This pin is an open drain output and is
capable of driving an LED from V
CC
.
80C24 Pin Description
[1] Pulldown indicates that the pin is pulled down internally so that the default state is low.
[2] Pullup indicates that the pin is internally pulled up so that the default state is high.
80C24
3
MD400119/J
Pin
Name
I/O
Description
17
LNK_LED
Output
Link pulse detect output. When LNK_LED = 0, link pulse is
detected on twisted pair receive input. This pin is an open
drain output and is capable of driving an LED from V
CC
.
18
FDPLX_DET
Output
Full duplex detect output. When FDPLX_DET = 0, the device
has been placed in the full duplex mode by either selection or by
the AutoDUPLEX feature.
19
CSN
Output
Carrier sense output. This controller interface output indicates
valid data and collisions on the receive TP or AUI inputs.
20
TXC
Output
Transmit clock output. This controller interface output provides
a 10MHZ clock to the controller. Transmit data from the controller
on TXD is clocked in on edges of TXC.
21
COLL
Output
Collision output. This controller interface output is asserted
when collision between transmit and receive data is occuring,
and during SQE test.
22
V
CC3
--
Power supply pin. +5V
5%.
23
GND
3
--
Ground pin.
24
X2
Output
Crystal oscillator output. The master clock for the device is
generated by either placing a crystal between X1 and X2, or
by applying an external clock to X1.
25
X1
Input
Crystal oscillator input. The master clock for the device is
generated by either placing a crystal between X1 and X2, or by
applying an external clock to X1.
26
RXC
Output
Receive clock output. This controller interface output provides
a 10MHZ clock to the controller. Receive data on RXD is
clocked out on edges of RXC.
27
RXD
Output
Receive data output. This controller interface output contains
receive data decoded from the receive TP/AUI inputs and is
clocked out on edges of RXC.
28
LNK_DIS
Input
Link disable input. When LNK_DIS = 0, link pulse functions
Pullup
are disabled; that is, no link pulses are transmitted on
TP outputs, link pulse detection on receive TP inputs ignored.
29
TXD
Input
Transmit data input. This controller interface input contains
data to be transmitted on either TP or AUI transmit outputs and
is clocked in on edges of TXC.
30
TXEN
Input
Transmit enable input. This controller interface input has to be
asserted when data on TXD is valid.
31
TPI
Input
Twisted pair receive input, negative.
32
TPI+
Input
Twisted pair receive input, positive.
33
GND
2
--
Ground pin.
34
V
CC2
--
Power supply pin. +5V
5%.
Pin Description
cont'd
80C24
4
MD400119/J
Pin
Name
I/O
Description
Pin Description
cont'd
35
TPO+
Output
Twisted pair transmit output, positive.
36
TPO
Output
Twisted pair transmit output, negative.
37
BIAS_RES
Output
Bias resistor set. A resistor tied between this pin and A
GND
sets the twisted pair transmit peak output current level on
TPO
.
38
SQE_DIS/
Input
SQE disable/loopback/full duplex enable input. This pin has three
LPBK/
Pullup
distinct functions. The pin is configured as one of the first two
FDPLX
functions, SQE_DIS and LPBK, depending on whether TP or AUI
port is selected.
IF TP PORT IS SELECTED AND LNK_DIS = 1
SQE_DIS =
1 SQE test enabled
=
0 SQE test disabled
IF AUI PORT IS SELECTED AND LNK_DIS = 0
LPBK
=
1 Loopback disabled
=
0 Loopback enabled
This pin can be configured as the third function, FDPLX, by setting
AUI/APT = 0, TP/APT = 0. LNK_DIS = 0, FDPLX = 1. This pin
combination forces the device into the full duplex mode. It is important
to note that the link pulses will be present even though the LNK_DIS
pin is held low. This happens only in this particular mode.
39
FLTR_DIS
Input
Filter disable input. When FLTR_DIS=1, the internal transmit
Pulldown
and receive filters are disabled.
40
ADPLX/
Input
Autoduplex enable/jabber disable input. This pin changes
JAB_DIS
Pullup
function depending on whether TP or AUI port is selected.
IF TP PORT IS SELECTED AND LNK_DIS = 1
ADPLX
= 1 Half duplex selected
= 0 Autoduplex on
IF AUI PORT IS SELECTED AND LNK_DIS = 0
JAB_DIS
= 1 Jabber enabled
= 0 Jabber disabled
41
LONG
Input
Long cable mode input. When LONG = 0, the receive input
Pullup
thresholds are reduced to accomodate cable lengths in
excess of 100 meters.
42
APOL
Input
Autopolarity input. When APOL = 1, this pin enables the
Pulldown
autopolarity function and automatically corrects for reversed
polarity on the twisted pair receive inputs, TPI
.
43
UTP/STP
Input
Cable type select input. This pin adjusts the twisted pair
Pullup
transmit output current level to accomodate either 100 ohm
(UTP) or 150 ohm (STP) cable.
UTP/STP
= 1 100 ohm cable (UTP)
= 0 150 ohm cable (STP)
44
GND
1
--
Ground pin.
80C24
5
MD400119/J
BLOCK DESCRIPTION
Functional Description
The 80C24 is an Ethernet adapter with a completely
integrated Manchester Code Converter, 10Base-T trans-
ceiver with on chip filters. The device contains both
10Base-T and AUI interfaces compliant with IEEE 802.3
specifications. The chip is divided into four major blocks,
namely (i) The controller interface (ii) The Encoder /
Decoder (iii) The twisted pair interface and (iv) The AUI.
The input signals are received on the TP or AUI receivers
depending on which is selected. Both the twisted pair and
AUI receivers contain a threshold comparator to validate
the signal and a zero crossing comparator for checking the
transitions. Then the data is sent to the PLL in the decoder
to separate the data from the clock. On the other side,
digital transmit data is clocked into the device via the
controller interface. The data is then sent to the Manch-
ester encoder to be encoded. Encoded data is then trans-
mitted on the twisted pair or AUI based on the selected
port.
The Controller Interface
The 80C24 is designed to interface directly to SEEQ's
80C03, 80C04 & NCORE controllers, INTEL's 82586/596/
592/593 LAN controllers, NSC and AMD's controllers with
the use of MODE1 & MODE2 pins . The controller interface
consists of the Transmit/Receive data (TXD/RXD), trans-
mit/receive Clocks (TXC/RXC), the Transmit Enable
(TXEN) input, the collision output (COLL), the Full Duplex
acknowledgment (FDPLX_DET) and the Carrier Sense
Output (CSN) pins. On the transmit side, data on TXD is
clocked into the device on the edges of TXC clock output
only when the data valid signal (TXEN) is asserted. On the
receive side, data on RXD is clocked out on edges of RXC.
In the SEEQ, NSC and AMD modes, RXC follows TXC for
2.2
s in the TP mode or 1.8
s in the AUI mode and then
switches to the recovered clock. In the Intel mode, RXC is
held low for 2.2
s in the TP mode or 1.8
s in the AUI mode
while the PLL is acquiring lock and then switches to the
recovered lock. The FDPLX_DET pin signifies to the
controller that full duplex channels have been established.
The following mode table illustrates the selection of the
appropriate inputs to match the controller.
MODE 2
MODE 1
Controller
0
0
SEEQ
0
1
NSC
1
0
INTEL
1
1
AMD
The Encoder/Decoder
Manchester encoding is a process of combining the clock
& the data stream together so that they can be transmitted
on the twisted pair interface or AUI at the transceiver side.
Once encoded, the first half contains the complement of
the data and the second half contains the true data, so that
a transition is always guaranteed at the middle of a bit cell.
Data encoding and transmission begins with TXEN going
active, and the subsequent data is clocked on the edges
of TXC and then gets encoded. The end of a transmit
packet occurs at a bit cell center if the last bit is a "ONE" or
at a bit boundary if the last bit is a "ZERO".
The decoding is a process of recovering the encoded data
stream coming from the receiver side and decoding it back
into the clock and data outputs using the phase locked loop
technique. The PLL is designed to lock into the preamble
of the incoming signal at less than 20 bit times with a
maximum jitter of
13.5 ns at the TPI or AUI inputs and can
also sample the incoming data with this amount of jitter.
The ENDEC asserts the CSN signal to indicate to the
controller that the data and clock received are valid and
available. There is an inhibit period after the end of a frame
after a node has finished transmitting for 4.4
s during
which CSN is deasserted irregardless of the state of the
receiver and collision status.
Twisted Pair Interface
(a) The transmitter function
The transmitter transfers Manchester encoded data from
the ENDEC to the twisted pair cable. The circuit consists
of a set of functional blocks to provide pre-coded wave-
shaped, pre-equalized and smoothed waveforms so that
the outputs are made to appear as though it had passed
through a 5-7th order external elliptic passive filter, thereby
eliminating the need for an external filter. The waveform
generator consists of a ROM, DAC, PLL, filter and a output
driver to preshape the output waveform transmitted onto
the twisted pair cable to meet the pulse template require-
ments outlined in IEEE STD 802.3 and illustrated in figure
12. The DAC first converts the data pulse into a stair
stepped representation of the desired output waveform,
which goes through a second order low-pass filter. The
DAC values are determined from the ROM addresses,
which are chosen to have different values for long and
short data bits so as to shape the pulse to meet the
10Base-T waveform template. The line driver takes the
smoothed current waveform and converts it into an high
current output that can drive the TP directly without any
external filters. The current output is also guaranteed to
have a very low common mode and differential noise. The
interface to the twisted pair cable requires a transformer
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