LSI403Z Digital Signal Processor
O V E R V I E W
The LSI403Z is a low power 16-bit fixed-point digital signal processor (DSP)
based on the LSI Logic ZSP400 DSP core. The device has been designed for
applications requiring high throughput and flexibility coupled with a high speed
I/O, such as Voice over Networks CPE/IAD devices and audio applications. The
LSI403Z is capable of a maximum clock rate of 150 MHz for 600 MIPS peak
performance and sustained effective throughput of 300 DSP MIPS (MACs). The
device is also software compatible with all other products in the ZSP architecture,
and offers an unrivalled combination of code density, performance and ease of use.
M E M O R Y
The internal memory structure of the LSI403Z comprises of 16K words of
on-chip instruction memory, 16K words of on-chip data memory, 2K words on-
chip boot ROM, and on-chip peripherals. Additionally, the boot ROM provides
start-up and self-test capabilities. Both synchronous and asynchronous devices
are supported including sync-burst SRAM. The external memory is logically
segmented into instruction, data, and peripheral spaces.
D M A
The DMA controller of the LSI403Z supports zero-overhead instruction or data
transfers to or from the entire 32K words of internal RAM to the memory interface
unit, host processor interface, or serial ports. The eight DMA channels are
segmented between four "indexed" and four "non-indexed" channels. Indexed
channels have the ability to multiplex and de-multiplex data. Indexed channels can
also operate in non-indexed mode.
F E A T U R E S
150 MHz operation at 1.8V
2 high-speed serial/TDM ports
(T1/E1 framer, H.100/H.110 bit
stream compatible)
Low power modes
32K words on-chip RAM, 2K
words on-chip ROM
8-channel DMA controller
On-board PLL for clock generation
32-/16-bit external memory interface
2 on-board timers
IEEE 1149.1-compliant JTAG port
for real-time emulation
B E N E F I T S
300 MMAC sustained DSP
performance at 150 MHz
Direct interfacing to standard
telecommunications interfaces,
reducing system cost
High data throughput without
processor overhead
Low power per channel
Flexibility to optimize power
consumption
High data bandwidth to off-chip
devices
RTOS support and increased
system integration
Low overhead on chip debug
Ideal for Voice over DSL IAD designs
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MAC 1
MAC 2
ALU 2
ALU 1
Register File
PPL
Boot ROM
Program
Memory
16Kx16
Data
Memory
16Kx16
DMA
MXU
Load/Store Buffer
Xbus
Serial Port 0 Serial Port 1 HPI
PIO
Pipeline
Control
Unit
Data Unit
D-Cache
Instruction Unit
I-Cache
Bus I/F Unit
ICU
DEU
JTAG
DSP Core
64b
32b
64b
32b
64b
64b
32b
Figure 1. LSI403Z Functional Block Diagram
Z S P
T M
A R C H I T E C T U R E P E R F O R M A N C E W I T H H I G H - E N D I N T E G R AT I O N
LSI403Z Digital Signal Processor
T I M E R S
The LSI403Z has two identical 16-bit on board timers for real-time interrupt
generation. Each timer is fully programmable, and has a 6-bit prescaler and
interrupt capability. The timers can automatically reload with the initial count so
that periodic interrupts can be generated.
T D M S E R I A L P O R T S
The LSI403Z provides two identical synchronous serial ports that support
8- or 16-bit active or passive transfers, which can be either burst or continuous.
It a maximum transfer rate in either active or passive mode of one-half the
processor clock rate. Both serial ports provide the programmable feature of a
TDM (time division multiplex) mode that is compatible with T1/E1 framers or
the local serial bus of H.100/H.110 interface devices. The TDM mode can
also be used to establish a serial multiprocessor communication link with only
three signals.
H O S T P R O C E S S O R I N T E R F A C E ( H P I )
The Host Processor Interface, or HPI, is an asynchronous 8-bit parallel port
that is used to interface with off-chip devices. It is compatible with both
Motorola and Intel style memory interfaces, and supports word transfers. The
maximum transfer rate for the HPI is one-forth of the processor clock frequency.
D E V E L O P M E N T T O O L S
The LSI403Z is fully supported by both LSI Logic and third party
commercial tools. LSI Logic provides a GNU-based compiler, linker and
assembler available for Windows and Solaris platforms. The compiler supports
C fixed-point data types and employs a variety of C intrinsic functions. Also
supported is a full commercial tool chain from GreenHills Software and Corelis
JTAG debug tools. The ZSP architecture enables the C compiler to produce
code unrivaled in code density and execution speed by any DSP in its class,
offering a fast time to market with optimal performance and cost.
An LSI403Z evaluation board, the EB403, is available offering the
following features:
32-bit PCI interface provides JTAG debug capabilities
16-bit A/D converter on board
Reference board with the ability to handle multiple voice channels
Programmable Gain Amplifier
For more information please call:
LSI Logic Corporation
North American Headquarters
Milpitas, CA
Tel: 800 574 4286
LSI Logic Europe Ltd.
European Headquarters
United Kingdom
Tel: 44 1344 426544
Fax: 44 1344 481039
LSI Logic KK Headquarters
Tokyo, Japan
Tel: 81 3 5463 7165
Fax: 81 3 5463 7820
LSI Logic web site
www.lsilogic.com
LSI Logic logo design, is a registered trademark of
LSI Logic Corporation. All other brand and product
names may be trademarks of their respective
companies.
LSI Logic Corporation reserves the right to make
changes to any products and services herein at any
time without notice. LSI Logic does not assume any
responsibility or liability arising out of the
application or use of any product or service
described herein, except as expressly agreed to in
writing by LSI Logic; nor does the purchase, lease,
or use of a product or service from LSI Logic
convey a license under any patent rights,
copyrights, trademark rights, or any other of the
intellectual property rights of LSI Logic or of third
parties.
Copyright 2001 by LSI Logic Corporation.
All rights reserved.
Order No. R20034
301.1k.SR.LT - Printed in USA
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