Электронный компонент: LSI53C040

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DB14-000125-02

LSI53C040
Enclosure Services
Processor

TECHNICAL

MANUAL

J u n e 2 0 0 2

Version 2.7

ii

This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.

Document DB14-000125-02, Fourth Edition (June 2002)
This document describes the LSI Logic LSI53C040 Enclosure Services
Processor and will remain the official reference source for all revisions/releases
of this product until rescinded by an update.

LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.

Copyright � 1998�2002 by LSI Logic Corporation. All rights reserved.

TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, LVDlink, and TolerANT are trademarks or registered
trademarks of LSI Logic Corporation. MCS is a registered trademark of Intel
Corporation. All other brand and product names may be trademarks of their
respective companies.

DB

To receive product literature, visit us at http://www.lsilogic.com.

For a current list of our distributors, sales offices, and design resource
centers, view our web page located at

http://www.lsilogic.com/contacts/na_salesoffices.html

Preface

iii

Preface

This technical manual provides reference information on the LSI53C040
Enclosure Services Processor. It contains a complete functional
description for the product and includes complete physical and electrical
specifications for it.

Audience

This manual assumes some prior knowledge of current and proposed
SCSI, Inter-Integrated Circuit, and SFF-8067 standards, including the
SAF-TE and SES standards for parallel SCSI devices, as well as a
detailed understanding of serial data communication. It is intended for
system designers who are using this device to manage SCSI or Fibre
Channel peripheral device enclosures.

Organization

This document has the following chapters and appendix:

�

Chapter 1, Introduction

, contains general information about the

LSI53C040, including an overview of its features and functions.

�

Chapter 2, Functional Description

, describes the main functions of

the chip in more detail, including the major interfaces.

�

Chapter 3, Signal Descriptions

, contains the pin diagrams and

descriptions of each signal.

�

Chapter 4, SCSI and DMA Registers

�

Chapter 5, SFF-8067 Registers

�

Chapter 6, Two-Wire Serial Registers

�

Chapter 7, Miscellaneous Registers

�

Chapter 8, System Registers

iv

Preface

�

Chapter 9, Electrical Characteristics

, contains the operating

conditions and AC timings for the chip and mechanical drawings.

�

Appendix A, Register Summary

Related Publications

For background information, please contact:

ANSI
11 West 42nd Street
New York, NY 10036
(212) 642-4900
Ask for document number X3.131-199X (SCSI-2)

Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
(800) 854-7179 or (303) 397-7956 (outside U.S.) FAX (303) 397-2740
Ask for document number X3.131-1994 (SCSI-2); X3.253 (SCSI-3
Parallel Interface); or NCITS 305-199x (SCSI-3 Enclosure Services
(SES) Specification working draft)

SCSI Accessed Fault-Tolerant Enclosures (SAF-TE) Specification
This document can be downloaded from www.safte.org

LSI Logic World Wide Web Home Page
www.lsilogic.com

SFF-8067 Specification
ENDL Fax Access
(408) 741-1600 (call from a FAX machine)

Inter-Integrated Circuit Bus Specification
For general information about the Inter-Integrated Circuit bus, contact
Philips Semiconductors at www.semiconductors.philips.com

Conventions Used in This Manual

The first time a word or phrase is defined in this manual, it is italicized.

Preface

v

The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive. Signals that are active
LOW end in a "/."

Hexadecimal numbers are indicated by the prefix "0x" --for example,
0x32CF. Binary numbers are indicated by the prefix "0b" --for example,
0b0011.0010.1100.1111.

Revision Record

Page No.

Date

Remarks

all

April 1998

Initial Release

all

December 1998

Preliminary, Version 2.0

all

February 2000

Version 2.5

all

April 2001

Version 2.6. All product names changed from SYM to
LSI. Updated DC electrical specifications and test
conditions.

Front Cover, page ii,
pages 9-25 and 9-26

June 2002

Version 2.7. Replaced PZ package mechanical
drawing with P3 package mechanical drawing, pages
9-25 and 9-26.

Document Outline

• Chapter1 Introduction
  • 1.1 LSI53C040 Overview
  • 1.2 SCSI Mode
    • Figure1.1 SCSI/SAF-TE Enclosure Implementation
  • 1.3 SFF-8067 Mode
    • Figure1.2 SFF-8067/SES Enclosure Implementation
  • 1.4 Features Summary
• Chapter2 Functional Description
  • Figure2.1 LSI53C040 Block Diagram
  • 2.1 Functional Blocks
    • 2.1.1 LSI53C80-Based SCSI Control Logic
    • 2.1.2 80C32 Microcontroller Core
    • 2.1.3 Two-Wire Serial Interface
    • 2.1.4 SFF-8067 Interface
    • 2.1.5 16 Kbytes SRAM
    • 2.1.6 DMA Function
  • 2.2 Memory Map
    • Figure2.2 LSI53C040 Memory Map
  • 2.3 SCSI Core Operation
    • 2.3.1 Recommended Use of SCSI High ID Pins
      • Figure2.3 Initiating Arbitration and Selection/Reselection
    • 2.3.2 LVDlink� Technology
      • Figure2.4 LVD Resistor Value
    • 2.3.3 Programmed I/O Transfers
      • Figure2.5 Programmed I/O Target Transfers
    • 2.3.4 SCSI - DMA Transfers
      • Figure2.6 DMA Target Mode Transfers
  • 2.4 DMA Function
    • Figure2.7 DMA External Memory Access
  • 2.5 Microcontroller Operation
    • 2.5.1 ONCE Mode
  • 2.6 Two-Wire Serial Interface Operation
    • Figure2.8 Serial Read Operation
    • Figure2.9 Serial Write Operation
    • 2.6.1 Two-Wire Serial Interface Transfer Rate
    • 2.6.2 Power-On Serial ROM Download
      • Figure2.10 Serial ROM Download
      • Table 2.1 Initial ROM Download Contents
    • 2.6.3 Address and Length Download Configuration
    • 2.6.4 Firmware Download and Checksum
    • 2.6.5 Manually Accessing External Two-Wire Serial Devices
      • Figure2.11 Two-Wire Serial Slave Data Transmit and Receive
      • Figure2.12 Two-Wire Serial Master Data Transmit and Receive
  • 2.7 Power-On Configuration Options
    • Table 2.2 Power-On Configuration Pins and Options
    • 2.7.1 Automatic Branch Generation
      • Table 2.3 External Pull-up Values for Automatic Branch Generation
    • 2.7.2 External Serial ROM Configuration
    • 2.7.3 Serial ROM Chip Address
      • Table 2.4 Serial ROM Chip Addresses
    • 2.7.4 Download Port Select
  • 2.8 Resets
  • 2.9 SFF-8067 Mode
    • Figure2.13 LSI53C040 SFF-8067 Interface Control State Diagram
  • 2.10 Interrupts
    • 2.10.1 Microcontroller Interrupts
      • Table 2.5 Register Bits for Interrupt Handling
    • 2.10.2 DMA and SCSI Interrupts
    • 2.10.3 SFF-8067 Interrupts
    • 2.10.4 Two-Wire Serial Interrupts
    • 2.10.5 Masking and Enabling Interrupts
    • 2.10.6 Polling and Hardware Interrupts
    • 2.10.7 Interrupt Service Routine
      • Table 2.6 Interrupt Handling
  • 2.11 JTAG Boundary Scan Testing
• Chapter3 Signal Descriptions
  • Figure3.1 LSI53C040, 160-Pin QFP Option
  • Table 3.1 LSI53C040 160-Pin QFP Pin List (Alphabetically by Signal Name)
  • Table 3.2 LSI53C040 160-Pin QFP Pin List (Numerically by Pin Number)
  • Figure3.2 LSI53C040 169-Ball BGA Top View
  • Table3.3 169-Ball BGA List (Alphabetically by Ball Grid Location)
  • Table3.4 169-Ball BGA List (Alphabetically by Signal Name)
  • Figure3.3 LSI53C040 Functional Pin Description
  • 3.1 Safety Mode Signals
    • 3.1.1 Miscellaneous Signals
      • Table 3.5 Miscellaneous Signals
    • 3.1.2 SCSI Signals
      • Table 3.6 SCSI Signals 
    • 3.1.3 JTAG Signals
      • Table 3.7 JTAG Signals
    • 3.1.4 Power and Ground Signals
      • Table 3.8 Power and Grounds Signals
  • 3.2 SFF-8067 Mode
    • Table 3.9 Pin Assignments for SFF-8067 Mode
• Chapter4 SCSI and DMA Registers
  • Figure4.1 Register Set Overview
  • Table 4.1 SCSI and DMA Registers
  • Table 4.2 SCSI Phase Bit Values
• Chapter5 SFF-8067 Registers
  • Figure5.1 Register Set Overview
  • Table 5.1 SFF-8067 Interface Registers
• Chapter6 Two-Wire Serial Registers
  • Figure6.1 Register Set Overview
  • Table 6.1 Two-Wire Serial Registers
• Chapter7 Miscellaneous Registers
  • Figure7.1 Register Set Overview
  • Table 7.1 Miscellaneous Registers
  • Table 7.2 LSI53C040 Miscellaneous Registers
  • Table 7.3 Possible Watchdog Timer Values (40 MHz Internal Clock)
• Chapter8 System Registers
  • Figure8.1 Register Set Overview
  • Table 8.1 System Registers
  • Table 8.2 Automatic Branch Destination Address
  • Table 8.3 Fast LED Blink Rates (40 MHz Internal Clock)
  • Table 8.4 Slow LED Blink Rates (20 MHz Internal Clock)
  • Table 8.5 LED Behavior
  • Table8.6 LED Bank 1 Behavior
  • Table 8.7 LED Bank 2 Behavior
• Chapter9 Electrical Characteristics
  • 9.1 Operating Requirements
    • Table 9.1 Absolute Maximum Stress Ratings
    • Table 9.2 Operating Conditions
  • 9.2 3.3 Volt DC Specifications
    • Table 9.3 LVD Driver SCSI Signals�SD[7:0]+ SD[7:0]-, SDP0+, SDP0-, SREQ+, SREQ-, SACK/+, SACK/-, ...
    • Figure9.1 LVD Driver
    • Table 9.4 LVD Receiver SCSI Signals�SD[7:0]+, SD[7:0]-, SDP0+, SDP0-, SREQ/+, SREQ/-, SACK/+, SAC...
    • Figure9.2 LVD Receiver
    • Table 9.5 SE SCSI and SFF-8067 Signals�SD[7:0]+, SD[7:0]-, SHID[2:0]+, SHID[2:0]-, SDP0+, SDP0-, ...
    • Table 9.6 SCSI Signals�DIFFSENS
    • Table 9.7 Bidirectional 80C32 Signals�AD[7:0], A[15:8], ALE, PSEN/, RD/, WR/
    • Table 9.8 Input Signals�CLK, TCK, TMS, TDI, TRST/, TESTIN
    • Table 9.9 Bidirectional Signals�RESET/, TESTOUT, CL0, SDA0, SCL1, SDA1
    • Table 9.10 Bidirectional Signals�MPIO0[7:0], MPIO1[7:0], MPIO2[7:0], MPIO3[3:0]
    • Table 9.11 Bidirectional Signals�MPLED0[7:0], MPLED1[7:0], MPLED2[7:0]
  • 9.3 TolerANT Technology Electrical Characteristics
    • Table 9.12 TolerANT Technology Electrical Characteristics for SE SCSI Signals
    • Figure9.3 Rise and Fall Time Test Condition
    • Figure9.4 SCSI Input Filtering
    • Figure9.5 Hysteresis of SCSI Receivers
    • Figure9.6 Input Current as a Function of Input Voltage
    • Figure9.7 Output Current as a Function of Output Voltage
  • 9.4 AC Characteristics
    • 9.4.1 Clock Timing
      • Figure9.8 LSI53C040 Clock Waveforms
      • Table 9.13 LSI53C040 Clock Timings
    • 9.4.2 Reset Signal
      • Figure9.9 Reset Waveforms
      • Table 9.14 Reset Timings
  • 9.5 Microcontroller Interface Timings
    • 9.5.1 External Memory Interface
      • Figure9.10 External Memory Interface Waveforms
      • Table 9.15 External Memory Interface Timings
    • 9.5.2 External Data Read Cycle
      • Figure9.11 External Data Read Waveforms
      • Table 9.16 External Data Read Timings
    • 9.5.3 External Data Write Cycle
      • Figure9.12 External Data Write Waveforms
      • Table 9.17 External Data Write Timings
  • 9.6 Multipurpose Register Access
    • Table 9.18 Multipurpose I/O and LED Timings
  • 9.7 Two-Wire Serial Timings
    • Figure9.13 Two-Wire Serial Bus Timings
    • Table 9.19 Two-Wire Serial Interface Timings, Normal Mode (100 KHz Clock)
    • Table 9.20 Two-Wire Interface Timings, Fast Mode (400 KHz Clock)
  • 9.8 SFF-8067 Interface Timings
    • Figure9.14 SFF-8067 Discovery Phase Waveforms
    • Figure9.15 SFF-8067 Write Phase Waveforms
    • Figure9.16 SFF-8067 Read Waveforms
    • Table 9.21 SFF-8067 Interface Timings
  • 9.9 SCSI Timings
    • 9.9.1 Initiator Asynchronous Send
      • Figure9.17 Initiator Asynchronous Send Waveforms
      • Table 9.22 Initiator Asynchronous Send Timings
    • 9.9.2 Initiator Asynchronous Receive
      • Figure9.18 Initiator Asynchronous Receive Waveforms
      • Table 9.23 Initiator Asynchronous Receive Timings
    • 9.9.3 Target Asynchronous Send
      • Figure9.19 Target Asynchronous Send Waveforms
      • Table 9.24 Target Asynchronous Send Timings
    • 9.9.4 Target Asynchronous Receive
      • Figure9.20 Target Asynchronous Receive Waveforms
      • Table 9.25 Target Asynchronous Receive Timings
  • 9.10 Mechanical Drawings
    • Figure9.21 160-Lead PQFP (P3) Mechanical Drawing (Sheet 1 of 2)
    • Figure9.22 169-Pin PBGA (GV) Mechanical Drawing
• Appendix A Register Summary
  • TableA.1 Register Summary by Description 
  • TableA.2 Register Summary by Address
• Index
  • Numerics
    • 160-pin QFP 3-2
    • 169-ball BGA 3-5
    • 8067 interface data nibble bits 5-6, 5-7
    • 8067 port 0 interrupt or MPIO3_0 interrupt bit 7-8, 7-14, 7-15
    • 8067 port 1 interrupt or MPIO3_1 interrupt bit 7-8, 7-14, 7-15
    • 8067 read data bits 5-3
    • 8067 write data bits 5-3
  • A
    • A[6:0] bits 6-3
    • AACK bit 4-4
    • AAS bit 6-8
    • AATN bit 4-5
    • ABSY bit 4-5
    • AC characteristics 9-7
      • clock timing 9-11
      • microcontroller interface timings 9-13
      • reset input 9-12
      • SCSI timings 9-20
      • two-wire serial timings 9-17
    • access request 2-25
    • ACD assert C_D/ bit 2-9
    • ACD bit 4-8
    • ACK bit 4-11, 6-6, 6-7
    • ACK/ bit 5-6, 5-7
    • ACK/ handshake 2-8
    • acknowledge bit 4-11, 6-6, 6-7
    • active SCL frequency bit 6-3
    • ADB bit 4-5
    • address space mapping options 2-4
    • addressed as slave bit 6-8
    • AIO assert I_O/ bit 2-9
    • AIO bit 4-8
    • AIP bit 4-4
    • AMSG assert MSG/ bit 2-9
    • AMSG bit 4-8
    • ARB bit 4-7
    • arbitrate bit 4-7
    • arbitration
      • SFF-8067 2-24
      • two-wire serial 6-8
    • arbitration in progress bit 4-4
    • arbitration/selection LVD bit 4-6
    • AREQ bit 4-8
    • ARST bit 4-4
    • AS_LVD bit 4-6
    • ASEL bit 4-5
    • ASF bit 6-3
    • assert ACK/ bit 2-9, 4-4
    • assert ATN/ bit 4-5
    • assert BSY/ bit 4-5
    • assert C_D/ bit 2-9, 4-8
    • assert data bus bit 4-5
    • assert I_O/ bit 4-8
    • assert I_O/ bit-assert MSG/ bit 2-9
    • assert MSG/ bit 4-8
    • assert REQ/ bit 2-9, 4-8
    • assert SEL/ bit 4-5
    • assert SRST bit 4-4
    • ATN bit 4-11
    • attention bit 4-11
    • automatic branch generation 2-21
  • B
    • BB_N bit 6-8
    • BER bit 6-8
    • BERR bit 4-11
    • block diagram 2-1
    • branch generation disabled 2-22
    • BSR register 4-10
    • BSY bit 4-9, 5-4
    • bus and status register 4-10
    • bus busy bit 6-8
    • bus error detection bit 6-8
    • busy bit 4-9
    • busy error bit 4-11
  • C
    • C_D bit 4-9
    • checksum error bit 6-9
    • chip revision bits 7-6
    • CKSUM bit 6-9
    • clock register 6-3
    • command/data bit 4-9
    • configuration ROM download 2-16
    • control register reads 6-6
    • control register writes 6-5
    • CSBS register 4-9
    • CSDHI register 4-13
    • CTL0 bit 6-10
    • CTL1 bit 6-9
    • current SCSI bus status register 4-9
    • current SCSI data high register 4-13
    • current SCSI data register 4-3
  • D
    • D[3:0] bits 5-6, 5-7
    • D[7:0] 6-4
    • data bits 6-4
    • data bus parity bit 4-10
    • data memory 2-3
    • data register 6-4
    • data transfer length bits 4-15
    • DB[7:0] bits 4-3, 5-3
    • DBP bit 4-10
    • DC specifications 9-3
    • DIFFSENS 2-8, 2-24
    • DLADR[2:0] bits 8-6
    • DLCFG bit 8-4
    • DLSEL bit 8-6
    • DM bit 4-7
    • DMA block 2-4
    • DMA core
      • initiating a DMA transfer 2-11
      • overview 2-4
      • send operation 2-13
    • DMA function 2-13 to 2-14
    • DMA handshaking 2-11
    • DMA interrupt bit 4-17, 7-7, 7-14, 7-15
    • DMA interrupt register 4-17
    • DMA mode bit 2-11, 4-7
    • DMA operation 2-27
    • DMA send register 4-12
    • DMA source/destination high register 4-16
    • DMA source/destination low register 4-16
    • DMA status 2-11
    • DMA status register 4-14
    • DMA target transfers 2-6
    • DMA transfer length 2-11
    • DMA transfer length register 4-15
    • DMA transfers 2-11
    • DMA_INT bit 7-7
    • DMAI register 4-17
    • download configuration select bit 8-6
    • download ROM address bits 8-6
    • download serial ROM bit 8-4
    • DS register 4-14
    • DSDH register 4-16
    • DSDL register 4-16
    • DSK_RD/ value bit 5-6, 5-7
    • DSK_WR/ value bit 5-5, 5-6
    • DTL register 4-15
    • DWR bit 5-5
    • DWR/ bit 5-6
  • E
    • EIEN bit 8-8
    • enable parity checking bit 4-6
    • enable parity interrupt bit 4-6
    • enable reset output bit 8-7
    • enable serial output bit 6-5, 6-6
    • ENCL_ACK/ value bit 5-6, 5-7
    • end of DMA transfer bit 4-10
    • ENI bit 6-5, 6-7
    • EOD bit 4-10
    • EPC bit 4-6
    • EPI bit 4-6
    • ERO bit 8-7
    • ES[1:2] bits 6-5, 6-6
    • ES0 bit 6-5, 6-6
    • EXS0_INT bit 7-8
    • EXS1_INT bit 7-8
    • external interrupt enable bit 6-5, 6-7, 8-8
  • F
    • fast blink rate bits 8-7
    • FBR[1:0] bits 8-7
    • features summary 1-4
    • FIBD[1:0] bits 8-4
    • firmware requirements 2-11
    • first instruction branch destination bits 8-4
    • functional overview 2-1
    • functional pin description 3-8
  • H
    • halting a DMA operation 2-11
    • high impedance mode bit 7-6
  • I
    • I/O direction bit 4-14
    • I_O bit 4-9
    • ICF bit 6-3
    • ICR 4-4
    • idle mode 2-11, 2-13
    • IDR register 7-15
    • IEN bit 4-15
    • IMR register 7-13
    • initial instruction fetch 2-21
    • initiator command register 4-4
    • input/output bit 4-9
    • instruction jump 2-21
    • INT bit 4-17
    • interface
      • port 0 2-24
      • port 1 2-24
      • SFF-8067 2-4, 2-23, 2-24
      • SFF-8067 control 2-25
      • two-wire serial 2-3, 2-22
    • inter-integrated circuit bus 2-15
    • intermediate clock frequency bit 6-3
    • internal chip reset 2-23
    • internal memory 2-3
    • internal scratch RAM 2-3
    • interrupt
      • read 2-25
      • write 2-25
    • interrupt destination register 2-27, 2-29, 7-15
    • interrupt enable bit 4-15
    • interrupt mask register 2-27, 2-29, 7-13
    • interrupt request active bit 4-11
    • interrupt status register 2-28, 7-7
    • interrupts 2-27
      • end of process 2-29
      • interrupt destination register 2-29
      • interrupt mask register 2-29
      • interrupt service routine 2-33
      • interrupt status register 2-28
      • loss of BSY/ 2-31
      • masking and enabling 2-32
      • parity error 2-30
      • phase mismatch 2-30
    • interrupts (Cont.)
      • polling and hardware interrupts 2-32
      • register bits used 2-28
      • SCSI 2-27, 2-29
      • SCSI bus reset 2-30
      • SFF-8067 2-31
      • two-wire serial 2-31
    • IOD bit 4-14
    • IRA bit 4-11
    • ISR register 7-7
    • ITF0 control bit 6-10
    • ITF0 SCL input bit 6-10
    • ITF0 SCL output bit 6-10
    • ITF0 SDA input bit 6-10
    • ITF0 SDA output bit 6-10
    • ITF1 control bit 6-9
    • ITF1 SCL input bit 6-9
    • ITF1 SCL output bit 6-9
    • ITF1 SDA input bit 6-9
    • ITF1 SDA output bit 6-9
  • J
    • JTAG signal pins 3-16
    • JTAG support 2-34
    • jump instruction 2-21
  • L
    • LA bit 4-4
    • LAB bit 6-8
    • last byte sent bit 4-8
    • last received bit/address 0 bit 6-8
    • LBR register 8-6
    • LBS bit 4-8
    • LED blink rate register 8-6
    • LESI0�LESI1 registers 5-5
    • live ESI registers 5-5
    • lost arbitration bit 4-4, 6-8
    • LRB/AD0 bit 6-8
    • LSI53C040
      • advantages 1-1
      • features summary 1-4
      • introduction 1-1
    • LVD bit 8-8
    • LVD mode 2-8
    • LVD_PWRDWN bit 7-6
    • LVDlink technology 2-8
  • M
    • manual data output registers 5-6
    • maximum ratings 9-2
    • MB bit 4-6
    • MCR register 7-6
    • MDATA0�MDATA1 registers 5-6
    • message bit 4-9
    • microcontroller core
      • automatic branch generation 2-21
      • interrupts 2-27
      • overview 2-3
      • timings 9-13
    • miscellaneous control register 7-6
    • miscellaneous register 6-9
    • miscellaneous signal pins 3-9
    • MLI0H register 8-23
    • MLI0L register 8-22
    • MLI1H register 8-27
    • MLI1L register 8-27
    • MLI2H register 8-32
    • MLI2L register 8-31
    • MLL0H register 8-25
    • MLL0L register 8-24
    • MLL1H register 8-29
    • MLL1L register 8-29
    • MLL2H register 8-34
    • MLL2L register 8-33
    • MLLM0H register 8-24
    • MLLM0L register 8-23
    • MLLM1H register 8-28
    • MLLM1L register 8-28
    • MLLM2H register 8-33
    • MLLM2L register 8-32
    • MLO0H register 8-22
    • MLO0L register 8-21
    • MLO1H register 8-26
    • MLO1L register 8-25
    • MLO2H register 8-31
    • MLO2L register 8-30
    • mode register 4-6
    • monitor busy bit 4-6
    • MPE0 register 8-9
    • MPE1 register 8-12
    • MPE2 register 8-15
    • MPE3 register 8-18
    • MPI0 register 8-9
    • MPI1 register 8-12
    • MPI2 register 8-15
    • MPI3 register 8-19
    • MPIO3_[1:0] 2-27, 2-28, 2-34
    • MPIO3_0 interrupt or 8067 port 0 interrupt bit 7-8, 7-14, 7-15
    • MPIO3_1 interrupt or 8067 port 1 interrupt bit 7-8, 7-14, 7-15
    • MPL0 register 8-10
    • MPL1 register 8-13
    • MPL2 register 8-16
    • MPL3 register 8-20
    • MPLM0 register 8-10
    • MPLM1 register 8-13
    • MPLM2 register 8-16
    • MPLM3 register 8-19
    • MPO0 register 8-8
    • MPO1 register 8-11
    • MPO2 register 8-14
    • MPO3 register 8-17
    • MPPE0 register 8-11
    • MPPE1 register 8-14
    • MPPE2 register 8-17
    • MPPE3 register 8-20
    • MSG/ bit 4-9
    • multipurpose I/O bank 0
      • enable register 8-9
      • input register 8-9
      • latch mask register 8-10
      • latch register 8-10
      • output register 8-8
      • pull-down enable register 8-11
    • multipurpose I/O bank 1
      • enable register 8-12
      • input register 8-12
      • latch mask register 8-13
      • latch register 8-13
    • multipurpose I/O bank 1 (Cont.)
      • output register 8-11
      • pull-down enable register 8-14
    • multipurpose I/O bank 2
      • enable register 8-15
      • input register 8-15
      • latch mask register 8-16
      • latch register 8-16
      • output register 8-14
      • pull-down enable register 8-17
    • multipurpose I/O bank 3
      • enable register 8-18
      • input register 8-19
      • latch mask register 8-19
      • latch register 8-20
      • output register 8-17
      • pull-down enable register 8-20
    • multipurpose LED bank 0H
      • input register 8-23
      • latch mask register 8-24
      • latch register 8-25
      • output register 8-22
    • multipurpose LED bank 0L
      • input register 8-22
      • latch mask register 8-23
      • latch register 8-24
      • output register 8-21
    • multipurpose LED bank 1H
      • input register 8-27
      • latch mask register 8-28
      • latch register 8-29
      • output register 8-26
    • multipurpose LED bank 1L
      • input register 8-27
      • latch mask register 8-28
      • latch register 8-29
      • output register 8-25
    • multipurpose LED bank 2H
      • input register 8-32
      • latch mask register 8-33
      • latch register 8-34
      • output register 8-31
    • multipurpose LED bank 2L
      • input register 8-31
      • latch mask register 8-32
      • latch register 8-33
      • output register 8-30
  • O
    • ODR 4-3
    • operating conditions 9-2
    • output data register 4-3
  • P
    • PA[7:0] bits 5-5
    • parallel ESI/ value bit 5-5, 5-6
    • parity error bit 4-11
    • PCST0�PCST1 registers 5-3
    • pending interrupt bit 6-5, 6-6
    • pending interrupt not bit
      • PIN bit 6-7
    • PERR bit 4-11
    • PESI/ bit 5-5, 5-6
    • PHAD0�PHAD1 register 5-5
    • phase match bit 4-11
    • physical address register 5-5
    • PIN bit 6-5, 6-6
    • PMATCH bit 4-11
    • PME bit 5-3
    • POC0 register 8-4
    • POC1 register 8-5
    • port access 2-25
    • port busy flag bit 5-4
    • port control/status register 5-3
    • port manual enable bit 5-3
    • power pins 3-17
    • power-on configuration one register 8-5
    • power-on configuration options 2-21
      • automatic branch generation 2-21
    • power-on configuration zero register 8-4
    • power-on options
      • download port select 2-23
      • serial ROM 2-22
      • serial ROM chip address 2-22
    • power-on reset, 2-23
    • program memory 2-3
    • programmed I/O transfers 2-8
    • protocol
      • SCSI 2-3
  • R
    • RD/ bit 5-6, 5-7
    • RDATA0�RDATA1 register 5-3
    • read data register 5-3
    • read interrupt bit 5-4
    • read register full bit 5-4
    • receive operations 2-13
    • register bits
      • 8067 interface data nibble 5-6, 5-7
      • 8067 port 0 interrupt 7-8, 7-14, 7-15
      • 8067 port 1 interrupt 7-8, 7-14, 7-15
      • 8067 read data 5-3
      • 8067 write data 5-3
      • A[6:0] 6-3
      • AACK 4-4
      • AAS 6-8
      • AATN 4-5
      • ABSY 4-5
      • ACD 4-8
      • ACK 4-11, 6-6, 6-7
      • ACK/ 5-6, 5-7
      • acknowledge 4-11, 6-6, 6-7
      • active SCL frequency 6-3
      • ADB 4-5
      • address 0 bit 6-8
      • addressed as slave 6-8
      • AIO 4-8
      • AIP 4-4
      • AMSG 4-8
      • ARB 4-7
      • arbitrate 4-7
      • arbitration in progress 4-4
      • arbitration/selection LVD 4-6
      • AREQ 4-8
      • ARST 4-4
      • AS_LVD 4-6
      • ASEL 4-5
      • ASF 6-3
      • assert ACK/ 4-4
    • register bits (Cont.)
      • assert ATN/ 4-5
      • assert BSY/ 4-5
      • assert C_D/ 4-8
      • assert data bus 4-5
      • assert I_O/ 4-8
      • assert MSG/ 4-8
      • assert REQ/ 4-8
      • assert SEL/ 4-5
      • assert SRST 4-4
      • ATN 4-11
      • attention 4-11
      • BB_N 6-8
      • BER 6-8
      • BERR 4-11
      • BSY 4-9, 5-4
      • bus busy 6-8
      • bus error detection 6-8
      • busy 4-9
      • busy error 4-11
      • C_D 4-9
      • checksum error 6-9
      • chip revision 7-6
      • CKSUM 6-9
      • command/data 4-9
      • CTL0 6-10
      • CTL1 6-9
      • current SCSI data bus 4-3
      • current SCSI data high 4-13
      • D[3:0] 5-6, 5-7
      • D[7:0] 6-4
      • data bits 6-4
      • data bus parity 4-10
      • data transfer length 4-15
      • DB[7:0] 4-3, 5-3
      • DBP 4-10
      • DLADR[2:0] 8-6
      • DLCFG 8-4
      • DLSEL 8-6
      • DM 4-7
      • DMA interrupt 4-17, 7-7, 7-14, 7-15
      • DMA mode 4-7
      • DMA source/destination high 4-16
      • DMA source/destination Low 4-16
      • DMA_INT 7-7
      • download configuration select 8-6
      • download ROM address 8-6
      • download serial ROM 8-4
      • DSDH[7:0] 4-16
      • DSDL[7:0] 4-16
      • DSK_RD/ value 5-6, 5-7
      • DSK_WR/ value 5-5, 5-6
      • DTL[7:0] 4-15
      • DWR/ 5-5, 5-6
      • EIEN 8-8
      • enable parity checking 4-6
      • enable parity interrupt 4-6
      • enable reset output 8-7
      • enable serial output 6-5, 6-6
      • ENCL_ACK/ value 5-6, 5-7
      • end of DMA transfer 4-10
      • ENI 6-5, 6-7
      • EOD 4-10
      • EPC 4-6
      • EPI 4-6
      • ERO 8-7
      • ES[1:2] 6-5, 6-6
      • ES0 6-5, 6-6
      • EXS0_INT 7-8
      • EXS1_INT 7-8
      • external interrupt enable 6-5, 6-7, 8-8
      • fast blink rate 8-7
      • FBR[1:0] 8-7
      • FIBD[1:0] 8-4
      • first instruction branch destination 8-4
      • high impedance mode 7-6
      • I/O direction 4-14
      • I_O 4-9
      • ICF 6-3
      • IDR[7:0] 7-15
      • IEN 4-15
      • IMR[7:0] 7-13
      • input/output 4-9
      • INT 4-17
      • intermediate clock frequency 6-3
      • interrupt enable 4-15
      • interrupt request active 4-11
      • IOD 4-14
      • IRA 4-11
      • ITF0 control 6-10
      • ITF0 SCL input 6-10
      • ITF0 SCL output 6-10
      • ITF0 SDA input 6-10
      • ITF0 SDA output 6-10
      • ITF1 control 6-9
      • ITF1 SCL input 6-9
      • ITF1 SCL output 6-9
      • ITF1 SDA input 6-9
      • ITF1 SDA output 6-9
      • LA 4-4
      • LAB 6-8
      • last byte sent 4-8
      • last received bit 6-8
      • LBS 4-8
      • lost arbitration 4-4, 6-8
      • LRB/AD0 6-8
      • LVD 8-8
      • LVD_PWRDWN 7-6
      • MB 4-6
      • message 4-9
      • MLI1_[3:0] 8-27
      • MLI1_[7:4] 8-27
      • MLI2_[3:0] 8-31
      • MLI2_[7:4] 8-32
      • MLL0_[3:0] 8-22, 8-24
      • MLL0_[7:4] bits 8-23, 8-25
      • MLL1_[3:0] bits 8-29
      • MLL1_[7:4] bits 8-29
      • MLL2_[3:0] 8-33
      • MLL2_[7:4] 8-34
      • MLLM0_[3:0] 8-23
      • MLLM0_[7:4] 8-24
      • MLLM1_[3:0] 8-28
      • MLLM1_[7:4] 8-28
      • MLLM2_[3:0] bits 8-32
      • MLLM2_[7:4] 8-33
      • MLO0_[3A:0A], [3B:0B] 8-21
      • MLO0_[7A:4A], [7B:4B] 8-22
      • MLO1_[3A:0A], [3B:0B] 8-25
      • MLO1_[7A:4A], [7B:4B] 8-26
      • MLO2_[3A:0A], [3B:0B] 8-30
      • MLO2_[7A:4A], [7B:4B] 8-31
    • register bits (Cont.)
      • monitor busy 4-6
      • MPE0_[7:0] 8-9
      • MPE1_[7:0] 8-12
      • MPE2_[7:0] 8-15
      • MPE3_[3:0] 8-18
      • MPI0_[7:0] 8-9
      • MPI1_[7:0] 8-12
      • MPI2_[7:0] bits 8-15
      • MPI3_[3:0] 8-19
      • MPIO3_0 interrupt 7-8, 7-14, 7-15
      • MPIO3_1 interrupt 7-8, 7-14, 7-15
      • MPL0_[7:0] 8-10
      • MPL1_[7:0] 8-13
      • MPL2_[7:0] 8-16
      • MPL3_[3:0] 8-20
      • MPLM0_[7:0] 8-10
      • MPLM1_[7:0] 8-13
      • MPLM2_[7:0] 8-16
      • MPLM3_[3:0] 8-19
      • MPO0_[7:0] 8-8
      • MPO1_[7:0] 8-11
      • MPO2_[7:0] 8-14
      • MPO3_[3:0] 8-17
      • MPPE0_[7:0] 8-11
      • MPPE1_[7:0] 8-14
      • MPPE2_[7:0] 8-17
      • MPPE3_[3:0] 8-20
      • MSG/ 4-9
      • multipurpose I/O bank 0
        • enable 8-9
        • input 8-9
        • latch 8-10
        • latch mask 8-10
        • output 8-8
        • pull-down enable 8-11
      • multipurpose I/O bank 1
        • enable 8-12
        • input 8-12
        • latch 8-13
        • latch mask 8-13
        • output 8-11
        • pull-down enable 8-14
      • multipurpose I/O bank 2
        • enable 8-15
        • input 8-15
        • latch 8-16
        • latch mask 8-16
        • output 8-14
        • pull-down enable 8-17
      • multipurpose I/O bank 3
        • enable 8-18
        • input 8-19
        • latch 8-20
        • latch mask 8-19
        • output 8-17
        • pull-down enable 8-20
      • multipurpose LED bank 0H
        • input 8-23
        • latch 8-25
        • latch mask 8-24
        • output 8-22
      • multipurpose LED bank 0L
        • input 8-22
        • latch 8-24
        • latch mask 8-23
        • output 8-21
      • multipurpose LED bank 1H
        • input 8-27
        • latch 8-29
        • latch mask 8-28
        • output 8-26
      • multipurpose LED bank 1L
        • input 8-27
        • latch bits 8-29
        • latch mask 8-28
        • output 8-25
      • multipurpose LED bank 2H
        • input 8-32
        • latch 8-34
        • latch mask 8-33
        • output 8-31
      • multipurpose LED bank 2L
        • input 8-31
        • latch 8-33
        • latch mask 8-32
        • output 8-30
      • own address 6-3
      • PA[7:0] 5-5
      • parallel ESI/ value 5-5, 5-6
      • parity error 4-11
      • pending interrupt 6-5, 6-6
      • pending interrupt not 6-7
      • PERR 4-11
      • PESI/ 5-5, 5-6
      • phase match 4-11
      • physical address 5-5
      • PIN 6-5, 6-6, 6-7
      • PMATCH 4-11
      • PME 5-3
      • POC0_[7:6], [4:2] 8-4
      • POC1_[6:4] 8-5
      • port busy flag 5-4
      • port manual enable 5-3
      • power-on configuration 1_[6:4] 8-5
      • power-on configuration[7:6], [4:2] 8-4
      • RD/ 5-6, 5-7
      • read interrupt 5-4
      • read register full 5-4
      • register selection 6-5, 6-6
      • repeated start 6-7
      • REQ 4-9
      • request 4-9
      • REV[3:0] 7-6
      • RINT 5-4
      • RPSS 6-7
      • RRF 5-4
      • RST 4-9
      • SBR[1:0] 8-7
      • SCLI0 6-10
      • SCLI1 6-9
      • SCLO0 6-10
      • SCLO1 6-9
      • SCSI high ID 4-13
      • SCSI interrupt 7-7, 7-13, 7-15
      • SCSI isolation 7-6
      • SCSI LVD mode 8-8
      • SCSI output data 4-3
      • SCSI reset 4-9
      • SCSI_INT 7-7
      • SDAI0 6-10
      • SDAI1 6-9
    • register bits (Cont.)
      • SDAO0 6-10
      • SDAO1 6-9
      • SE[7:0] 4-10
      • SEL 4-10
      • select 4-10
      • selection ID bits 4-10
      • serial port enable 8-8
      • SHID[2:0] 4-13
      • SISO 7-6
      • slave mode stop 6-8
      • slow blink rate 8-7
      • SPEN 8-8
      • STA 6-5, 6-7
      • start 6-5, 6-7
      • STO 6-6, 6-7
      • stop 6-6, 6-7
      • STS 6-8
      • T1CLR 7-9
      • T1EXP 7-8
      • T1FC[7:0] 7-10
      • T1IEN 7-9
      • T1PS 7-9
      • T1RUN 7-8
      • T1SC[6:0] 7-10
      • T1TH[7:0] 7-9
      • T2CLR 7-11
      • T2EXP 7-11
      • T2FC[7:0] 7-13
      • T2IEN 7-11
      • T2PS 7-11
      • T2RUN 7-11
      • T2SC[6:0] 7-12
      • T2TH[7:0] 7-12
      • target mode 4-6
      • TC 4-14
      • TE 7-6
      • TGTM 4-6
      • Timer 1
        • final chain 7-10
      • timer 1
        • clear 7-9
        • expired 7-8
        • interrupt enable 7-9
        • prescaler 7-9
        • run 7-8
        • secondary chain 7-10
        • threshold 7-9
      • timer 1 interrupt 7-7, 7-14, 7-15
      • timer 2
        • clear 7-11
        • expired 7-11
        • final chain 7-13
        • interrupt enable 7-11
        • prescaler 7-11
        • run 7-11
        • secondary chain 7-12
        • threshold 7-12
      • timer 2 interrupt 7-7, 7-14, 7-15
      • TIP 4-15
      • TMR1_INT 7-7
      • TMR2_INT 7-7
      • TolerANT enable 7-6
      • transfer complete 4-14
      • transfer in progress 4-15
      • TW0_INT 7-7
      • TW1_INT 7-7
      • two-wire interface 0 interrupt 7-7, 7-13, 7-15
      • two-wire interface 1 interrupt 7-7, 7-13, 7-15
      • watchdog final chain 7-5
      • watchdog reboot 7-3
      • watchdog secondary chain 7-5
      • watchdog timer threshold 7-3
      • WDFC[3:0] 7-5
      • WDRBT 7-3
      • WDSC[6:0] 7-5
      • WINT 5-4
      • WRF 5-4
      • write interrupt 5-4
      • write register full 5-4
      • WTHR[3:0] 7-3
      • ZMODE 7-6
    • register selection bits 6-5, 6-6
    • registers
      • bus and status 4-10
      • clock 6-3
      • control reads 6-6
      • control register writes 6-5
      • current SCSI bus status 4-9
      • current SCSI data 4-3
      • current SCSI data high 4-13
      • data 6-4
      • DMA interrupt 4-17
      • DMA send 4-12
      • DMA source/destination high 4-16
      • DMA source/destination low 4-16
      • DMA status 4-14
      • DMA transfer length 4-15
      • IDR 7-15
      • IMR 7-13
      • initiator command 4-4
      • interrupt destination 7-15
      • interrupt mask 7-13
      • interrupt status 7-7
      • ISR 7-7
      • LBR 8-6
      • LED blink rate 8-6
      • LESI0�LESI1 5-5
      • live ESI 5-5
      • manual data output 5-6
      • MCR 7-6
      • MDATA0�MDATA1 5-6
      • miscellaneous 6-9
      • MLI0H 8-23
      • MLI0L 8-22
      • MLI1H 8-27
      • MLI1L 8-27
      • MLI2H 8-32
      • MLI2L 8-31
      • MLL0H 8-25
      • MLL0L 8-24
      • MLL1H 8-29
      • MLL1L 8-29
      • MLL2H 8-34
      • MLL2L 8-33
      • MLLM0H 8-24
      • MLLM0L 8-23
      • MLLM1H 8-28
      • MLLM1L 8-28
      • MLLM2H 8-33
      • MLLM2L 8-32
      • MLO0H 8-22
    • registers (Cont.)
      • MLO0L 8-21
      • MLO1H 8-26
      • MLO1L 8-25
      • MLO2H 8-31
      • MLO2L 8-30
      • mode register 4-6
      • MPE0 8-9
      • MPE1 8-12
      • MPE2 8-15
      • MPE3 8-18
      • MPI0 8-9
      • MPI1 8-12
      • MPI2 8-15
      • MPI3 8-19
      • MPL0 8-10
      • MPL1 8-13
      • MPL2 8-16
      • MPL3 8-20
      • MPLM0 8-10
      • MPLM1 8-13
      • MPLM2 8-16
      • MPLM3 8-19
      • MPO0 8-8
      • MPO1 8-11
      • MPO2 8-14
      • MPO3 8-17
      • MPPE0 8-11
      • MPPE1 8-14
      • MPPE2 8-17
      • MPPE3 8-20
      • multipurpose I/O bank 0
        • enable 8-9
        • input 8-9
        • latch 8-10
        • latch mask 8-10
        • output 8-8
        • pull-down enable 8-11
      • multipurpose I/O bank 1
        • enable 8-12
        • input 8-12
        • latch 8-13
        • latch mask 8-13
        • output 8-11
        • pull-down enable 8-14
      • multipurpose I/O bank 2
        • enable 8-15
        • input 8-15
        • latch 8-16
        • latch mask 8-16
        • output 8-14
        • pull-down enable 8-17
      • multipurpose I/O bank 3
        • enable 8-18
        • input 8-19
        • latch 8-20
        • latch mask 8-19
        • output 8-17
        • pull-down enable 8-20
      • multipurpose LED bank 0H
        • input 8-23
        • latch 8-25
        • latch mask 8-24
        • output 8-22
      • multipurpose LED bank 0L
        • input 8-22
        • latch 8-24
        • latch mask 8-23
        • output 8-21
      • multipurpose LED bank 1H
        • input 8-27
        • latch 8-29
        • latch mask 8-28
        • output 8-26
      • multipurpose LED bank 1L
        • input 8-27
        • latch 8-29
        • latch mask 8-28
        • output 8-25
      • multipurpose LED bank 2H
        • input 8-32
        • latch 8-34
        • latch mask 8-33
        • output 8-31
      • multipurpose LED bank 2L
        • input 8-31
        • latch 8-33
        • latch mask 8-32
        • output 8-30
      • output data register 4-3
      • own address 6-3
      • PCST0�PCST1 5-3
      • PHAD0�PHAD1 5-5
      • physical address 5-5
      • POC0 8-4
      • POC1 8-5
      • port control/status 5-3
      • power-on configuration one 8-5
      • power-on configuration zero 8-4
      • reset parity/interrupt 4-12
      • select enable 4-10
      • select enable register high 4-13
      • start DMA initiator receive 4-13
      • start DMA target receive 4-12
      • status register reads 6-7
      • summary
        • by address A-5
        • by description A-1
      • SYSCTRL 8-7
      • system control 8-7
      • T1C 7-8
      • T1FC 7-10
      • T1SC 7-10
      • T1TH 7-9
      • T2C 7-11
      • T2FC 7-13
      • T2SC 7-12
      • T2T 7-12
      • target command 4-8
      • timer 1 control 7-8
      • timer 1 final chain 7-10
      • timer 1 secondary chain 7-10
      • timer 1 threshold 7-9
      • timer 2 control 7-11
      • timer 2 final chain 7-13
      • timer 2 secondary chain 7-12
      • timer 2 threshold 7-12
      • UC control ITF0 6-10
      • UC control ITF1 6-9
      • watchdog final chain 7-5
      • watchdog secondary chain 7-5
      • watchdog timer control 7-3
    • registers (Cont.)
      • WDATA0�WDATA1 5-3
      • WDFC 7-5
      • WDSC 7-5
      • WDTC 7-3
      • write data 5-3
    • repeated start bit 6-7
    • REQ bit 4-9
    • REQ/ handshake 2-8
    • request bit 4-9
    • reset parity/interrupt register 4-12
    • reset pin 2-23
    • resets 2-23
    • REV[3:0] bits 7-6
    • RINT bit 5-4
    • ROM download 2-22
    • RPI register 4-12
    • RPSS bit 6-7
    • RRF bit 5-4
    • RST bit 4-9
  • S
    • SAF-TE typical implementation 1-2
    • SBR[1:0] bits 8-7
    • SCLI0 bit 6-10
    • SCLI1 bit 6-9
    • SCLO0 bit 6-10
    • SCLO1 bit 6-9
    • SCSI arbitration 2-6
    • SCSI core
      • description 2-5 to 2-12
      • halting a DMA operation 2-11
      • interrupts 2-29
      • overview 2-3
      • register bits used for interrupts 2-28
      • SCSI-DMA transfers 2-11
      • timings 9-20
    • SCSI current SCSI data bus bits 4-3
    • SCSI high ID bits 4-13
    • SCSI high IDs 2-5
    • SCSI interrupt bit 7-7, 7-15
    • SCSI interrupts 2-27
      • register bits used 2-28
    • SCSI isolation bit 7-6
    • SCSI LVD mode bit 8-8
    • SCSI output data bus bits 4-3
    • SCSI pins 3-13
    • SCSI protocol 2-3
    • SCSI reselection 2-6
    • SCSI reset bit 4-9
    • SCSI selection 2-6
    • SCSI_INT bit 7-7
    • SCSI-DMA transfers 2-11
    • SDAI0 bit 6-10
    • SDAI1 bit 6-9
    • SDAO0 bit 6-10
    • SDAO1 bit 6-9
    • SDIR register 4-13
    • SDTR register 4-12
    • SE[7:0] bits 4-10
    • SEL bit 4-10
    • select bit 4-10
    • select enable register 4-10
    • select enable register high 4-13
    • selection ID bits 4-10
    • SEN register 4-10
    • send operations 2-13
    • SENHI register 4-13
    • serial port enable bit 8-8
    • serial ROM download
      • chip address mapping 2-22
      • external ROM 2-22
      • selecting a two-wire serial interface 2-23
    • SFF-8067 interface 2-4, 2-23, 2-24
      • control 2-25
      • interrupts 2-31
      • pin assignments 3-18
      • typical implementation 1-3
    • SFF-8067 mode 2-24 to 2-26
    • SHID[2:0] bits 2-6, 4-13
    • single
      • ended SCSI signals 9-7
    • single-ended mode 2-8
    • SISO bit 7-6
    • slave mode stop bit 6-8
    • slow blink rate bits 8-7
    • soft reset 2-23
    • SPEN bit 8-8
    • SRAM, internal 2-4
    • STA bit 6-5, 6-7
    • start bit 6-5, 6-7
    • start DMA initiator receive register 4-13
    • start DMA target receive register 4-12
    • status register reads register 6-7
    • STO bit 6-6, 6-7
    • stop bit 6-6, 6-7
    • stress ratings 9-2
    • STS bit 6-8
    • SYSCTRL register 8-7
    • system control register 8-7
  • T
    • T1C register 7-8
    • T1CLR bit 7-9
    • T1EXP bit 7-8
    • T1FC register 7-10
    • T1IEN bit 7-9
    • T1PS bit 7-9
    • T1RUN bit 7-8
    • T1SC register 7-10
    • T1TH register 7-9
    • T2C register 7-11
    • T2CLR bit 7-11
    • T2EXP bit 7-11
    • T2FC register 7-13
    • T2IEN bit 7-11
    • T2PS bit 7-11
    • T2RUN bit 7-11
    • T2SC register 7-12
    • T2T register 7-12
    • T2TH[7:0] bits 7-12
    • target applications 2-6
    • target command register 4-8
    • target mode bit 4-6
    • TC bit 4-14
    • TE bit 7-6
    • TGTM bit 4-6
    • timer 1
      • clear bit 7-9
      • control register 7-8
    • timer 1 (Cont.)
      • expired bit 7-8
      • final chain register 7-10
      • interrupt bit 7-7, 7-14, 7-15
      • interrupt enable bit 7-9
      • prescaler bit 7-9
      • run bit 7-8
      • secondary chain bits 7-10
      • secondary chain register 7-10
      • threshold register 7-9
    • timer 2
      • clear bit 7-11
      • control register 7-11
      • expired bit 7-11
      • final chain register 7-13
      • interrupt bit 7-7, 7-14, 7-15
      • interrupt enable bit 7-11
      • prescaler bit 7-11
      • run bit 7-11
      • secondary chain register 7-12
      • threshold register 7-12
    • timings 9-7
      • clock timing 9-11
      • microcontroller interface 9-13
      • reset input 9-12
      • SCSI 9-20
      • two-wire serial interface 9-17
    • TIP bit 4-15
    • TISC[6:0] bits 7-10
    • TMR1_INT bit 7-7
    • TMR2_INT bit 7-7
    • TolerANT
      • technology
        • electrical characteristics 9-7
    • TolerANT enable bit 7-6
    • transfer complete bit 4-14
    • transfer in progress bit 4-15
    • transfer length 2-13
    • TW0_INT bit 7-7
    • TW1_INT bit 7-7
    • two-wire Interface 0 interrupt bit 7-7
    • two-wire interface 0 interrupt bit 7-13
    • two-wire interface 1 interrupt bit 7-7, 7-13, 7-15
    • two-wire interface own address register 6-3
    • two-wire serial interface 2-3, 2-22
      • accessing two-wire serial peripherals 2-18
      • configuration ROM download 2-16
      • external serial ROM 2-22
      • functions 2-15
      • interrupts 2-31
      • overview 2-3
      • power-on configuration options 2-21
      • selecting a two-wire port 2-23
      • timings 9-17
      • transfer rate 2-16
  • U
    • UC control ITF0 register 6-10
    • UC control ITF1 register 6-9
  • W
    • watchdog final chain register 7-5
    • watchdog reboot bit 7-3
    • watchdog secondary chain register 7-5
    • watchdog timer 2-24
    • watchdog timer control register 7-3
    • watchdog timer threshold bits 7-3
    • WDATA0�WDATA1 register 5-3
    • WDFC register 7-5
    • WDRBT bit 7-3
    • WDSC register 7-5
    • WDTC register 7-3
    • wide SCSI bus 2-5
    • WINT bit 5-4
    • WRF bit 5-4
    • write data register 5-3
    • write interrupt bit 5-4
    • write register full bit 5-4
    • WTHR[3:0] bits 7-3
  • Z
    • ZMODE bit 7-6
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