Document Outline

• LSI53C1020 PCI-X to Ultra320 SCSI Controller
  • Preface
  • Contents
  • Figures
  • Tables
  • Chapter1 Introduction
    • 1.1 General Description
      • Figure1.1 Typical LSI53C1020 Board Application
      • Figure1.2 Typical LSI53C1020 System Application
    • 1.2 Benefits of the Fusion-MPT Architecture
    • 1.3 Benefits of PCI-X
    • 1.4 Benefits of Ultra320 SCSI
    • 1.5 Benefits of SureLINK (Ultra320 SCSI Domain Validation)
    • 1.6 Benefits of LVDlink Technology
    • 1.7 Benefits of TolerANT� Technology
    • 1.8 Summary of LSI53C1020 Features
      • 1.8.1 SCSI Performance
      • 1.8.2 PCI Performance
      • 1.8.3 Integration
      • 1.8.4 Flexibility
      • 1.8.5 Reliability
      • 1.8.6 Testability
  • Chapter2 Functional Description
    • 2.1 Block Diagram Description
      • Figure2.1 LSI53C1020 Block Diagram
      • 2.1.1 Host Interface Module Description
      • 2.1.2 SCSI Channel Module Description
    • 2.2 Fusion-MPT Architecture Overview
    • 2.3 PCI Functional Description
      • 2.3.1 PCI Addressing
      • 2.3.2 PCI Commands and Functions
        • Table 2.1 PCI/PCI-X Bus Commands and Encodings
      • 2.3.3 PCI Arbitration
      • 2.3.4 PCI Cache Mode
      • 2.3.5 PCI Interrupts
      • 2.3.6 Power Management
        • Table 2.2 Power States
    • 2.4 Ultra320 SCSI Functional Description
      • 2.4.1 Ultra320 SCSI Features
        • Figure2.2 Paced Transfer Example
        • Figure2.3 Example of Precompensation
      • 2.4.2 SCSI Bus Interface
    • 2.5 External Memory Interfaces
      • 2.5.1 Flash ROM Interface
        • Table2.3 Flash ROM Size Programming
        • Figure2.4 Flash ROM Block Diagram
        • Table 2.4 Flash Signature Value
      • 2.5.2 NVSRAM Interface
        • Figure2.5 NVSRAM Diagram
    • 2.6 Serial EEPROM Interface
      • Table 2.5 PCI Configuration Record in Serial EEPROM
    • 2.7 Zero Channel RAID
      • Figure2.6 ZCR Circuit Diagram for the LSI53C1020 and LSI53C1000R
    • 2.8 Multi-ICE Test Interface
      • Table 2.6 20-Pin Multi-ICE Header Pinout
  • Chapter3 Signal Description
    • 3.1 Signal Organization
      • Figure3.1 LSI53C1020 Functional Signal Grouping
    • 3.2 PCI Bus Interface Signals
      • 3.2.1 PCI System Signals
        • Table3.1 PCI System Signals
      • 3.2.2 PCI Address and Data Signals
        • Table3.2 PCI Address and Data Signals
      • 3.2.3 PCI Interface Control Signals
        • Table3.3 PCI Interface Control Signals
      • 3.2.4 PCI Arbitration Signals
        • Table3.4 PCI Arbitration Signals
      • 3.2.5 PCI Error Reporting Signals
        • Table3.5 PCI Error Reporting Signals
      • 3.2.6 PCI Interrupt Signals
        • Table 3.6 PCI Interrupt Signal
    • 3.3 PCI-Related Signals
      • Table 3.7 PCI-Related Signals
    • 3.4 SCSI Interface Signals
      • Table 3.8 SCSI Bus Clock Signal
      • Table 3.9 SCSI Channel Interface Signals
      • Table 3.10 SCSI Channel Control Signals
    • 3.5 Memory Interface
      • Table 3.11 Flash ROM/NVSRAM Interface Signals
      • Table 3.12 Serial EEPROM Interface Signals
    • 3.6 Zero Channel RAID (ZCR) Interface
      • Table 3.13 ZCR Configuration Signals
    • 3.7 Test Interface
      • Table 3.14 JTAG, ICE, and Debug Signals
      • Table 3.15 LSI Logic Test Signals
    • 3.8 GPIO and LED Signals
      • Table3.16 GPIO and LED Signals
    • 3.9 Power and Ground Pins
      • Table 3.17 Power and Ground Pins
    • 3.10 Power-On Sense Pins Description
      • Table 3.18 MAD Power-On Sense Pin Options
      • Table3.19 Flash ROM Size Programming
    • 3.11 Internal Pull-Ups and Pull-Downs
      • Table3.20 Pull-Up and Pull-Down Signal Conditions
  • Chapter4 PCI Host Register Description
    • 4.1 PCI Configuration Space Register Description
      • Table 4.1 LSI53C1020 PCI Configuration Space Address Map
      • Table4.2 Subsystem ID Register Download Conditions and Values
      • Table4.3 Multiple Message Enable Field Bit Encoding
      • Table4.4 Maximum Outstanding Split Transactions
      • Table4.5 Maximum Memory Read Count
    • 4.2 I/O Space and Memory Space Register Description
      • Table 4.6 PCI I/O Space Address Map
      • Table 4.7 PCI Memory [0] Address Map
      • Table 4.8 PCI Memory [1] Address Map
      • Table4.9 Interrupt Signal Routing
  • Chapter5 Specifications
    • 5.1 DC Characteristics
      • Table 5.1 Absolute Maximum Stress Ratings
      • Table 5.2 Operating Conditions
      • Table 5.3 LVD Driver SCSI Signals � SACK�, SATN�, SBSY�, SCD�, SD[15:0]�, SDP[1:0]�, SIO�, SMSG�,...
      • Figure5.1 LVD Driver
      • Table 5.4 LVD Receiver SCSI Signals � SACK�, SATN�, SBSY�, SCD�, SD[15:0]�, SDP[1:0]�, SIO�, SMSG...
      • Figure5.2 LVD Receiver
      • Table 5.5 DIFFSENS SCSI Signal
      • Table 5.6 Input Capacitance
      • Table 5.7 8 mA Bidirectional Signals � GPIO[7:0], MAD[15:0], MADP[1:0], SerialDATA
      • Table 5.8 8 mA PCI Bidirectional Signals � ACK64/, AD[63:0], C_BE[7:0]/, DEVSEL/, FRAME/, IRDY/, ...
      • Table 5.9 Input Signals � CLK, CLKMODE_0, CLKMODE_1, DIS_PCI_FSN/, DIS_SCSI_FSN/, GNT/, IDDTN, ID...
      • Table 5.10 8 mA Output Signals � ADSC/, ADV/, ALT_INTA/, BWE[1:0]/, FLSHALE[1:0]/, FLSHCE/, INTA/...
      • Table 5.11 12 mA Output Signals � A_LED/, B_LED/, HB_LED/
    • 5.2 TolerANT Technology Electrical Characteristics
      • Table 5.12 TolerANT Technology Electrical Characteristics for SE SCSI Signals
      • Figure5.3 Rise and Fall Time Test Condition
      • Figure5.4 SCSI Input Filtering
    • 5.3 AC Characteristics
      • Table 5.13 External Clock
      • Figure5.5 External Clock
      • Table 5.14 Reset Input
      • Figure5.6 Reset Input
      • Table 5.15 Interrupt Output
      • Figure5.7 Interrupt Output
    • 5.4 External Memory Timing Diagrams
      • 5.4.1 NVSRAM Timing
        • Table 5.16 NVSRAM Read Cycle Timing
        • Figure5.8 NVSRAM Read Cycle
        • Figure5.8 NVSRAM Read Cycle (Cont.)
        • Table 5.17 NVSRAM Write Cycle
        • Figure5.9 NVSRAM Write Cycle
        • Figure5.9 NVSRAM Write Cycle (Cont.)
      • 5.4.2 Flash ROM Timing
        • Table 5.18 Flash ROM Read Cycle Timing
        • Figure5.10 Flash ROM Read Cycle
        • Figure5.10 Flash ROM Read Cycle (Cont.)
        • Table 5.19 Flash ROM Write Cycle
        • Figure5.11 Flash ROM Write Cycle
        • Figure5.11 Flash ROM Write Cycle (Cont.)
    • 5.5 Package Drawings
      • Figure5.12 LSI53C1020 456-Pin BGA Top View
      • Figure5.12 LSI53C1020 456-Pin BGA Top View (Cont.)
      • Figure5.13 456-Pin EPBGA (KY) Mechanical Drawing
  • AppendixA Register Summary
    • TableA.1 LSI53C1020 PCI Registers
    • TableA.2 LSI53C1020 PCI I/O Space Registers
    • TableA.3 LSI53C1020 PCI Memory [0] Registers
  • Customer Feedback
  • Index
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