Document Outline

• LSI53C825A/825AE PCI to SCSI I/O Processor
  • Chapter1 Introduction
    • 1.1 General Description
    • 1.2 Package and Feature Options
      • 1.2.1 PCI Pad Power-up Sequence
    • 1.3 TolerANT� Technology
    • 1.4 LSI53C825A Benefits Summary
      • 1.4.1 SCSI Performance
      • 1.4.2 PCI Performance
      • 1.4.3 Integration
      • 1.4.4 Ease of Use
      • 1.4.5 Flexibility
      • 1.4.6 Reliability
      • 1.4.7 Testability
        • Figure1.1 LSI53C825A External Memory Interface
        • Figure1.2 LSI53C825A Chip Block Diagram
  • Chapter2 Functional Description
    • 2.1 PCI Addressing
      • 2.1.1 Configuration Space
      • 2.1.2 PCI Bus Commands and Functions Supported
        • Table 2.1 PCI Bus Commands and Encoding Types
      • 2.1.3 PCI Cache Mode
    • 2.2 SCSI Functional Description
      • 2.2.1 SCSI Core
      • 2.2.2 DMA Core
      • 2.2.3 SCRIPTS Processor
      • 2.2.4 Internal SCRIPTS RAM
      • 2.2.5 SDMS: The Total SCSI Solution
      • 2.2.6 Prefetching SCRIPTS Instructions
      • 2.2.7 Opcode Fetch Burst Capability
    • 2.3 External Memory Interface
      • Table 2.2 External Memory Support
    • 2.4 PCI Cache Mode
      • 2.4.1 Load and Store Instructions
      • 2.4.2 3.3 V/5 V PCI Interface
      • 2.4.3 Additional Access to General Purpose Pins
      • 2.4.4 JTAG Boundary Scan Testing
      • 2.4.5 Big and Little Endian Support
      • 2.4.6 Loopback Mode
      • 2.4.7 Parity Options
        • Table 2.3 Bits Used for Parity Control and Generation
        • Table 2.4 SCSI Parity Control
        • Table 2.5 SCSI Parity Errors and Interrupts
      • 2.4.8 DMA FIFO
        • Figure2.1 DMA FIFO Sections
        • Figure2.2 LSI53C825A Host Interface Data Paths
      • 2.4.9 SCSI Bus Interface
        • Table 2.6 Differential Mode
        • Figure2.3 LSI53C825A Differential Wiring Diagram
        • Figure2.4 Regulated Termination
      • 2.4.10 Select/Reselect During Selection/Reselection
      • 2.4.11 Synchronous Operation
      • 2.4.12 Achieving Optimal SCSI Send Rates
        • Figure2.5 Determining the Synchronous Transfer Rate
      • 2.4.13 Interrupt Handling
      • 2.4.14 Chained Block Moves
        • Figure2.6 Block Move and Chained Block Move Instructions
    • 2.5 Power Management
      • 2.5.1 Power State D0
      • 2.5.2 Power State D3
  • Chapter3 Signal Descriptions
    • Figure3.1 LSI53C825A Pin Diagram
    • Figure3.2 LSI53C825AJ Pin Diagram
    • Table 3.1 LSI53C825A, LSI53C825AJ, LSI53C825AE, and LSI53C825AJE Power and Ground Pins
    • Figure3.3 LSI53C825A Functional Signal Grouping
    • 3.1 PCI Bus Interface Signals
      • 3.1.1 System Signals
        • Table 3.2 System Signals
      • 3.1.2 Address and Data Signals
        • Table 3.3 Address and Data Signals
      • 3.1.3 Interface Control Signals
        • Table 3.4 Interface Control Signals
      • 3.1.4 Arbitration Signals
        • Table 3.5 Arbitration Signals
      • 3.1.5 Error Reporting Signals
        • Table 3.6 Error Reporting Signals
      • 3.1.6 SCSI Bus Interface Signals
        • Table 3.7 SCSI Bus Interface Signals
      • 3.1.7 Additional Interface Signals
        • Table 3.8 Additional Interface Signals
      • 3.1.8 External Memory Interface Signals
        • Table 3.9 External Memory Interface Signals
      • 3.1.9 JTAG Signals
        • Table 3.10 JTAG Signals (LSI53C825AJ, LSI53C825AJE Only)
    • 3.2 MAD Bus Programming
      • Table 3.11 Subsystem Data Configuration Table for the LSI53C825AE (PCI Rev ID 0x26)
      • Table 3.12 Subsystem Data Configuration Table for the LSI53C825A (PCI Rev ID 0x14) Revision G Only
      • Table 3.13 External Memory Support
  • Chapter4 Registers
    • 4.1 Configuration Registers
      • Table 4.1 PCI Configuration Register Map
    • 4.2 Operating Registers
      • Table 4.2 LSI53C825A Register Map
      • Table 4.3 Synchronous Clock Conversion Factor
      • Table 4.4 Examples of Synchronous Transfer Periods and Rates for SCSI-1
      • Table 4.5 Example Transfer Periods and Rates for Fast SCSI-2
      • Table 4.6 Maximum Synchronous Offset
      • Table 4.7 Timeout Periods
      • Table 4.8 Timeout Periods, 50 MHz Clock
  • Chapter5 SCSI SCRIPTS Instruction Set
    • 5.1 Low Level Register Interface Mode
    • 5.2 High Level SCSI SCRIPTS Mode
      • Table 5.1 SCRIPTS Instructions
      • 5.2.1 Sample Operation
        • Figure5.1 SCRIPTS Overview
    • 5.3 Block Move Instructions
      • 5.3.1 First Dword
        • Figure5.2 Block Move Instruction Register
      • 5.3.2 Second Dword
    • 5.4 I/O Instruction
      • 5.4.1 First Dword
        • Figure5.3 I/O Instruction Register
      • 5.4.2 Second Dword
    • 5.5 Read/Write Instructions
      • 5.5.1 First Dword
        • Figure5.4 Read/Write Instruction Register
      • 5.5.2 Second Dword
      • 5.5.3 Read-Modify-Write Cycles
      • 5.5.4 Move To/From SFBR Cycles
        • Table 5.2 Read/Write Instructions
    • 5.6 Transfer Control Instructions
      • 5.6.1 First Dword
        • Figure5.5 Transfer Control Instruction
      • 5.6.2 Second Dword
    • 5.7 Memory Move Instructions
      • 5.7.1 First Dword
      • 5.7.2 Read/Write System Memory from SCRIPTS
      • 5.7.3 Second Dword
      • 5.7.4 Third Dword
        • Figure5.6 Memory Move Instruction
    • 5.8 Load and Store Instructions
      • 5.8.1 First Dword
      • 5.8.2 Second Dword
        • Figure5.7 Load and Store Instruction Format
  • Chapter6 Specifications
    • 6.1 DC Characteristics
      • Table 6.1 Absolute Maximum Stress Ratings
      • Table 6.2 Operating Conditions
      • Table 6.3 SCSI Signals�SD[15:0]/, SDP[1:0]/, SREQ/, SACK/
      • Table 6.4 SCSI Signals�SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/
      • Table 6.5 Input Signals�CLK, SCLK, GNT/, IDSEL, RST/, TESTIN, DIFFSENS, BIG_LIT/
      • Table 6.6 Capacitance
      • Table 6.7 Output Signals�MAC/_TESTOUT, REQ/
      • Table 6.8 Output Signals�IRQ/, SDIR[15:0], SDIRP0, SDIRP1, BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/...
      • Table 6.9 Output Signal�SERR/
      • Table 6.10 Bidirectional Signals�AD[31:0], C_BE[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/...
      • Table 6.11 Bidirectional Signals�GPIO0_FETCH/, GPIO1_MASTER/, GPIO2_MAS2/, GPIO3, GPIO4
      • Table 6.12 Bidirectional Signals�MAD[7:0]
      • Table 6.13 Input Signals�TDI, TMS, TCK (LSI53C825AJ only)
      • Table 6.14 Output Signal�TDO (LSI53C825AJ only)
    • 6.2 TolerANT Technology Electrical Characteristics
      • Table 6.15 TolerANT Technology Electrical Characteristics
      • Figure6.1 Rise and Fall Time Test Conditions
      • Figure6.2 SCSI Input Filtering
      • Figure6.3 Hysteresis of SCSI Receivers
      • Figure6.4 Input Current as a Function of Input Voltage
      • Figure6.5 Output Current as a Function of Output Voltage
    • 6.3 AC Characteristics
      • Table 6.16 External Clock
      • Figure6.6 External Clock
      • Table 6.17 Reset Input
      • Figure6.7 Reset Input
      • Table 6.18 Interrupt Output
      • Figure6.8 Interrupt Output
    • 6.4 PCI and External Memory Interface Timing Diagrams
      • 6.4.1 Target Timing
        • Figure6.9 PCI Configuration Register Read
        • Figure6.10 PCI Configuration Register Write
        • Figure6.11 Operating Register/SCRIPTS RAM Read
        • Figure6.12 Operating Register/SCRIPTS RAM Write
        • Figure6.13 External Memory Read
        • Figure6.14 External Memory Write
      • 6.4.2 Initiator Timing
        • Figure6.15 Nonburst Opcode Fetch
        • Figure6.16 Burst Opcode Fetch
        • Figure6.17 Back-to-Back Read
        • Figure6.18 Back-to-Back Write
        • Figure6.19 Burst Read
        • Figure6.20 Burst Write
      • 6.4.3 External Memory Timing
        • Figure6.21 Read Cycle, Normal/Fast Memory (� 64 Kbytes), Single Byte Access
        • Figure6.22 Write Cycle, Normal/Fast Memory (� 64 Kbytes), Single Byte Access
        • Figure6.23 Read Cycle, Normal/Fast Memory (� 64 Kbytes), Multiple Byte Access
        • Figure6.24 Write Cycle, Normal/Fast Memory (� 64 Kbytes), Multiple Byte Access
        • Figure6.25 Read Cycle, Slow Memory (� 64 Kbytes)
        • Figure6.26 Write Cycle, Slow Memory (� 64 Kbytes)
        • Figure6.27 Read Cycle, Normal/Fast Memory (� 64 Kbytes)
        • Figure6.28 Write Cycle, Normal/Fast Memory (� 64 Kbytes)
        • Figure6.29 Read Cycle, Slow Memory (� 64 Kbytes)
        • Figure6.30 Write Cycle, Slow Memory (� 64 Kbytes)
    • 6.5 PCI and External Memory Interface Timing
      • Table 6.19 LSI53C825A PCI and External Memory Interface Timing
    • 6.6 SCSI Timing Diagrams
      • Table 6.20 Initiator Asynchronous Send
      • Figure6.31 Initiator Asynchronous Send
      • Table 6.21 Initiator Asynchronous Receive
      • Figure6.32 Initiator Asynchronous Receive
      • Table 6.22 Target Asynchronous Send
      • Figure6.33 Target Asynchronous Send
      • Table 6.23 Target Asynchronous Receive
      • Figure6.34 Target Asynchronous Receive
      • Figure6.35 Initiator and Target Synchronous Transfers
      • Table 6.24 SCSI-1 Transfers (SE 5.0 Mbytes)
      • Table 6.25 SCSI-1 Transfers (Differential, 4.17 Mbytes/s)
      • Table 6.26 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transf...
      • Table 6.27 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transfers...
    • 6.7 Package Drawings
      • Figure6.36 LSI53C825A 160 Pin PQFP (PF) Mechanical Drawing
  • AppendixA Register Summary
    • TableA.1 Configuration Registers
    • TableA.2 LSI53C825A Register Map
  • AppendixB External Memory Interface Diagram Examples
    • FigureB.1 64 Kbyte Interface with 200 ns Memory
    • FigureB.2 64 Kbyte Interface with 150 ns Memory
    • FigureB.3 256 Kbyte Interface with 150 ns Memory
    • FigureB.4 512 Kbyte Interface with 150 ns Memory
  • Index
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