ii
Copyright 19992001 by LSI Logic Corporation. All rights reserved.
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB14-000121-03, Fourth Edition (December 2001)
This document describes LSI Logic Corporation's ZSP400 Digital Signal
Processing Architecture and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of LSI
Logic or third parties.
Copyright 19992001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, CoreWare, and ZSP are trademarks or registered
trademarks of LSI Logic Corporation. All other brand and product names may be
trademarks of their respective companies.
GL
To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/na_salesoffices.html
ZSP400 Digital Signal Processor Architecture Technical Manual
iii
Copyright 19992001 by LSI Logic Corporation. All rights reserved.
Preface
This book is the primary reference and Technical Manual of the LSI Logic
ZSP400 Digital Signal Processor Architecture. It contains a functional
description of the architecture and details the instruction set.
Audience
This document assumes that you have some familiarity with
microprocessors and related support devices. The people who benefit
from this book are:
Engineers and managers who are evaluating the ZSP400
architecture for possible use in a system
Engineers who are designing a device based on the ZSP400
architecture into a system
Engineers who are programming a device based on the ZSP400
architecture
Organization
This document has the following chapters and appendixes:
Chapter 1, Introduction
, introduces the features of the ZSP400 DSP
architecture and the instruction set.
Chapter 2, ZSP400 Architecture Overview
, briefly describes the
functional blocks that make up a ZSP400 device.
Chapter 3, Control Registers
, describes the control registers and
mode bits of a ZSP400 device.
Chapter 4, Pipeline Control Unit
, describes the pipeline operation,
the control register file, interrupts, and instruction grouping.
iv
Preface
Copyright 19992001 by LSI Logic Corporation. All rights reserved.
Chapter 5, Instruction Unit
, describes the instruction control unit,
which is responsible for fetching instructions from memory and
forwarding them to the pipeline.
Chapter 6, Data Unit
, describes the data unit, which is responsible
for fetching data from memory and forwarding it to the pipeline. The
data unit also handles data linking.
Chapter 7, Execution Unit
, describes the arithmetic logic units and
multiply/accumulate units.
Chapter 8, ZSP400 Instruction Set
, describes the ZSP400
instruction set in detail.
Related Publications
LSI402Z Digital Signal Processor User's Guide, document number
DB15-000131-01
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive. Signals that are active
LOW end in an "n."
Hexadecimal numbers are indicated by the prefix "0x" --for example,
0x32CF. Binary numbers are indicated by the prefix "0b" --for example,
0b0011.0010.1100.1111.
ZSP400 Digital Signal Processor Architecture Technical Manual
v
Copyright 19992001 by LSI Logic Corporation. All rights reserved.
Contents
Chapter 1
Introduction
1.1
ZSP400 Architecture Overview
1-1
1.2
Instruction Set Highlights
1-3
1.3
Available Implementations
1-5
Chapter 2
ZSP400 Architecture Overview
2.1
Typical ZSP400 System
2-1
2.2
Control Register File
2-3
2.3
Pipeline Control Unit
2-3
2.4
Instruction Unit
2-3
2.5
Data Unit
2-4
2.6
Execution Unit
2-4
2.7
Device Emulation Unit
2-4
Chapter 3
Control Registers
3.1
Introduction
3-2
3.2
Address Mode Register (%amode)
3-4
3.3
Circular Buffer 0 Begin Address Register (%cb0_beg)
3-5
3.4
Circular Buffer 0 End Address Register (%cb0_end)
3-6
3.5
Circular Buffer 1 Begin Address Register (%cb1_beg)
3-6
3.6
Circular Buffer 1 End Address Register (%cb1_end)
3-7
3.7
Device Emulation Data Register (%ded)
3-7
3.8
Device Emulation Instruction Register (%dei)
3-7
3.9
Functional Mode Register (%fmode)
3-8
3.10
Guard Bits for {r1 r0} and {r3 r2}
3-9
3.11
Hardware Flag Register (%hwflag)
3-10
3.12
Interrupt Mask Register (%imask)
3-12
3.13
Interrupt Priority Register 0 (%ip0)
3-14
3.14
Interrupt Priority Register 1 (%ip1)
3-15
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