ICM102A CIF CMOS sensor

Data Sheet Version 1.0 July 2002

7/24/2002

web site:

http://www.ic- media.com/

web site:

http://www.ic- media.com.tw/

page 1

ICM102A CIF CMOS image sensor

Data Sheet

V1.0

July 2002

IC Media Corporation

545 East Brokaw Road

San Jose, CA 95112, U.S.A.
Phone: (408) 451-8838

Fax: (408) 451-8839
Email: Sales@IC-Media.Com

Web Site:

www.ic-media.com

IC Media Technology Corporation

6F, No. 61, ChowTze Street., NeiHu District

Taipei, Taiwan, R.O.C.
Phone: 886-2-2657-7898

Fax: 886-2-2657-8751
Email: Ap.Sales@IC-Media.Com.tw

Web Site: www.ic-media.com.tw

Important notice: This document contains information of a new product. IC Media

Corp. reserves the right to make any changes without further notice to any product

herein to improve design, function or quality and reliability. No responsibility is

assumed by IC Media Corp. for its use, nor for any infringements of patents of third

parties that may result from its use.

ICM102A CIF CMOS sensor

Data Sheet Version 1.0 July 2002

7/24/2002

web site:

http://www.ic- media.com/

web site:

http://www.ic- media.com.tw/

page 2

Features

101,376 (352x288) pixels, CIF format, used with 1/7" optical system

Progressive readout

Output data format: 8-bit raw data

Control interface: SIF

Electronic exposure control

On-chip 9-bit ADC

Correlated double sampling

Video mode at frame rate of 30/15/10/6/5/3/2/1 fps

Dead column removal

Flash light control

Power down mode

Automatic optical black compensation

Support both master and slave mode

Mirror image

Single 3.3 V power supply

General Description

ICM-102A is a single-chip digital color imaging device. It incorporates a 352x288 sensor array (362x298 in
physical layout) operating at 1 ~ 30 frames per second in progressive manner. Each pixel is covered by a

color filter, which formed a so -called Bayer pattern. Correlated double sampling is performed by the
internal ADC and timing circuitry. The raw data can be adjusted by the digital gain for all pixels, or be

adjusted separately for the 4 Bayer pattern pixels. The output format is 8-bit raw data which can be fed to
other DSP, color processing, or compression chips.

Application

Digital camcorder

Digital still camera

Video phone

Video conferencing

Video mail

Video cellular phone

PC camera

Security system

Visual toy

Industrial image capture/analysis

Environment monitor system

Key Parameters

Number of Active Pixels: 352x288

Number of Physical Pixels: 362x298

Frame Rate: 30/15/10/6/5/3/2/1 fps

ICM102A CIF CMOS sensor

Data Sheet Version 1.0 July 2002

7/24/2002

web site:

http://www.ic- media.com/

web site:

http://www.ic- media.com.tw/

page 3

Pixel Size: 6.0

m x 6.0

Sensor Area: 2.2 mm x 1.8 mm

Main Clock Frequency: up to 12 MHz

Exposure Time: 83

s (@ 30 fps, 1 line, 12 MHz) ~ 164 s (@ 1 fps, 65,535 lines, 12 MHz)

RGB Gain:1/256 to 8 for individual Bayer pattern pixels

Sensitivity: 2.0 V/lux-sec (555 nm)

Quantum Efficiency: 38% (555 nm)

Dynamic Range: 53 dB (analog), 48 dB(digital)

Digital Gain: 1 ~ 64 x @ 2

for all pixels

Fill Factor: 28%

RGB Gain: 11 bits format 3.8(default), 1/256 to 8 for individual Bayer pattern pixels

S/N Ratio: 40 dB @ 75% full signal level

Sensitive to infrared illumination source

Power Supply: 3.3 V

Power Requirement: 25 mA (@ 30fps, 12 MHz)

Package: Ceramic LCC48, Plastic LCC48, Shrunk Plastic LCC48, miniature lens module (dimension

8mm x 8mm x 5.8mm)

ICM102A CIF CMOS sensor

Data Sheet Version 1.0 July 2002

7/24/2002

web site:

http://www.ic- media.com/

web site:

http://www.ic- media.com.tw/

page 4

1. Pin Assignment

Pin #

Name

Class*

Function

CLKSEL

D, I, N Clock source selection. 0: internal oscillator, 1:

CLKIN

D, I, N External clock source

XIN

A, I

Oscillator in

XOUT

A, O

Oscillator out

PCLK

D, O

Pixel clock output

OEN

D, I, N Output enable. 0: enable, 1: disable

SIFID

D, I, N Lsb of SIF slave address

MSSEL

D, I, U

SIF master/slave selection. 0: slave, 1: master

SCL

I/O

SIF clock

SDA

D,
I/O

SIF data

POWERDN

D, I, N Power down control, 0: power down, 1: active

RSET

A, I

Resistor to ground = 39 K

@ 12 MHz main clock

RSTN

D, I, U

Chip reset, active low

DOUT[7]

D, O

Data output bit 7

DOUT[6]

D,
I/O

Data output bit 6; if pulled up/down, the initial
value of TIMING_CONTROL_LOW[2] (VSYNC

polarity) is 1/0

DOUT[5]

I/O

Data output bit 5; if pulled up/down, the initial

value of TIMING_CONTROL_LOW[1] (HSYNC
polarity) is 1/0

DOUT[4]

I/O

Data output bit 4; if pulled up/down, the initial

value of AD_IDL[3] (Sub ID) is 1/0

DOUT[3]

I/O

Data output bit 3; if pulled up/down, the initial

value of AD_IDL[2] (Sub ID) is 1/0

DOUT[2]

I/O

Data output bit 2; if pulled up/down, the initial

value of AD_IDL[1] (Sub ID) is 1/0

DOUT[1]

D,
I/O

Data output bit 1; if pulled up/down, the initial
value of AD_IDL[0] (Sub ID) is 1/0

DOUT[0]

D,
I/O

Data output bit 0; if pulled up/down, the
synchronization mode is in master/slave mode

which requires HSYNC and VSYNC operating in
output/input mode

HSYNC

D,
I/O

Horizontal sync signal

VSYNC

I/O

Vertical sync signal

FLASH

D, O

Flash light control

RAMP

A, O

Analog ramp output

7, 31

VDDA

Sensor analog power

9, 30

GNDA

Sensor analog ground

VDDD

Sensor digital power

GNDD

Sensor digital ground

ICM102A CIF CMOS sensor

Data Sheet Version 1.0 July 2002

7/24/2002

web site:

http://www.ic- media.com/

web site:

http://www.ic- media.com.tw/

page 5

4, 43

VDDK

Digital power

6, 45

GNDK

Digital ground

VDDO

Pad power

GNDO

Pad ground

GNDS

Substrate ground

Class Code: A Analog signal, D Digital signal, I Input, O Output, P Power or ground, U Internal
pull-up, N Internal pull-down

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ICM102A