GT-48001A
Switched Ethernet Controller
for 10BaseX
Preliminary
Revision 1.6
12/29/97
Please contact Galileo Technology for possible
updates before finalizing a design.
FEATURES
www.galileoT.com support@galileoT.com Tel: +1-408.367.1400 Fax: +1-408.367.1401
Single-chip, low cost, Switched Ethernet Controller
- Provides packet switching functions between 8 on-
chip Ethernet ports and the PCI expansion port
- Switch expansion via 1Gbps PCI bus
GalNet Architecture Family Member
- Advanced distributed switching architecture
- Connects seamlessly to other GalNet Family
Devices
- GT-48002A 100BaseX and GT-48003 100VG-
AnyLAN devices available
Incorporates eight 802.3 compliant Ethernet ports
- 10Mbps half-duplex or full-duplex 20Mbps Ethernet
for each port
- Serial mode selectable per port: 10Base-T,
10Base-FL, AUI, and NRZ Synchronous
All digital logic on-chip for each port
- Media Access Control (MAC)
- Manchester encoder/decoder
- Link integrity, Partition
- Automatic polarity detection and correction
- Dual 32-byte FIFOs for receive and transmit
- 7 LEDs for
Link Status, Receive, Transmit,
Collision, Forward Unknown Packets, Port Sniffer,
and Half/Full Duplex
- CRC generation for CPU generated packets
High-Performance Distributed Switching Engine
- Performs forwarding and filtering at full wire speed
- 14,880 packets/sec on each Ethernet port
- Flexible software or hardware intervention in
packet routing decisions
Supports `Store and Forward' switching approach
- Low last-bit in to first-bit out delay
- Allows bridging between higher/lower speed
interfaces (Fast Ethernet, ATM, WAN)
Advanced address recognition
- Intelligent address recognition mechanism enables
forwarding rate at full wire speed
- Self-learning mechanism
- Supports up to 8K Unicast addresses and
unlimited Multicast/Broadcast addresses
- Broadcast storm rate filtering
Direct support for packet buffering
- Glueless interface to 1 or 2Mbyte of 60ns EDO
DRAM
- Up to 1K buffers, 1536-bytes each, dynamically
allocated to the receive and PCI ports
PCI Rev 2.1 interface for switch expansion and
management CPU connection
- Up to 10 GT-48001A devices per PCI bus without
PCI-to-PCI bridging
- Up to 32 GalNet devices in a single switch
- Standard CPU connection for management
- Simple interface to other networking interfaces
(ATM, FDDI, etc.)
Extensive network management support
- Repeater MIB and PCI counters
- Address aging support
- Hardware assist for Spanning Tree algorithm
- RMON Station-to-Station connectivity matrix
- CPU access to Address Table
- Ability to define static addresses
- Monitoring (sniffer) mode
HP-EASE Packet sampling management technology
- Takes "snapshots" of packets at programmable
intervals
- Allows for the implementation of HP-EASE or
sampled RMON with low-cost CPUs
208 pin PQFP package
DMA
Transmit
Receive
Collision
Forwarding Unknown
Sniffer
Half/Full Duplex
Status
Switching
Engine
PCI Bus
Data
Address
Control
PCI Bus Controller
Self-Learning &
Address
Recognition
Engine
DRAM
Controller
Frame
Controller
G
AL
N
ET
Controller
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 0
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 1
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 2
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 3
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 4
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 5
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 6
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 7
RMON FIFO
Control
Control
PCI Counters
8 x MIB Counters
PCI
Address Table
Statistics Counters
Configuration Registers
Intervention
Mode
Control
Packet Buffers
Serial
Switching
G
AL
N
ET
Sniffer
Control
Miscellaneous
8 x
LED
Control
Tx Rx
FIFO FIFO
Tx Rx
FIFO FIFO
Tx Rx
FIFO FIFO
Tx Rx
FIFO FIFO
Tx Rx
FIFO FIFO
Tx Rx
FIFO FIFO
Tx Rx
FIFO FIFO
Tx Rx
FIFO FIFO
DMA
GT-48001A Switched Ethernet Controller
2
Revision 1.6
Contents
1. Functional Overview ........................................................................................................... 6
1.1
The GalNet Switching Architecture .......................................................................................................... 6
1.2
Ethernet Ports .......................................................................................................................................... 6
1.3
Address Recognition ................................................................................................................................ 7
1.4
CPU Packet Routing ................................................................................................................................ 7
1.5
Intervention Mode ..................................................................................................................................... 7
1.6
Network Management Features ............................................................................................................... 7
1.7
DRAM Interface ........................................................................................................................................ 7
1.8
PCI Interface ............................................................................................................................................ 7
2. Pin Information .................................................................................................................... 8
2.1
Logic Symbol ............................................................................................................................................ 8
2.2
Pin Functions and Assignment ................................................................................................................ 9
3. Operational Overview ....................................................................................................... 13
3.1
Enabling/Disabling the GT-48001A ........................................................................................................ 13
3.2
Basic Operation ...................................................................................................................................... 13
3.3
Address Learning ................................................................................................................................... 14
3.4
Packet Buffering ..................................................................................................................................... 14
3.5
Packet Forwarding ................................................................................................................................. 14
3.6
The GalNet Protocol ............................................................................................................................... 14
3.7
Terminology ............................................................................................................................................ 14
4. MAC Address Learning Process...................................................................................... 16
4.1
Address Recognition .............................................................................................................................. 16
4.2
Recovery Process .................................................................................................................................. 16
4.3
Address Aging ........................................................................................................................................ 17
4.4
Static Addresses .................................................................................................................................... 17
4.5
Address Recognition Failure .................................................................................................................. 17
5. GT-48001A Buffers and Queues ...................................................................................... 18
5.1
Receive Buffer Threshold Programming ................................................................................................ 19
6. Packet Forwarding ............................................................................................................ 20
6.1
Forwarding a Unicast Packet to a Local Port ......................................................................................... 20
6.2
Forwarding a Unicast Packet to a Port in a Different GalNet Device ..................................................... 20
6.3
Forwarding a Multicast Packet ............................................................................................................... 21
6.3.1
Local Ports .............................................................................................................................. 21
6.3.2
Between GalNet Devices ........................................................................................................ 21
6.3.2.1
CPU Disabled ......................................................................................................... 21
6.3.2.2
CPU Enabled .......................................................................................................... 21
6.4
Forwarding a Packet to the CPU Directly ............................................................................................... 22
6.5
Forwarding a Packet from the CPU to a GalNet Device ........................................................................ 24
6.6
CRC Generation ..................................................................................................................................... 25
6.7
Tx Watchdog Timer ................................................................................................................................ 25
7. Device Table Operation .................................................................................................... 26
7.1
Automatic Device Table Initialization ...................................................................................................... 26
7.2
Manual Device Table Initialization .......................................................................................................... 26
7.3
Programming Device Numbers .............................................................................................................. 26
GT-48001A Switched Ethernet Controller
Revision 1.6
3
8. Unicast Intervention Mode ................................................................................................ 27
8.1
Unicast Intervention Mode Address Space ............................................................................................ 28
9. Address Table .................................................................................................................... 29
10. GalNet Messaging Protocol .............................................................................................. 31
10.1 GalNet Protocol Region ......................................................................................................................... 31
10.2 GalNet Messages Between Devices ..................................................................................................... 33
10.2.1 NEW_ADDRESS Message between GalNet devices ............................................................ 33
10.2.2 BUFFER_REQUEST Message between GalNet devices ...................................................... 34
10.2.3 START_OF_PACKET Message between GalNet devices ..................................................... 34
10.2.4 PACKET_TRANSFER Message between GalNet devices .................................................... 35
10.2.5 END_OF_PACKET Message between GalNet devices ......................................................... 35
10.3 GalNet Messages Between a GalNet Device and a CPU ...................................................................... 36
10.3.1 NEW_ADDRESS Message (GalNet to CPU) ......................................................................... 36
10.3.2 NEW_ADDRESS Message (CPU to GalNet) ......................................................................... 37
10.3.3 BUFFER_REQUEST Message (GalNet to CPU) ................................................................... 38
10.3.4 BUFFER_REQUEST Message (CPU to GalNet) ................................................................... 38
10.3.5 START_OF_PACKET Message (GalNet to CPU).................................................................. 39
10.3.6 START_OF_PACKET Message (CPU to GalNet).................................................................. 39
10.3.7 PACKET_TRANSFER Message (GalNet to CPU 16 Block Buffer)........................................ 40
10.3.8 PACKET_TRANSFER Message (GalNet to CPU in Unicast Intervention Mode)................... 41
10.3.9 PACKET_TRANSFER Message (CPU to GalNet) ................................................................. 41
10.3.10 END_OF_PACKET Message (GalNet to CPU 16 Block Buffer)............................................. 42
10.3.11 END_OF_PACKET Message (GalNet to CPU in Unicast Intervention Mode) ....................... 42
10.3.12 END_OF_PACKET Message (CPU to GalNet) ...................................................................... 43
11. PCI Bus Operation ............................................................................................................. 44
11.1 PCI Configuration Header Registers ..................................................................................................... 44
11.2 Accessing DRAM and Internal Registers through the PCI Interface ...................................................... 44
11.3 PCI Bandwidth/Performance Issues ...................................................................................................... 44
11.4 Plug-and-Play Considerations In PCI Systems ...................................................................................... 45
11.5 Unused PCI Bus in Stand-Alone Systems ............................................................................................. 45
11.6 PCI Bus Arbiter in Multiple GalNet Device Systems .............................................................................. 45
12. Ethernet Interfaces ............................................................................................................ 46
12.1 Media Access Control (MAC) ................................................................................................................ 46
12.2 Illegal Frames ........................................................................................................................................ 46
12.3 Selecting the Duplex Mode .................................................................................................................... 46
12.3.0.1 Packet Transmission .............................................................................................. 46
12.4 Backoff Algorithm Options ..................................................................................................................... 46
12.5 Manchester Encoder/Decoder ............................................................................................................... 46
12.6 Link Integrity and Auto Polarity Detector ............................................................................................... 47
12.7 Data Blinder ........................................................................................................................................... 47
12.8 Inter-Packet Gap (IPG) .......................................................................................................................... 47
12.9 Partition Mode ........................................................................................................................................ 47
12.9.1 Enabling Partition Mode ......................................................................................................... 47
12.9.2 Entering Partition State........................................................................................................... 47
12.9.3 Exiting from Partition State ..................................................................................................... 47
12.10 Back-pressure ........................................................................................................................................ 48
12.11 VLAN Tagging Support .......................................................................................................................... 48
12.12 Serial Modes .......................................................................................................................................... 48
12.12.1 Signal Polarity in Specific Serial Modes ................................................................................. 48
12.12.2 10BaseT Mode ....................................................................................................................... 48
GT-48001A Switched Ethernet Controller
4
Revision 1.6
12.12.2.1 Generating the Required 10BaseT Signals ............................................................ 49
12.12.2.2 Pol Output/Auto-Polarity in 10BaseT ...................................................................... 50
12.12.3 10BaseFL Mode...................................................................................................................... 51
12.12.4 AUI Mode ............................................................................................................................. 52
12.12.4.1 TxD Pins ................................................................................................................. 52
12.12.4.2 AUILinkUp............................................................................................................... 52
12.12.4.3 Setting DAddr[6] on Reset ...................................................................................... 52
12.12.5 Synchronous Mode ................................................................................................................. 53
13. Network Management Support ........................................................................................ 55
13.1 Repeater MIB and PCI Counters ........................................................................................................... 55
13.2 Station-to-Station Connectivity Matrix .................................................................................................... 55
13.2.1 Data Structure Format............................................................................................................. 56
13.3 Monitoring (Sniffer) Mode ....................................................................................................................... 57
13.4 Spanning Tree Support .......................................................................................................................... 57
13.5 Broadcast Storm Filtering ....................................................................................................................... 57
14. HP-EASE Packet Sampling Technology ......................................................................... 58
14.1 HP EASE Technology Overview ............................................................................................................ 58
14.2 EASE Functionality on the GT-48001A .................................................................................................. 59
14.3 Ease_Register ........................................................................................................................................ 59
14.4 EASE Interrupts ...................................................................................................................................... 59
14.5 Sampled Packet Indication ..................................................................................................................... 60
14.6 Error Source Indications ......................................................................................................................... 61
14.7 Enabling/Disabling EASE Functionality .................................................................................................. 62
14.8 Interaction With Other GT-48001A Features .......................................................................................... 62
15. DRAM Interface and Usage .............................................................................................. 63
16. LED Support ...................................................................................................................... 63
16.1 Led Indications Interface Description ..................................................................................................... 63
16.2 LED Serial Interface Description ........................................................................................................... 63
16.3 Detailed LED Signal Description ........................................................................................................ 64
16.3.1 Primary Port Status LED ........................................................................................................ 64
16.3.1.1 Primary Port Status LED (Mode 0): (LEDMode input is LOW) .............................. 64
16.3.1.2 Status LED blink timing (Mode 0) .......................................................................... 64
16.3.1.3 Primary Port Status LED (Mode 1): (LEDMode input is HIGH).............................. 65
16.3.2 Transmit data in progress ....................................................................................................... 66
16.3.3 Receive data in progress ........................................................................................................ 66
16.3.4 Collision active ........................................................................................................................ 66
16.3.5 Full/Half duplex ....................................................................................................................... 66
16.3.6 Receive Buffer Full.................................................................................................................. 66
16.3.7 Forwarding of unknown packets enabled................................................................................ 66
16.3.8 The port is configured as Sniffer ............................................................................................. 66
16.3.9 Link Fail State ......................................................................................................................... 66
16.3.10 Partition State.......................................................................................................................... 66
16.4 LED Signals Timing Type ....................................................................................................................... 66
16.4.1 Static LED Signals .................................................................................................................. 66
16.4.2 Dynamic Internal Signals: ....................................................................................................... 66
16.4.3 Table of Internal Activities/Status Driven via the LED Interface............................................. 66
17. Interrupts............................................................................................................................ 69
GT-48001A Switched Ethernet Controller
Revision 1.6
5
18. RESET Configuration ........................................................................................................ 69
18.1 Configuration Pins ................................................................................................................................. 69
18.2 Configuration Input Timings ................................................................................................................... 69
19. Switch Expansion .............................................................................................................. 70
20. Development Tools............................................................................................................ 71
20.1 Evaluation Platforms .............................................................................................................................. 71
20.2 Verilog Models ....................................................................................................................................... 71
20.3 Reference Designs ................................................................................................................................ 71
20.4 Complimentary Products ....................................................................................................................... 71
21. Register Tables .................................................................................................................. 72
21.1 Internal Control Registers ...................................................................................................................... 73
21.2 PCI Configuration Registers .................................................................................................................. 86
21.3 Register Modification Restrictions ......................................................................................................... 89
22. Pinout for 208 pin PQFP (sorted by number) ................................................................. 90
22.1 Package/Pin Drawing ............................................................................................................................ 92
23. DC Characteristics - PRELIMINARY/SUBJECT TO CHANGE ........................................ 93
23.1 Absolute Maximum Ratings ................................................................................................................... 93
23.2 Recommended Operating Conditions .................................................................................................... 93
23.3 DC Electrical Characteristics Over Operating Range ............................................................................ 93
23.4 Thermal Data ......................................................................................................................................... 94
24. AC Timing - PRELIMINARY/SUBJECT TO CHANGE....................................................... 95
25. Functional Waveforms ...................................................................................................... 98
25.1 PCI Read/Write Cycle ............................................................................................................................ 98
26. Packaging ......................................................................................................................... 100
27. Document History ............................................................................................................101
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