Document Outline

• Features
• Table of Contents
• List of Tables
• List of Figures
• 1. Overview
  • 1.1 CPU Bus Interface
  • 1.2 SDRAM and Device Interface
  • 1.3 PCI Interface
  • 1.4 DMA Engines
• 2. Pin Information
  • 2.1 Pin Assignment Table
  • 2.2 603e/860 Pins Multiplex Table
• 3. Address Space Decoding
  • 3.1 Two Stage Decoding Process
    • 3.1.1 CPU Side Decoding Process
  • 3.2 PCI Side Decoding Process
  • 3.3 Disabling the Device Decoders
  • 3.4 DMA Unit Address Decoding
  • 3.5 Address Space Decoding Errors
  • 3.6 Default Memory Map
  • 3.7 CPU and PCI Address Remapping
    • 3.7.1 CPU Address Remapping
    • 3.7.2 Writing to Decode Registers
    • 3.7.3 PCI Address Remapping
    • 3.7.4 Writing to Decode Registers
  • 3.8 CPU PCI Override
  • 3.9 DMA PCI Override
• 4. CPU Interface Description
  • 4.1 CPU Interface Signals
  • 4.2 PowerPC Address/Data Buses Multiplex
  • 4.3 A/DL,DH,DP Buses and Transaction Attributes
  • 4.4 QuickSwitch Configuration
  • 4.5 Glueless Configuration
  • 4.6 CPU Interface Write Buffer
  • 4.7 CPU Interface Read Buffer
  • 4.8 CPU Interface Endianess
  • 4.9 Parity Support
  • 4.10 Burst Order
  • 4.11 Address Only Transaction
  • 4.12 L2 Cache Support
  • 4.13 Multiple GT-64130 Support
    • 4.13.1 Hardware Connections
    • 4.13.2 Multi-GT Mode Enabled
    • 4.13.3 Initializing a Multiple GT-64130 System
    • 4.13.4 Multi-GT Restrictions
  • 4.14 Multi CPU Support
  • 4.15 AACK* Delay
  • 4.16 32-bit Bus Support
  • 4.17 PowerQUICC Support
    • 4.17.1 Bus Arbitration
    • 4.17.2 PowerQUICC Memory Controller
    • 4.17.3 PowerQUICC Transactions
  • 4.18 PowerQUICC II Support
  • 4.19 CPU Interface Restrictions
• 5. Memory Controller
  • 5.1 SDRAM Controller
    • 5.1.1 SDRAM Configuration Register (0x448)
      • 5.1.1.1 Refresh Rates
      • 5.1.1.2 Non-staggered and staggered Refresh
      • 5.1.1.3 Read Modify Write Enable/ECC
    • 5.1.2 Duplicating Signals
      • 5.1.2.1 Duplicating SDRAM Control Lines
      • 5.1.2.2 Duplicating DAdr[11] and BankSel[1] on DMAReq[2:1]*
      • 5.1.2.3 Duplicating DMA End of Transfer Pins
    • 5.1.3 SDRAM Operation Mode Register (0x474)
      • 5.1.3.1 Normal SDRAM Mode
      • 5.1.3.2 NOP Commands
      • 5.1.3.3 Precharge Both Bank
      • 5.1.3.4 Writing to the SDRAM�s Mode Register
      • 5.1.3.5 Force Refresh
    • 5.1.4 SDRAM Address Decode Register (0x47c)
  • 5.2 Connecting the Address Bus to the SDRAM
    • 5.2.1 16 MBit SDRAMs
    • 5.2.2 64/128 Mbit SDRAMs
  • 5.3 64/128 Mbit/64-bit SDRAM Connection to Memory Bus Using x8 Devices
  • 5.4 Programmable SDRAM Parameters
    • 5.4.0.1 SCAS* Latency
    • 5.4.0.2 Flow-through
    • 5.4.0.3 SRAS* Precharge
    • 5.4.0.4 64-bit Interleaving
    • 5.4.0.5 Bank Width
    • 5.4.0.6 Bank Location
    • 5.4.0.7 ECC Support
    • 5.4.0.8 64-bit Bypass Mode for CPU Reads
    • 5.4.0.9 SRAS* to SCAS*
    • 5.4.0.10 16/64/128 MBit SDRAM Configuration
    • 5.4.0.11 Burst Length
  • 5.5 SDRAM Performance
    • 5.5.1 CPU Access to SDRAM
    • 5.5.2 PCI Read Performance from SDRAM
  • 5.6 SDRAM Interleaving
  • 5.7 Unified Memory Architecture (UMA) Support
    • 5.7.1 UMA Hardware Support
    • 5.7.2 SDRAM Pins
    • 5.7.3 Address Decoding
    • 5.7.4 Arbitration
    • 5.7.5 Latencies, Low and High Priority
    • 5.7.6 Total Request
    • 5.7.7 Disable Refresh
  • 5.8 Device Controller
    • 5.8.1 TurnOff, bits [2:0]
    • 5.8.2 AccToFirst, bits [6:3]
    • 5.8.3 AccToNext, bits [10:7]
    • 5.8.4 ALEtoWr, bits[13:11]
    • 5.8.5 WrActive, bits[16:14]
    • 5.8.6 WrHigh, bits[19:17]
    • 5.8.7 Device Bank Width and Location
    • 5.8.8 Burst Writes
    • 5.8.9 Packing and Unpacking Data and Burst Support
    • 5.8.10 Ready* Support
    • 5.8.11 Parity Support for Devices
  • 5.9 Error Checking and Correcting (ECC)
    • 5.9.1 ECC Calculation
    • 5.9.2 ECC Error Report
  • 5.10 Programming the ADP lines for other Functions
  • 5.11 Memory Controller Restrictions
• 6. PCI Interfaces
  • 6.1 Reset Configuration
  • 6.2 PCI Master Operation
    • 6.2.1 PCI Master CPU Address Space Decode and Translation
    • 6.2.2 PCI Master CPU Byte Swapping
    • 6.2.3 PCI Master FIFOs
    • 6.2.4 PCI Master DMA
    • 6.2.5 PCI Master RETRY Counter
  • 6.3 PCI Target Interface
    • 6.3.1 PCI Target FIFOs
    • 6.3.2 Controlling Burst Length
    • 6.3.3 PCI Target Read Prefetching
    • 6.3.4 PCI Target Address Space Decode Process
    • 6.3.5 PCI Target Byte Swapping
    • 6.3.6 Tweaking the Performance of the Target Interface
  • 6.4 PCI Synchronization Barriers
  • 6.5 PCI Master Configuration
    • 6.5.1 Special Cycles and Interrupt Acknowledge
  • 6.6 Target Configuration and Plug and Play
    • 6.6.1 Plug and Play Base Address Register Sizing
    • 6.6.2 PCI Autoconfiguration at RESET
    • 6.6.3 Expansion ROM Functionality
  • 6.7 PCI Parity Support
  • 6.8 PCI Bus/Device Bus/CPU Clock Synchronization
  • 6.9 64-bit PCI Configuration
  • 6.10 Retry Enable
  • 6.11 Locked Cycles
  • 6.12 Hot-Plug Support
  • 6.13 PCI Interface Restrictions
    • 6.13.1 Master
    • 6.13.2 Slave
    • 6.13.3 Master and Slave
• 7. Intelligent I/O (I2O) Standard Support
  • 7.1 Overview
  • 7.2 I2O Registers
    • 7.2.1 I2O Register Map
  • 7.3 Enabling I2O Support
  • 7.4 Register Map Compatibility with the i960Rx Family
  • 7.5 Message Registers
    • 7.5.1 Inbound Messages
    • 7.5.2 Outbound Messages
  • 7.6 Doorbell Registers
    • 7.6.1 Inbound Doorbells
    • 7.6.2 Outbound Doorbells
  • 7.7 Circular Queues
    • 7.7.1 Inbound Message Queues
    • 7.7.2 Outbound Message Queues
    • 7.7.3 Circular Queue Data Storage
    • 7.7.4 Inbound/Outbound Queue Port Register Function
      • 7.7.4.1 Inbound Queue Port Reads and Writes
      • 7.7.4.2 The Outbound Queue Port
    • 7.7.5 Inbound Post Queue
    • 7.7.6 Inbound Free Queue
    • 7.7.7 Outbound Post Queue
    • 7.7.8 Outbound Free Queue
  • 7.8 Index Registers
• 8. DMA Controllers
  • 8.1 DMA Channel Registers
    • 8.1.1 Byte Count Register
    • 8.1.2 Source Address Register
    • 8.1.3 Destination Address Register
    • 8.1.4 Pointer to the Next Record Register
  • 8.2 DMA Channel Control Register (0x840 - 0x84c)
    • 8.2.1 FlyByEn bit
    • 8.2.2 R/W bit
    • 8.2.3 SrcDir, bits[3:2]
    • 8.2.4 DestDir, bits[5:4]
    • 8.2.5 DatTransLim, bits[8:6]
    • 8.2.6 ChainMod, bit 9
    • 8.2.7 IntMode, bit 10
    • 8.2.8 TransMod, bit 11
    • 8.2.9 ChanEn, bit 12
    • 8.2.10 FetNexRec, bit 13
    • 8.2.11 DMAActSt, bit 14 (Read Only)
    • 8.2.12 SDA, Source/Destination Alignment, bit 15
    • 8.2.13 Mask DMA Requests, MDREQ, bit 16
    • 8.2.14 Close Descriptor Enable, CDE, bit 17
    • 8.2.15 End Of Transfer Enable, EOTE, bit 18
    • 8.2.16 End Of Transfer Interrupt Enable, EOTIE, bit 19
    • 8.2.17 Abort DMA, ABR, bit 20
    • 8.2.18 SLP (bits [22:21]), DLP (bits [24:23]), RLP (bits [26:25])
  • 8.3 Restarting a Disabled Channel
  • 8.4 Reprogramming an Active Channel
  • 8.5 Arbitration
  • 8.6 Current Descriptor Pointer Registers
  • 8.7 Design Information
    • 8.7.1 DMA in Demand Mode
      • 8.7.1.1 Asserting and Deasserting DMAReq*
      • 8.7.1.2 Asserting DMAAck*
      • 8.7.1.3 DMAReq* Sampling
      • 8.7.1.4 Transferring Data Examples/recommendations
      • 8.7.1.5 DMA in Block Mode
    • 8.7.2 Non-Chain Mode
    • 8.7.3 Chain Mode
    • 8.7.4 Dynamic DMA chaining
    • 8.7.5 Fly-by DMA
      • 8.7.5.1 Background
      • 8.7.5.2 FlyBy in the GT-64130
      • 8.7.5.3 Programming the GT-64130 for FlyBy
      • 8.7.5.4 Design Considerations
      • 8.7.5.5 Determining CS During FlyBy
  • 8.8 Initiating a DMA From a Timer/Counter
  • 8.9 DMA Restrictions
    • 8.9.1 Fly-by Mode DMA Restrictions
• 9. Timer/Counters
• 10. Interrupt Controller
  • 10.1 Interrupt Cause Registers
  • 10.2 Interrupt Mask Registers
  • 10.3 Interrupt Summaries
  • 10.4 Interrupt Select Registers
• 11. Reset Configuration
• 12. Connecting the Memory Controller to SDRAM and Devices
  • 12.1 SDRAM
  • 12.2 Devices
• 13. JTAG Application Notes
• 14. Big and Little Endian
  • 14.1 Endian Background
    • 14.1.1 Bit 12 of the CPU Interface Configuration Register
    • 14.1.2 Bits 0 and 16 of the PCI Internal Command Register
    • 14.1.3 Bits 10-12 of the PCI Internal Command Register
  • 14.2 Configuring a System for Big and Little Endian
• 15. Using the GT-64130 Without the CPU Interface
• 16. Using the GT�64130 in Different PCI Configurations
• 17. Using the GT-64130 in MPC860 Configuration
• 18. System Configurations
  • 18.1 Minimal System Configuration
  • 18.2 Typical System
  • 18.3 High Performance System
• 19. Register Tables
  • 19.1 Access to On-Chip PCI Configuration Space Registers
  • 19.2 Register Map
  • 19.3 CPU Configuration
  • 19.4 CPU Address Decode
  • 19.5 CPU Sync Barrier
  • 19.6 SDRAM and Device Address Decode
  • 19.7 SDRAM Configuration
  • 19.8 SDRAM Parameters
  • 19.9 ECC
  • 19.10 Device Parameters
  • 19.11 DMA Record
  • 19.12 DMA Channel Control
  • 19.13 DMA Arbiter
  • 19.14 Timer/Counter
  • 19.15 PCI Internal
  • 19.16 Interrupts
    • 19.16.1 Interrupt MASK Registers
  • 19.17 PCI Configuration
    • 19.17.1 Function 1 Configuration Registers
  • 19.18 I2O Support Registers
• 20. GT-64130 Pinout Table, 388 pin BGA
• 21. DC Characteristics
  • 21.1 DC Electrical Characteristics Over Operating Range
  • 21.2 Thermal Data
• 22. AC Timing
  • 22.1 TClk/PClk Restrictions
  • 22.2 Additional Delay Due to Capactive Loading
    • 22.2.1 Calculating the Maximum Delay Due to Loading
      • 22.2.1.1 Calculating Atypa
    • 22.2.2 Calculating the Minimum Delay Due to Loading
      • 22.2.2.1 Calculating Atypb
    • 22.2.3 Btyp Values
    • 22.2.4 Example Calculation of Tmax
• 23. 388 PBGA Package Mechanical Information
• 24. GT�64130 Part Numbering
  • 24.1 Standard Part Number
  • 24.2 Valid Part Numbers
• 25. Revision History