1 (7)
DA9187.001
29 May, 2002
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
O8
8-BIT DAC
O7
O6
O5
O4
O3
O2
O1
VREFHVREFL
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
O12
O11
O10
O9
CLK
SDI
XCS
VDD
GND
12-bit
Shift
Register
Address
Decoder
8-bit data
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MAS9187 is 12-channel 8-bit DAC, designed
primarily for trimmer replacement. Device is
controlled by a simple 3-line input. The output
buffers operate in the entire voltage range from
ground to the positive power supply rail.
DAC is selected with four first bits in serial input data
(SDI-pin) and the DAC output value is set according
to the last 8 bits in serial input data.
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Twelve 8-bit DACs on a single monolithic chip
Voltage level output
TSSOP 20 package
Single, low +1.8 V supply
Power-on
reset
High resolution monitors
Automatic gain control
Trimmer
replacement
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29 May, 2002
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1
VREFH
VREFH
DAC output reference high voltage
2
O1
O1
DAC 1, address 0x0
3
O2
O2
DAC 2, address 0x1
4
O3
O3
DAC 3, address 0x2
5
O4
O4
DAC 4, address 0x3
6
O5
O5
DAC 5, address 0x4
7
O6
O6
DAC 6, address 0x5
8
XSHDN
XSHDN
Device analog part power-down signal (active low)
9
XCS
XCS
Device enable signal (rising edge loads data to DAC)
10
GND
GND
Device ground-pin
11
CLK
VREFL
Data clock / DAC output low reference voltage
12
SDI
CLK
Serial input data / Data clock
13
O7
SDI
DAC 7, address 0x6 / Serial input data
14
O8
O7
DAC 8, address 0x7 / DAC 7, address 0x6
15
O9
O8
DAC 9, address 0x8 / DAC 8, address 0x7
16
O10
O9
DAC 10, address 0x9 / DAC 9, address 0x8
17
O11
O10
DAC 11, address 0xA / DAC 10, address 0x9
18
O12
O11
DAC 12, address 0xB / DAC 11, address 0xA
19
XRESET
O12
Device Digital part reset middle code preset pin/DAC 12,
address 0xB
20
VDD
VDD
Device power supply pin
MAS9187 has two bonding options available:
MAS9187A1, where VREFL pin is bonded to GND pin and XRESET pin can be used
MAS9187A2, where XRESET pin is bonded to VDD pin and VREFL pin can be used
VREFH
VREFH
O1
O2
O3
O4
O5
O6
XSHDN
XCS
GND
O1
O2
O3
O4
O5
O6
XSHDN
XCS
GND
M
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9
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8
7
A
2
VDD
XRESET
O12
O11
O10
O9
O8
O7
SDI
CLK
VDD
VREFL
O12
O11
O10
O9
O8
O7
SDI
CLK
Top view
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Y
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Y
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29 May, 2002
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Power Supply (VDD to GND)
VDD
-0.3
+6.0
V
Input Voltage Range (any other pin)
-0.3
VDD + 0.3
V
Continuous Power Dissipation
1000
mW
Storage Temperature Range
-65
+150
C
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Supply Voltage Range
VDD
2.7
3.6
5.5
V
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Operating Temperature
Range
Temp
-40
+85
C
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: MAS9187Axx3 and MAS9187Axx4 minimum supply voltage 1.8 V
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(VDD = 3.0 V
10% or 5.0 V
10%, VREFH = VDD, VREFL = 0V, -40
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+85
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DAC Resolution
N
8
Bits
DAC Differential Nonlinearity Error
DNL
-1
+1
LSB
DAC Integral Nonlinearity Error
INL
-1
+1
LSB
DAC Full-scale Error
GFSE
-1
+1
LSB
DAC Zero Code Error
BZSE
-1
+1
LSB
DAC Output Resistance
ROUT
30
60
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REFH Voltage Range
VREFH
V
REFH
> V
REFL
0
VDD
REFL Voltage Range (MAS9187A2 only)
VREFL
V
REFH
> V
REFL
0
VDD
REFH Input Resistance
RREFH
5
10
k
REFL Input Resistance
RREFL
10
k
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DA9187.001
29 May, 2002
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Digital Logic High
VIH
0.7*VDD
Digital Logic Low
VIL
0.3*VDD
Digital Input Current
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Power Supply Range
VDD
2.7
5.5
V
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Supply Current
IDD
VDD = 3.60V
3
6
mA
Supply Current
IDD
VDD = 5.50V
20
mA
Shutdown Current
ISHDN
0.5
5
uA
1RWH
: MAS9187Axx3 and MAS9187Axx4 minimum supply voltage 1.8 V
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Power Supply Sensitivity (100Hz)
PSRR
54
dB
Vout Settling time (
1/2 LSB error band)
TS
6
s
Crosstalk between adjacent outputs
CT
63
dB
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(Minimum values at +25
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Input Clock High Pulse Width
TCH
16
ns
Input Clock Low Pulse Width
TCL
7
ns
Data Setup Time
TDS
-5
ns
Data Hold Time
TDH
5
ns
XCS Fall to First Clock Pulse Fall
TCLCL
16
ns
XCS High Pulse Width
TCSW
22
ns
RESET Pulse Width
TRS
28
ns
CLK Rise to XCS Rise Hold Time
TCSH
22
ns
XCS Rise to CLOCK Rise Setup
TCS1
-5
ns
5 (7)
DA9187.001
29 May, 2002
23(5$7,1* 02'(6
DAC maximum output voltage is set using VREFH and VREFL pins (= 255/256 * (VREFH-VREFL)+VREFL)
(note: VREFL=GND in case of MAS9187A1). XRESET pin is used for middle code preset: DAC registers are
reset and middle code will appear at the DAC output.
Serial input data is written to SDI while XCS is low. Data is read at CLK rising edge to on-chip shift register.
Rising XCS-pin stops data reading and 12 CLK-cycles are used as the input data (4 address bits and 8 data bits).
The last 12 bits before rising XCS are used as input data.
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Clock
Data In
MAS9187A2
O8
O1
O2
O3
O4
O5
O6
O7
15
14
7
6
5
4
3
2
VREFH
VREFL
CLK
SDI
12
13
Controller
O12
O9
O10
O11
19
18
17
16
VDD
GND
+3.0v
11
10
1
20
XCS
Latch
9
8
XSHDN
100 nF
SDI
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CLK
XCS
DAC Register Load
V
OUT
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