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091399
FEATURES
Dual Fixed frequency outputs (30 kHz - 100 MHz)
No external components
0.5% Initial tolerance
1% variation over temperature and voltage
Single 5V supply
Power-down mode
Synchronous output gating
DESCRIPTION
The DS1075 Custom is a fixed frequency oscillator requiring no external components for operation.
Numerous operating frequencies are possible in the range 29.2 kHz to 100 MHz through the use of an on-
chip factory-programmable prescaler and divider.
The DS1075 Custom is shipped from the factory pre-programmed on a custom basis to the customers
specified output frequency and mode of operation. The part is branded according to the device's master
frequency (see DS1075 data sheet). The customer fills out a "1075 Custom Order Form" with the
required information and submits it to the factory for approval.
Custom EconOscillators are available in two versions, Simple Custom and Complex Custom, that can be
programmed at the factory in sample and volume quantities.
Simple Custom parts are based on one of the standard master frequencies of 60, 66, 80 and 100 MHz with
non-standard values programmed for the dividers and function select bits. An impressive number (over
1500) of sub-frequencies can be programmed using a Simple Custom part.
Complex Custom parts have a non-standard Master frequency (within the 60 MHz to 110 MHz range)
programmed into the internal master oscillator and non-standard values are programmed for the dividers
and function select bits. Virtually any frequency within the 29.24 kHz to 110 MHz range is possible
using complex custom parts Contact the factory for Custom Part selection and ordering information.
The DS1075 Custom is available in 8-pin DIP or SOIC packages, allowing the generation of a clock
signal easily, economically and using minimal board area.
DS1075 Custom
EconOscillator/Divider
PRELIMINARY
www.dalsemi.com
DS1075Z 150-MIL SOIC
DS1075M 300-MIL DIP
OUT1
OUT0
V
CC
GND
NC
NC
OE
PDN
1
2
3
8
7
6
5
4
DS1075
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BLOCK DIAGRAM Figure 1
Master
Oscillator
60-110MHz
Power
Down
Control
Divider
Divide by N
1-513
Prescaler
Divide by M
1, 2, 4
OUT0
(Optional)
(Reference)
OUT1
OE
PDN
DS1075
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1075 Custom Order Form
Use this form for DS1075 Custom programmed EconOscillators . All sections must be completed.
Refer to the datasheet or contact Bob Brown at (972) 371-3719 for assistance.
Parent Part Number:
DS1075
Customer Name: _______________________________________________________________
Customer Contact: _____________________________________________________________
Customer Address: _____________________________________________________________
_____________________________________________________________________________
Customer Phone: (Area) _____ _____ ________
Salesman: ____________________________________________________________________
Sales Representative: ___________________________________________________________
Distributor (if any): ____________________________________________________________
Package: 300mil 8-pin DIP 150mil 8-pin SOIC (circle one)
Parent Device: DS ________________ ( part will be branded with this speed)
Master Frequency: _________ MHz Standard or Custom (circle one)
(60,66,80 or 100MHz)
Reference Output: Disabled
Enabled - Frequency _________
(Equals master frequency/M)
Output Frequency: _________ (Equals master frequency/MN)
Prescaler (M) : _________
Divider (N): _________
Special Instructions (Tape & Reel, etc.):
_____________________________________________________________________________
_____________________________________________________________________________
_____________________________________________________________________________
_____________________________________________________________________________
_____________________________________________________________________________
Customer Signature: _____________________________________
(acknowledges acceptance of custom settings)
Fax the completed form to Bob Brown at (972) 371-3717
DS1075
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PIN DESCRIPTIONS
Output Pin (OUT1 pin):
This pin is the main oscillator output, with a frequency determined by clock
reference, M and N dividers.
Output Enable Function (OE pin): The DS1075 Custom features a "synchronous" output enable.
When OE is at a high logic level the oscillator free runs. When this pin is taken low OUT/ is held low,
immediately if OUT/ is already low, or at the next high-to-low transition if OUT/ is high. This prevents
any possible truncation of the output pulse width when the enable is used. While the output is disabled
the master oscillator continues to run (producing an output at OUT0, if the
EN0 bit = 0) but the internal
counters (/N) are reset. This results in a constant phase relationship between OE's return to a high level
and the resulting OUT/ signal. When the enable is released OUT/ will make its first transition within one
to two clock periods of the master clock.
Power-Down (
PDN
pin): A low logic level on this pin can be used to make the device stop oscillating
(active low) and go into a reduced power consumption state. Internal "Enabling Sequencer" circuitry
will first disable OUT in the same way as when OE is used. Next OUT0 will be disabled in a similar
fashion. Finally the oscillator circuitry will be disabled. In this mode both outputs will go into a high
impedance state. The power consumption in the power-down state is much less than if OE is used
because the internal oscillator is completely powered down. Consequently the device will take
considerably longer to recover (i.e., achieve stable oscillation) from a power-down condition than if the
OE is used.
Reference Output (OUT0 pin): A reference output, OUT0, is also available from the output of the
prescaler. OUT0 is unaffected by the OE pin, but is disabled in a glitchless fashion if the device is
powered down. If this output is not required it can be permanently disabled and there will be a
corresponding reduction in overall power consumption. The availability of this output and its frequency
are specified on the custom order form.
OPERATION OF OUTPUT ENABLE
Since the output enable and internal master oscillator are asynchronous there is the possibility of timing
difficulties in the application. To minimize these difficulties the DS1075 features an "enabling
sequencer" to produce predictable results when the device is enabled and disabled. In particular the
output gating is configured so that truncated output pulses can never be produced.
ENABLE TIMING
The output enable function is produced by sampling the OE input with the output from the pre-scaler mux
(MCLK) and gating this with the output from the programmable divider. The exact behavior of the
device is therefore dependent on the setup time (t
SU
) from a transition on the OE input to the rising edge
of MCLK. If the actual setup time is less than t
SUEM
then one more complete cycle of MCLK will be
required to complete the enable or disable operation (see diagrams). This is unlikely to be of any
consequence in most applications, and then only if the value for N is small. In general, the output will
make its first positive transition between approximately one and two clock periods of MCLK after the
rising edge of OE. (Figure 2)
DS1075
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Figure 2
Disable Timing
If OE goes low while OUT1 is high, the output will be disabled on the completion of the output pulse. If
OUT1 is low, the disabling behavior will be dependent on the setup time between the falling edge of OE
and the rising edge of MCLK. If t
SU
< t
SUEM
the result will be one additional pulse appearing on the
output before disabling occurs.
If the device is in divide-by-one mode, the disabling occurs slightly differently. In this case if t
S
> t
SUEM
one additional output pulse will appear, if t
SU
<
t
SUEM
then two additional output pulses will appear. The
following diagrams illustrate the timing in each of these cases. (Figure 3 and 4)
Figure 3
Figure 4
DS1075
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POWER-DOWN CONTROL
POWER-DOWN
If
PDN is taken low a power-down sequence is initiated. The "Enabling Sequencer" is used to execute
events in the following sequence:
1.
Disable OUT1 (same sequence as when OE is used) and reset N counters.
2.
When OUT1 is low, switch OUT1 to high-impedance state.
3.
Disable MCLK, switch OUT0 to high impedance state.
4.
Disable master oscillator.
POWER-UP
When
PDN is taken to a high level the following power-up sequence occurs:
1.
Enable internal oscillator.
2.
Set M and N to maximum values.
3.
Wait approximately 256 cycles of MCLK for it to stabilize.
4.
Reset M and N to programmed values.
5. Enable OUT0 ( if enabled)
6. Enable OUT1.
Steps 2 through 4 exist to allow the oscillator to stabilize before enabling the outputs.
Figure 5
DS1075
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POWER-ON RESET
When power is initially applied to the device supply pin, a power-on reset sequence is executed, similar
to that which occurs when the device is restored from a power-down condition. This sequence comprises
two stages, first a conventional POR to initialize all on-chip circuitry, followed by a stabilization period
to allow the oscillator to reach a stable frequency before enabling the outputs:
1.
Initialize internal circuitry.
2.
Enable internal oscillator.
3.
Set M and N to maximum values.
4.
Wait approximately 256 cycles of MCLK for the oscillator to stabilize.
5.
Load M and N programmed values from EEPROM.
6.
Enable OUT0 (if enabled).
7.
Enable OUT1.
Figure 6
DS1075
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
-1.0V to +7.0V
Operating Temperature
0C to 70C
Storage Temperature
-55C to +125C
Soldering Temperature
260C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS (T
A
=0C to 70C; V
CC
= 5V 5%)
PARAMETER
SYMBOL
CONDITION
MIN
TYP MAX UNITS NOTES
Supply Voltage
V
CC
4.75
5
5.25
V
High-level Output
Voltage
(OUT1, OUT0)
V
OH
I
OH
=-4 mA,
V
CC
= MIN
2.4
V
Low-level Output
Voltage (OUT1, OUT0)
V
OL
I
OL
=4 mA
0.4
V
High-level Input Voltage
(
PDN
,
OE)
V
IH
V
IH
2
3
V
V
Low-level Input Voltage
(
PDN
,
OE)
V
IL
V
IL
0.8
2
V
V
High-level Input Current
(
PDN
,
OE)
I
IH
I
IH
V
IH
=2.4V,
V
CC
=5.25V
V
IH
=V
CC
=5.25V
1
25
A
A
Low-level Input Current
(
PDN , OE)
I
IL
I
IL
V
IL
=0,
V
CC
=5.25V
V
IL
=0,V
CC
=
5.25V
-1
-25
A
A
Supply Current (Active)
DS1075-100
DS1075-80
DS1075-66
DS1075-60
I
CC
C
L
=15pF
(both outputs)
V
CC
=5.25V
50
mA
Standby Current
I
CCQ
Power-Down
Mode
0.8
A
DS1075
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AC ELECTRICAL CHARACTERISTICS
(T
A
=0C to 70C; V
CC
= 5V 5%)
PARAMETER
SYMBOL
CONDITION
MIN
TYP MAX UNITS NOTES
Output Frequency
Tolerance
? f
O
V
CC
=5V, T
A
=25C
-0.5
0
+0.5
%
Combined Freq.
Variation
? f
O
Over temp and
voltage
-1
+1
%
Long Term Stability
? f
O
-0.5
+0.5
%
Minimum Output
Frequency
f
OUT
Master = 60MHz
M=4, N-513
29.24
KHz
Power-up Time
t
por
+t
stab
0.1
1
ms
1, 2
Enable OUT1 from
PDN
t
stab
0.1
1
ms
2
Enable OUT0 from
PDN
t
stab
0.1
1
ms
2, 3
OUT1 Hi-Z from
PDN
t
pdn
1
ms
OUT0 Hi-Z from
PDN
t
pdn
1
ms
Load Capacitance
(OUT1, OUT0)
C
L
15
pF
4
Output Duty Cycle
OUT1
OUT0
40
60
%
NOTES:
1.
This is the time from when V
CC
is applied until the output starts oscillating
2.
When the device is initially powered up, or restored from the power-down mode, OE should be
asserted (high).Otherwise the start of the t
stab
interval will be delayed until OE goes high. OE can
subsequently be returned to a low level during the t
stab
interval to force out low after the t
stab
interval.
3.
Although OE does not normally affect OUT0 operation, if OE is held low during power-up the start
of the t
stab
period will be delayed until OE is asserted. If OE remains low, OUT0 will not start.
4.
Operation with higher capacitive loads is possible but may impair output voltage swing and maximum
operation frequency.
DS1075
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AC ELECTRICAL CHARACTERISTICS-CALCULATED PARAMETERS
The following characteristics are derived from various device operating parameters (frequency, mode
etc.). They are not specifically tested or guaranteed and may differ from the min and max limits shown
by a small amount due to internal device setup times and propagation delays. However, these equations
can be used to derive a more accurate idea of typical device performance than the guaranteed values.
PARAMETER
SYMBOL
CONDITION
MIN
MAX
OUT1
from OE
t
en
t
M
2t
M
OUT1
from OE
N =1
N = 2
t
dis
t
dis
t
OUTH
0
t
OUTH +
t
M
t
OUTH
PDN
to OUT1 Hi-Z
N =1 N = 2
t
pdn
t
pdn
t
OUTH
0
t
OUTH +
t
M
t
OUTH
PDN
to OUT0 Hi-Z
N =1
N = 2
t
pdn
t
pdn
t
OUTH
0
t
OUTH +
t
M
t
OUTH
PDN
to OUT1
t
stab
256t
M
PDN
to OUT0
t
stab
256t
M
OUT1
after Power-up
256t
M
OUT0
after Power-up
256t
M
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