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100199
FEATURES
Dual Fixed frequency outputs (30 kHz - 100
MHz)
User-programmable on-chip dividers (from 1
- 513)
User-programmable on-chip prescaler (1, 2,
4)
No external components
0.5% initial tolerance
3% variation over temperature and voltage
Internal clock, external clock or crystal
reference options
Single 5V supply
Power-down mode
Synchronous output gating
PIN ASSIGNMENT
FREQUENCY OPTIONS
Part No.
Max O/P freq.
DS1075-100 IND
100.000
DS1075-80 IND
80.000
DS1075-66 IND
66.667
DS1075-60 IND
60.000
DESCRIPTION
The DS1075-IND EconOscillator/Divider is a fixed frequency oscillator requiring no external
components for operation. Numerous operating frequencies are possible in the range of approximately
30kHz to 100 MHz through the use of an on-chip programmable prescaler and divider.
The DS1075-IND features a master oscillator followed by a prescaler and then a programmable divider.
The prescaler and programmable divider are user-programmable with the desired values being stored in
non-volatile memory. This allows the user to buy an off the shelf component and program it on-site prior
to board production. Design changes can be accommodated on the fly by simply programming different
values into the device (or reprogramming previously programmed devices).
The DS1075-IND is shipped from the factory configured for half the maximum operating frequency.
Contact the factory for specially programmed devices. As alternatives to the on-board oscillator an
external clock signal or a crystal may be used as a reference. The choice of reference source (internal or
external) is user-selectable at the time of programming (or on the fly if the SEL mode is chosen).
The DS1075-IND features a dual-purpose Input/Output pin. If the device is powered up in Program
mode this pin can be used to input serial data to the on chip registers. After a Write command this data is
stored in non-volatile memory. When the chip is subsequently powered up in operating mode these
values are automatically restored to the on-chip registers and the Input/ Output pin becomes the oscillator
output.
The DS1075-IND is available in 8-pin DIP or SOIC packages, allowing the generation of a clock signal
easily, economically and using minimal board area.
DS1075-IND
EconOscillator/Divider
www.dalsemi.com
I/O
OUT0
V
CC
GND
OSCIN
2
3
4
8
7
6
5
1
DS1075Z 150-mil SOIC
DS1075M-IND 300-mil DIP
XTAL
OE
PDN/SELX
DS1075-IND
2 of 17
BLOCK DIAGRAM Figure 1
PART
NO.
SUFFIX
INTOSC
FREQUENCY
-100
080
-66
-60
100.000 MHz
80.000 MHz
66.667 MHz
60.000 MHz
DS1075-IND
3 of 17
PIN DESCRIPTIONS
Input/Output Pin (IN/OUT):
This pin is the main oscillator output, with a frequency determined by
clock reference, M and N dividers. Except in programming mode this pin is always an output and will be
referred to as "OUT." In programming mode this pin will be referred to as "IN."
External Oscillator Input (OSCIN): This pin can be
used to supply an external reference frequency to
the device.
Crystal Oscillator Connection (XTAL): A crystal can
be connected between this pin and OSCIN to
provide an alternative frequency reference. The crystal must be operated in fundamental mode. If a
crystal is not used this pin should be left open.
Output Enable Function (OE pin): The DS1075-IND
also features a "synchronous" output enable.
When OE is at a high logic level the oscillator free runs. When this pin is taken low OUT is held low,
immediately if OUT is already low, or at its next high-to-low transition if OUT is high. This prevents any
possible truncation of the output pulse width when the enable is used. While the output is disabled the
master oscillator continues to run (producing an output at OUT0, if the
EN0
bit = 0) but the internal
counters (/N) are reset. This results in a constant phase relationship between OE's return to a high level
and the resulting OUT signal. When the enable is released OUT will make its first transition within one
to two clock periods of the master clock.
Power-Down/Select Function (
PDN
/
SELX
pin): The
Power-Down/Select (
PDN
/
SELX
) pin has a user-
selectable function determined by one bit (PDN bit) of the user-programmable memory. According to
which function is selected, this pin will be referred to as
PDN
or
SELX
.
If the Power-Down function is selected (PDN bit = 1) a low logic level on this pin can be used to make
the device stop oscillating (active low) and go into a reduced power consumption state. The "Enabling
Sequencer" circuitry will first disable OUT in the same way as when OE is used. Next OUT0 will be
disabled in a similar fashion. Finally the oscillator circuitry will be disabled. In this mode both outputs
will go into a high impedance state. The power consumption in the power-down state is much less than if
OE is used because the internal oscillator (if used) is completely powered down. Even if an external
reference or a crystal is used all of the on-chip buffers are powered down to minimize current drain.
Consequently the device will take considerably longer to recover (i.e., achieve stable oscillation) from a
power-down condition than if the OE is used.
If the Select function is chosen (PDN bit = 0) this pin can be used to switch between the internal
oscillator and an external reference (or crystal) on the fly. When this mode is chosen the E/
I
select bit is
overridden, a high logic level on
SELX
will select the internal oscillator, a low logic level will select the
external reference (or crystal oscillator).
Reference Output (OUT0 pin): A reference output,
OUT0, is also available from the output of the
reference select mux. This output is especially useful as a buffered output of a crystal defined master
frequency. OUT0 is unaffected by the OE pin, but is disabled in a glitchless fashion if the device is
powered down. If this output is not required it can be permanently disabled by setting the
EN0
bit to one,
and there will be a corresponding reduction in overall power consumption.
USER-PROGRAMMABLE REGISTERS
The following registers can be programmed by the user to determine operating frequency and mode of
operation. Details of how these registers are programmed can be found in a later section; in this section
DS1075-IND
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the function of the registers are described. The register settings are nonvolatile, the values being stored
automatically in EEPROM when the registers are programmed.
Note: The register bits cannot be used to make mode or frequency changes on the fly. Changes can only
be made by powering the device up in "Programming" mode. For them to be become effective the device
must then be powered down and powered up again in "Operation" mode.
For programming purposes the register bits are divided into two 9-bit words. The "MUX" word
determines mode of operation and prescaler values. The "DIV" word sets the value of the programmable
divider.
MUX WORD Figure 2
(MSB)
(LSB)
0*
0*
0*
EN0
PDN
M
MSEL
DIV1
E/
I
*
These bits must be set to 0
E/
I
This bit selects either the internal oscillator or the external/ crystal reference.
1=External/Crystal
0=Internal Oscillator
However, if the PDN bit is set to 0 the E/
I
bit will be overridden by the logic level on the
PDN
/
SELX
pin.
Table 1
PDN
BIT
E/
I
PDN
/
SELX
PIN
OSCILLATOR
MODE
0
X
0
EXTERNAL/CRYSTAL
0
X
1
INTERNAL
1
X
0
POWER-DOWN
1
0
1
INTERNAL
1
1
1
EXTERNAL/CRYSTAL
DIV1
This bit allows the master clock to be routed directly to the output (DIV1=1). The N programmable
divider is bypassed so the programmed value of N is ignored. The frequency of the output (f
OUT
) will be
INTCLK or EXTCLK depending on which reference has been selected. If the internal clock is selected
the M prescaler is also bypassed (the bit values of MSEL and M are ignored), so in this case
f
OUT
=INTOSC (which also equals MCLK and INTCLK). If DIV1=0 the prescaler and programmable
divider function normally.
MSEL
This bit determines whether or not the M prescaler is bypassed.
MSEL
=1 will bypass the prescaler.
MSEL
=0 will switch in the prescaler (unless overridden by DIV1=1), with a divide-by number
determined by the M bit.
M
This bit sets the divide-by number for the prescaler. M=0 results in divide-by-4, M=1 results in divide-
by-2. The setting of this bit is irrelevant if either DIV1=1 or
MSEL
=1.
DS1075-IND
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Table 2
DIV1
BIT
E/
I
BIT*
MSEL
BIT
M
BIT
OPERATION
0
0
0
0
INTERNAL OSCILLATOR DIVIDED BY 4*N
0
0
0
1
INTERNAL OSCILLATOR DIVIDED BY 2*N
0
0
1
X
INTERNAL OSCILLATOR DIVIDED BY N
0
1
X
X
EXTERNAL OSCILLATOR DIVIDED BY N
1
0
X
X
INTERNAL OSCILLATOR DIVIDED BY 1
1
1
X
X
EXTERNAL OSCILLATOR DIVIDED BY 1
*Assuming PDN bit = 1, otherwise internal/external selection will be controlled by the
PDN
/
SELX
pin.
DIV WORD
Figure 3
(MSB)
(LSB)
N (9 BITS)
PDN
This bit is used to determine the function of the
PDN
/
SELX
pin. If PDN=0, the
PDN
/
SELX
pin can be
used to determine the timing reference (either the internal oscillator or an external reference/crystal). If
PDN=1, the
PDN
/
SELX
pin is used to put the device into power-down mode.
EN0
This bit is used to determine whether the OUT0 pin is active or not. If
EN0
=1, OUT0 is disabled (High-
impedance). If
EN0
=0, the internal reference clock (MCLK) is output from OUT0. The OE pin has no
effect on OUT0, but OUT0 is disabled as part of the power-down sequence.
N
These 9 bits determine the value of the programmable divider. The range of divisor values is from 2 to
513, and is equal to the programmed value of N plus 2:
Table 3
BIT
VALUES
DIVISOR (N)
VALUE
000000000
2
000000001
3
.
.
.
.
.
.
.
.
.
.
111111111
513
NOTE:
INTOSC/(M*N) must be greater than f
OUTmin
; if the external clock is selected, EXTCLK/N must be
greater than f
OUTmin
. (If DIV1=1, then INTOSC or EXTCLK, as applicable, must exceed f
OUTmin
).
DS1075-IND
6 of 17
OPERATION OF OUTPUT ENABLE
Since the output enable, internal master oscillator and/or external master oscillator are likely all
asynchronous there is the possibility of timing difficulties in the application. To minimize these
difficulties the DS1075-IND features an "enabling sequencer" to produce predictable results when the
device is enabled and disabled. In particular the output gating is configured so that truncated output
pulses can never be produced.
ENABLE TIMING
The output enable function is produced by sampling the OE input with the output from the prescaler mux
(MCLK) and gating this with the output from the programmable divider. The exact behavior of the
device is therefore dependent on the setup time (t
SU
) from a transition on the OE input to the rising edge
of MCLK. If the actual setup time is less than t
SUEM
then one more complete cycle of MCLK will be
required to complete the enable or disable operation (see diagrams). This is unlikely to be of any
consequence in most applications, and then only if the value for N is small. In general, the output will
make its first positive transition between approximately one and two clock periods of MCLK after the
rising edge of OE.
FIGURE 4
DISABLE TIMING
If OE goes low while OUT is high, the output will be disabled on the completion of the output pulse. If
OUT is low, the disabling behavior will be dependent on the setup time between the falling edge of OE
and the rising edge of MCLK. If t
SU
< t
SUEM
the result will be one additional pulse appearing on the
output before disabling occurs.
If the device is in divide-by-1 mode, the disabling occurs slightly differently. In this case if t
SU
> t
SUEM
one additional output pulse will appear, if t
SU
< t
SUEM
then two additional output pulses will appear.
The following diagrams illustrate the timing in each of these cases.
DS1075-IND
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Figure 5
SELECT TIMING
If the PDN bit is set to 0, the
PDN
/
SELX
pin can be used to switch between the internal oscillator and an
externalor crystal reference. The "Enabling Sequencer" is again employed to ensure this transition occurs
in a glitch-free fashion. Two asynchronous clock signals are involved, INTCLK is the internal reference
oscillator divided by one or whatever value of M is selected. EXTCLK is the clock signal fed into the
OSCIN pin, or the clock resulting from a crystal connected between OSCIN and XTAL. The behavior of
OUT0 is described in the following paragraphs, the OUT pin will behavior similarly but will be divided
by N.
FROM INTERNAL TO EXTERNAL CLOCK
This is accomplished by a high to low transition on the
SELX
pin. This transition is detected on the
falling edge of INTCLK. The output OUT0 will be held low for a minimum of half the period of
INTCLK (t
I
/2), then if EXTCLK is low it will be routed through to OUT0. If EXTCLK is high the
switching will not occur until EXTCLK returns to a low level.
Figure 6
DS1075-IND
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Figure 7
Depending on the relative timing of the
SELX
signal and the internal clock, there may be up to one full
cycle of t
I
on the output after the falling edge of
SELX
. Then, the "low" time (t
LOW
) between output
pulses will be dependent on the relative timing between t
I
and t
E
. The time interval between the falling
edge of
SELX
and the first rising edge of the externally derived clock is t
SIE
. Approximate maximum and
minimum values of these parameters are:
t
LOW
(min) = t
I
/2
t
LOW
(max) = t
I
/2 + t
E
t
SIE
(min) = t
I
/2
t
SIE
(max) = 3t
I
/2 + t
E
NOTE:
In each case there will be a small additional delay due to internal propagation delays.
FROM EXTERNAL TO INTERNAL CLOCK
This is accomplished by a low to high transition on the
SELX
pin. In this case the switch is level
triggered, to allow for the possibility of a clock signal not being present at OSCIN. Note therefore, that if
a constant high-level signal is applied to OSCIN it will not be possible to switch over to the internal
reference. (Level triggering was not employed for the switch from internal to external reference as this
approach is slower and the internal clock may be running at a much higher frequency than the maximum
allowed external clock rate.) When
SELX
is high and a low level is sensed on EXTCLK, OUT0 will be
held low until a falling edge occurs on INTCLK, then the next rising edge of INTCLK will be routed
through to OUT0.
Figure 8
Depending on the relative timing of the
SELX
signal and the external clock, there may be up to one full
t
Ehigh
period on the output after the rising edge of
SELX
. Then, the "low" time (t
LOW
) between output
pulses will be dependent on the relative timing between t
I
and t
E
. The time interval between the falling
DS1075-IND
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edge of
SELX
and the first rising edge of the externally derived clock is t
SIE
. Approximate maximum and
minimum values of these parameters are:
t
LOW
(min) = t
I
/2
t
LOW
(max) = 3t
I
/2 + t
Elow
t
SIE
(min) = t
I
/2
t
SIE
(max) = 3t
I
/2 + t
Ehigh
NOTE:
In each case there will be a small additional delay due to internal propagation delays.
POWER-DOWN CONTROL
If the PDN bit is set to 1, the
PDN
/
SELX
pin can be used to power-down the device. If
PDN
is high the
device will run normally.
POWER-DOWN
If
PDN
is taken low a power-down sequence is initiated. The "Enabling Sequencer" is used to execute
events in the following sequence:
1.
Disable OUT (same sequence as when OE is used) and reset N counters.
2.
When OUT is low, switch OUT to high-impedance state.
3.
Disable MCLK (and OUT0 if
EN0
bit = 0), switch OUT0 to high impedance state.
4.
Disable internal oscillator and OSCIN buffer.
POWER-UP
When
PDN
is taken to a high level the following power-up sequence occurs:
1.
Enable internal oscillator and/or OSCIN buffer.
2.
Set M and N to maximum values.
3.
Wait approximately 256 cycles of MCLK for it to stabilize.
4.
Reset M and N to programmed values.
5.
Enable OUT0 (assuming
EN0
bit = 0).
6.
Enable OUT.
Steps 2 through 4 exist to allow the oscillator to stabilize before enabling the outputs.
DS1075-IND
10 of 17
Figure 9
POWER-ON RESET
When power is initially applied to the device supply pin, a power-on reset sequence is executed, similar
to that which occurs when the device is restored from a power-down condition. This sequence comprises
two stages, first a conventional POR to initialize all on-chip circuitry, followed by a stabilization period
to allow the oscillator to reach a stable frequency before enabling the outputs:
1.
Initialize internal circuitry.
2.
Enable internal oscillator and/or OSCIN buffer.
3.
Set M and N to maximum values.
4.
Wait approximately 256 cycles of MCLK for the oscillator to stabilize.
5.
Load M and N programmed values from EEPROM.
6.
Enable OUT0 (assuming EN0=0).
7.
Enable OUT.
Figure 10
PROGRAMMING
Normally when power is applied to the supply voltage pin the device will enter its normal operating mode
following the power-on reset sequence. However the device can be made to enter a programming mode if
a pullup resistor is connected between IN/OUT and the supply voltage pin, prior to power-up. The
method used for programming is a variant of the 1-Wire
TM
protocol used on a number of Dallas
Semiconductor products.
DS1075-IND
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HARDWARE
The hardware configuration is shown in the diagram. A bus master is used to read and write data to the
DS1075-IND's internal registers. The bus master may have either an open-drain or TTL-type
architecture.
Figure 11
Programming mode is entered by simply powering up the DS1075-IND with a pullup of approximately
5 k
. This will pull the IN/OUT pin above V
IH
on power-up and initiate the programming mode, causing
the DS1075-IND to internally release the IN/OUT pin (after t
POR
), and allow the pullup resistor to pull the
pin to the supply rail and await the Master Tx Reset pulse (see diagram).
NOTE:
To ensure normal operation any external pullup applied to IN/OUT must be greater than 20 k
in value.
This will cause the IN/OUT pin to remain below V
IH
on power-up, resulting in normal operation at the
end of t
stab
.
VCC
DS1075-IND
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Figure 12
TRANSACTION SEQUENCE
The sequence for accessing the DS1075-IND via the 1-Wire port is as follows:
Initialization
Function Command
Transaction/Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the
DS1075-IND. The presence pulse lets the bus master know that the DS1075-IND is present and is ready
to operate.
Figure 13
FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the four function commands. All
function commands are 8 bits long and are written lsb first. A list of these commands follows:
Write DIV Register [01H]
This command allows the bus master to write to the DS1075-IND's DIV register.
DS1075-IND
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Read DIV Register [A1H]
This command allows the bus master to read the DS1075-IND's DIV register.
Write MUX Register [02H]
This command allows the bus master to write to the DS1075-IND's MUX register.
Read MUX Register [A2H]
This command allows the bus master to read the DS1075-IND's MUX register.
TRANSACTION/DATA
Immediately following the Function Command, the 9 data bits are written to or read from the DS1075-
IND. This data is written/read lsb first. The following diagrams illustrate the timing. Once data transfer
is complete a new transaction sequence can be started by re-initializing the device. Therefore to program
both the DIV and MUX registers two complete transaction sequences are required.
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated below. All time slots are initiated by the master
driving the data line low. The falling edge of the data line synchronizes the DS1075-IND to the master
by triggering a delay circuit in the DS1075-IND. During write time slots, the delay circuit determines
when the DS1075-IND will sample the data line. For a read data time slot, if a 0 is to be transmitted, the
delay circuit determines how long the DS1075-IND will hold the data line low overriding the 1 generated
by the master. If the data bit is a 1, the DS1075-IND will leave the read data time slot unchanged.
WRITE 1 TIME SLOT Figure 14
DS1075-IND
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WRITE 0 TIME SLOT Figure 15
READ DATA TIME SLOT Figure 16
RETURN TO NORMAL OPERATION
When programming is complete the DS1075-IND should be powered down. If the pullup resistor on the
IN/OUT pin is removed, normal device operation will be restored next time power is applied.
DEFAULT REGISTER VALUES
Unless ordered from the factory with specific register program values, the DS1075-IND is shipped with
the following default register values:
DIV = 0 0000 0000 (Programmable divider will divide by two)
MUX = 0 0011 0100
OUT0 Disabled
Power-Down Enabled, Select Disabled
M = 4 (Ignored, see
MSEL
)
MSEL
= 1 (M prescaler bypassed)
DIV1 = 0 (N Dividers enabled)
E/
I
= 0 (Internal oscillator selected)
DS1075-IND
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
-1.0V to +7.0V
Operating Temperature
-40
C to +85
C
Storage Temperature
-55
C to +125
C
Soldering Temperature
260C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS (T
A
= -40C to +85C, V
CC
= 5V 10%)
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX UNITS NOTES
Supply Voltage
V
CC
4.5
5
5.5
V
High-level Output
Voltage(IN/OUT,
OUT0)
V
OH
I
OH
= -4 mA,
V
CC
= MIN
2.4
V
Low-level Output
Voltage(IN/OUT,OUT0)
V
OL
I
OL
= 4 mA
0.4
V
High-level Input Voltage
(
PDN
/
SELX
, OE, IN/
OUT)(OSCIN)
V
IH
V
IH
2
3
V
V
Low-level Input Voltage
(
PDN
/
SELX
, OE, IN/
OUT)(OSCIN)
V
IL
V
IL
0.8
2
V
V
High-level Input Current
(
PDN
/
SELX
, OE)
(OSCIN)
I
IH
I
IH
V
IH
=2.4V,
V
CC
=5.5V
V
IH
=V
CC
=5.5V
1
25
uA
uA
Low-level Input Current
(
PDN
/
SELX
, OE)
(OSCIN)
I
IL
I
IL
V
IL
=0,V
CC
=5.5V
V
IL
=0,V
CC
=5.5V
-1
-25
uA
uA
Supply Current (Active)
DS1075-IND-100
DS1075-IND-80
DS1075-IND-66
DS1075-IND-60
I
CC
C
L
= 15 pF
(both outputs)
35
60
mA
Standby Current
(power-down)
I
CCQ
Power-Down
Mode
0.8
uA
DS1075-IND
16 of 17
AC ELECTRICAL CHARACTERISTICS (T
A
= 0
C to 70
C, V
CC
= 5V + 10%)
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX UNITS NOTES
Output Frequency
Accuracy
f
O
V
CC
= 5V, T
A
=25
C
-0.5
0
+0.5
%
Combined Freq.
Variation
f
O
Over temp and
voltage
-3
+3
%
Long Term Stability
f
O
-0.5
+0.5
%
External clock
50
MHz
Maximum Input
Frequency
f
OSCIN
Crystal reference
25
MHz
1
Minimum Output
Frequency
f
OUT
29.3
kHz
2
Power-up Time
t
por
+ t
stab
0.1
1
ms
3, 4
Enable OUT from
PDN
?
t
stab
0.1
1
ms
4
Enable OUT0 from
PDN
?
t
stab
0.1
1
ms
4, 5
OUT Hi-Z from
PDN
?
t
pdn
1
ms
OUT0 Hi-Z from
PDN
?
t
pdn
1
ms
Load Capacitance
(IN/OUT, OUT0)
C
L
15
pF
6
Output Duty Cycle
IN/OUT
OUT0
40
40
60
60
%
%
Jitter
J
100
pS
7
NOTES:
1.
This is the maximum frequency which can be applied to OSCIN, or, the maximum crystal frequency
that can be used. If a crystal is used it must be operated in fundamental mode.
2.
The values of M, N and the frequency of OSCIN (if used) must be chosen so that this spec is met.
3.
This is the time from when V
CC
is applied until the output starts oscillating.
4.
When the device is initially powered up, or restored from the power-down mode, OE should be
asserted (high). Otherwise the start of the t
stab
interval will be delayed until OE goes high. OE can
subsequently be returned to a low level during the t
stab
interval to force out low after the t
stab
interval.
If the external mode is selected t
stab
will be a function of the OSCIN period, i.e., external clock
frequency. See "Calculated Parameters" to determine the value of t
stab
in this case.
5.
Although OE does not normally affect OUT0 operation, if OE is held low during power-up the start of
the t
stab
period will be delayed until OE is asserted. If OE remains low, OUT0 will not start.
6.
Operation with higher capacitive loads is possible but may impair output voltage swing and maximum
operation frequency.
7.
Parmeter given is a typical max.
DS1075-IND
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AC ELECTRICAL CHARACTERISTICS - CALCULATED PARAMETERS
The following characteristic are derived from various device operating parameters (frequency, mode etc.).
They are not specifically tested or guaranteed and may differ from the min and max limits shown by a
small amount due to internal device setup times and propagation delays. However, thes equations in the
max column can e used to estimate a more accurate idea of typical device performance than the
guaranteed values.
PARAMETER
SYMBOL
CONDITION
MIN
MAX
OUT
?
from OE
?
t
en
t
M
2t
M
OUT
?
from OE
?
N = 1
N = 2
t
dis
t
dis
t
OUTH
0
t
OUTH
+ t
M
t
OUTH
SELX
?
to OUT0
?
-Internal to External
-External to Internal
t
SIE
t
SEI
t
I
/2
t
I
/2
3t
I
/2 + t
E
3t
I
/2 + t
Ehigh
Break during SEL switch
-Internal to External
-External to Internal
t
LOW
t
LOW
t
I
/2
t
I
/2
t
I
/2 + t
E
3t
I
/2 + t
Elow
PDN
?
to IN/OUT Hi-Z
N = 1
N = 2
t
pdn
t
pdn
t
OUTH
0
t
OUTH
+ t
M
t
OUTH
PDN
?
to OUT0 Hi-Z
N = 1
N =
2
t
pdn
t
pdn
t
OUTH
0
t
OUTH
+ t
M
t
OUTH
PDN
?
to OUT
?
t
stab
256t
M
PDN
?
to OUT0
?
t
stab
256t
M
OUT
?
after Power-up
256t
M
OUT0
?
after Power-up
256t
M
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