_______________General Description
The MAX100 ECL-compatible, 250Msps, 8-bit analog-to-
digital converter (ADC) allows accurate digitizing of ana-
log signals from DC to 125MHz (Nyquist frequency).
Designed with Maxim's proprietary advanced bipolar
processes, the MAX100 contains a high-performance
track/hold (T/H) amplifier and a quantizer in a single
ceramic strip-line package.
The innovative design of the internal T/H assures an
exceptionally wide input bandwidth of 1.2GHz and aper-
ture delay uncertainty of less than 2ps, resulting in a high
6.8 effective bits performance. Special comparator output
design and decoding circuitry reduce out-of-sequence
code errors. The probability of erroneous codes occurring
due to metastable states is reduced to less than 1 error
per 10
15
clock cycles. Unlike other ADCs, which can
have errors that result in false full-scale or zero-scale out-
puts, the MAX100 keeps the magnitude to less than 1LSB.
The analog input is designed for either differential or single-
ended use with a 270mV range. Sense pins for the refer-
ence input allow full-scale calibration of the input range or
facilitate ratiometric use. Midpoint tap for the reference
string is available for applications that need to modify the
output coding for a user-defined bilinear response. Use of
separate high-current and low-current ground pins pro-
vides better noise immunity and highest device accuracy.
Dual output data paths provide several data output modes
for easy interfacing. These modes can be configured as
either one or two identical latched ECL outputs. An 8:16
demultiplexer mode that reduces the output data rates to
one-half the clock rate is also available.
For applications that require faster data rates, refer to
Maxim's MAX101, which allows conversion rates up to
500Msps.
____________________________Features
o
250Msps Conversion Rate
o
6.8 Effective Bits at 125MHz
o
Less than 1/2LSB INL
o
50
Differential or Single-Ended Inputs
o
270mV Input Signal Range
o
Reference Sense Inputs
o
Ratiometric Reference Inputs
o
Configurable Dual-Output Data Paths
o
Latched, ECL-Compatible Outputs
o
Low Error Rate, Less than 10
-15
Metastable States
o
Selectable On-Chip 8:16 Demultiplexer
o
84-Pin Ceramic Flat Pack
________________________Applications
High-Speed Digital Instrumentation
High-Speed Signal Processing
Medical Systems
Radar/Sonar
High-Energy Physics
Communications
______________Ordering Information
MAX100
________________________________________________________________
Maxim Integrated Products
1
DCLK
DCLK
A=B
DIV
MOD
BData
(B0B7)
AData
(A0A7)
AIN+
AIN-
CLK
CLK
VA
RT
VA
RTS
VA
RB
VA
RBS
VA
CT
VA
CTS
L
A
T
C
H
E
S
B
U
F
F
E
R
L
A
T
C
H
E
S
MODE
CONTROL
TRACK/
HOLD
FLASH CONVERTER
8
8
8
_________________________________________________________Functional Diagram
Call toll free 1-800-998-8800 for free literature.
PART
MAX100CFR* 0C to +70C
TEMP. RANGE
PIN-PACKAGE
84 Ceramic Flat Pack (with heatsink)
19-0282; Rev 0; 7/94
EVALUATION KIT
AVAILABLE
*Contact factory for 84-Pin Ceramic Flat Pack without heatsink.
250Msps, 8-Bit ADC with Track/Hold
MAX100
250Msps, 8-Bit ADC with Track/Hold
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS (Note 1)
ELECTRICAL CHARACTERISTICS
(V
EE
= -5.2V, V
CC
= +5V, R
L
= 50
to -2V, VA
RT
= 1.02V, VA
RB
= -1.02V, T
MIN
to T
MAX
= 0C to +70C, T
A
= +25C, unless
otherwise noted.) (Note 3)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:
The digital control inputs are diode protected; however, permanent damage may occur on unconnected units under high-
energy electrostatic fields. Keep unused units in conductive foam or shunt the terminals together. Discharge the conduc-
tive foam to the destination socket before insertion.
Note 2:
Typical thermal resistance, junction-to-case R
JC
= 5C/W and thermal resistance, junction to ambient (MAX100CA) R
JA
=
12C/W, providing 200 lineal ft/min airflow with heatsink. See
Package Information.
Supply Voltages
V
CC
.............................................................................0V to +7V
V
EE
...............................................................................-7V to 0V
V
CC -
V
EE
............................................................................+12V
Analog Input Voltage .............................................................2V
Digital Input Voltage .................................................-2.3V to +0V
Reference Voltage (VA
RT
) .....................................-0.3V to +1.5V
Reference Voltage (VA
RB
).....................................-1.5V to +0.3V
Data Output Current ..........................................................-33mA
DCLK Output Current ........................................................-43mA
Operating Temperature Range...............................0C to +70C
Operating Junction Temperature (Note 2)............0C to +125C
Storage Temperature Range .............................-65C to +150C
Lead Temperature (soldering, 10sec) .............................+250C
AData, BData
CONDITIONS
0.5
Bits
8
Resolution
LSB
0.6
INL
Integral Nonlinearity (Note 4)
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
f
CLK
= 250MHz,
V
IN
= 95% full scale
(Note 5)
Bits
7.1
7.4
6.8
ENOB
Effective Bits
Figure 5
Figure 5
(Note 7)
f
AIN
= 50MHz, f
CLK
= 250MHz, V
IN
= 95%
full scale (Note 6)
ps
2
t
AJ
ps
270
t
AW
Aperture Width
Aperture Jitter
230
315
Msps
250
f
CLK
Maximum Conversion Rate
dB
44.5
SNR
Signal-to-Noise Ratio
GHz
1.2
BW
3dB
Analog Input Bandwidth
AIN+ to AIN-, Table 2,
T
A
= T
MIN
to T
MAX
mV
-305
-215
V
IN
Input Voltage Range
AIN+ and AIN- with respect to GND
T
A
= T
MIN
to T
MAX
AIN+, AIN-, T
A
= T
MIN
to T
MAX
/C
0.008
Input Resistance
Temperature Coefficient
49
51
R
I
Input Resistance
mV
1.8
2.5
LSB
mV
-17
+32
V
IO
Input Offset Voltage
Least-Significant-Bit Size
T
A
= +25C
T
A
= T
MIN
to T
MAX
AData, BData,
no missing codes
0.75
T
A
= +25C
T
A
= T
MIN
to T
MAX
LSB
0.85
DNL
Differential Nonlinearity
f
AIN
= 10MHz
f
AIN
= 50MHz
f
AIN
= 125MHz
Full scale
Zero scale
ACCURACY
DYNAMIC SPECIFICATIONS
ANALOG INPUT
MAX100
250Msps, 8-Bit ADC with Track/Hold
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
EE
= -5.2V, V
CC
= +5V, R
L
= 50
to -2V, VA
RT
= 1.02V, VA
RB
= -1.02V, T
MIN
to T
MAX
= 0C to +70C, T
A
= +25C, unless
otherwise noted.) (Note 3)
VA
RT
to VA
RB
-5
20
-1.95
-1.60
CONDITIONS
V
CC
= 5.0V
AData, BData,
DCLK, DCLK
mA
710
I
CC
Positive Supply Current
V
-1.95
-1.50
V
OL
Digital Output Low Voltage
464
670
116
175
R
REF
Reference String Resistance
/C
0.02
Reference String Resistance
Temperature Coefficient
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
DIV, MOD, A=B, CLK, CLK,
T
A
= T
MIN
to T
MAX
V
-1.5
V
IL
Digital Input Low Voltage
(Note 8)
DIV, MOD, A=B, CLK, CLK,
T
A
= T
MIN
to T
MAX
V
-1.07
V
IH
Digital Input High Voltage
(Note 8)
DIV, MOD, A=B = -1.8V, T
A
= T
MIN
to T
MAX
A
0
80
I
IL
CLK, CLK, V
IL
= -1.8V (no termination),
T
A
= T
MIN
to T
MAX
Digital Input Low Current
-5
20
DIV, MOD, A=B = -0.8V, T
A
= T
MIN
to T
MAX
A
0
80
I
IH
CLK, CLK, V
IH
= -0.8V (no termination),
T
A
= T
MIN
to T
MAX
Digital Input High Current
T
A
= +25C
T
A
= T
MIN
to T
MAX
-1.02
-0.70
T
A
= +25C
T
A
= T
MIN
to T
MAX
AData, BData,
DCLK, DCLK
V
-1.10
-0.70
V
OH
Digital Output High Voltage
T
A
= +25C
T
A
= T
MIN
to T
MAX
V
EE
= -5.2V
T
A
= +25C
mA
-780
I
EE
Negative Supply Current
T
A
= T
MIN
to T
MAX
-750
-560
V
INCM
= 0.5V
T
A
= T
MIN
to T
MAX
dB
CMRR
Common-Mode Rejection Ratio
35
dB
40
V
CC
(nom) = 0.25V
Power-Supply Rejection Ratio
PSRR
T
A
= T
MIN
to T
MAX
REFERENCE INPUT
LOGIC INPUTS
LOGIC OUTPUTS (Note 9)
POWER REQUIREMENTS
V
EE
(nom) = 0.25V
40
OUTPUT CODE
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.75
0.50
0.25
0
-0.25
0
64
128
192
256
-0.50
-0.75
INL (LSBs)
OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.75
0.50
0.25
0
-0.25
0
DNL (LSBs)
64
128
192
256
-0.50
-0.75
__________________________________________Typical Operating Characteristics
(T
A
= +25C, unless otherwise noted.)
MAX100
250Msps, 8-Bit ADC with Track/Hold
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(V
EE
= -5.2V, V
CC
= +5V, R
L
= 50
to -2V, VA
RT
= 1.02V, VA
RB
= -1.02V, T
A
= +25C, unless otherwise noted.)
DIV = 0, Figure 1
DIV = 1, Figure 2
CLK, CLK, Figures 1 and 2
0.8
2.4
CLK, CLK, Figures 1 and 2
ns
1.9
5.7
t
PD1
CLK to DCLK
Propagation Delay
CONDITIONS
See Figures 3 and 4
and Table 1 (delay
depends on output
mode)
20% to 80%
Clock
Cycles
8 1/2
8 1/2
t
NPD
7 1/2
7 1/2
Pipeline Delay
(Latency)
7 1/2
7 1/2
ps
700
t
R
500
Rise Time
ns
1.9
t
PWH
ns
1.9
5.0
t
PWL
Clock Pulse Width Low
Clock Pulse Width High
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
DIV = 0, Figure 1
DIV = 1, Figure 2
0.5
2.2
ns
-1.4
-0.1
t
PD2
DCLK to A/BData
Propagation Delay
DCLK
DATA
DCLK
DATA
20% to 80%
ps
550
t
F
600
Fall Time
Divide-by-1 mode
Divide-by-
2 mode
BData
AData
Note 3:
All devices are 100% production tested at +25C and are guaranteed by design for T
A
= T
MIN
to T
MAX
as specified.
Note 4:
Deviation from best-fit straight line. See
Integral Nonlinearity section.
Note 5:
See the
Signal-to-Noise Ratio and Effective Bits section in the Definitions of Specifications.
Note 6:
SNR calculated from effective bits performance using the following equation: SNR (dB) = 1.76 + (6.02) (effective bits).
Note 7:
Clock pulse width minimum requirements t
PWL
and t
PWH
must be observed to achieve stated performance.
Note 8:
Functionality guaranteed for -1.07
V
IH
-0.7 and -2.0
V
IL
-1.5.
Note 9:
Outputs terminated through 50
to -2.0V.
MAX100
250Msps, 8-Bit ADC with Track/Hold
_______________________________________________________________________________________
5
f
CLK
= 250MHz, f
AIN
= 120.4462MHz
SER = -42.3dB, NOISE FLOOR = -65.4dB
FREQUENCY (MHz)
FFT PLOT (f
AIN
= 120.4462MHz)
0
-10
-20
-30
-40
SIGNAL AMPLITUDE (dB)
-50
-60
-70
-80
-90
-100
0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125
f
CLK
= 250MHz, f
AIN
= 10.4462MHz
SER = -45.87dB, NOISE FLOOR = -68.5dB
FFT PLOT (f
AIN
= 10.4462MHz)
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
12.5
25
37.5
50
62.5
0
SIGNAL AMPLITUDE (dB)
FREQUENCY (MHz)
0
0
50
EFFECTIVE BITS
vs. ANALOG INPUT FREQUENCY
MAX100-10
f
AIN
(MHz)
EFFECTIVE BITS
100
150
200
250
300
1
2
3
4
5
6
7
8
f
CLK
= 250MHz,
V
IN
= 95% FS
0
50
100
150
200
250
0
MAX100-12
f
AIN
(MHz)
EFFECTIVE BITS
1
2
3
4
5
6
7
8
EFFECTIVE BITS
vs. ANALOG INPUT FREQUENCY
T
CASE
= +80C,
f
CLK
= 250MHz,
V
IN
= 95% FS
300
50
100
150
200
250
0
0
EFFECTIVE BITS
vs. CLOCK FREQUENCY
MAX100-11
f
CLK
(MHz)
EFFECTIVE BITS
1
2
3
4
5
6
7
8
f
AIN
= 10.4MHz,
V
IN
= 95% FS
0
50
100
150
200
250
0
MAX100-13
f
AIN
(MHz)
EFFECTIVE BITS
1
2
3
4
5
6
7
8
T
CASE
= -15C,
f
CLK
= 250MHz
V
IN
= 95% FS
EFFECTIVE BITS
vs. ANALOG INPUT FREQUENCY
____________________________Typical Operating Characteristics (continued)
(T
A
= +25C, unless otherwise noted.)
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