_______________General Description
The MAX1003 is a dual, 6-bit analog-to-digital converter
(ADC) that combines high-speed, low-power operation
with a user-selectable input range, an internal refer-
ence, and a clock oscillator. The dual parallel ADCs are
designed to convert in-phase (I) and quadrature (Q)
analog signals into two 6-bit, offset-binary-coded digital
outputs at sampling rates up to 90Msps. The ability to
directly interface with baseband I and Q signals makes
the MAX1003 ideal for use in direct-broadcast satellite,
VSAT, and QAM16 demodulation applications.
The MAX1003 input amplifiers feature true differential
inputs, a -0.5dB analog bandwidth of 55MHz, and user-
programmable input full-scale ranges of 125mVp-p,
250mVp-p, or 500mVp-p. With an AC-coupled input
signal, matching performance between input channels
is typically better than 0.1dB gain, 1/4LSB offset, and
0.5 phase. Dynamic performance is 5.85 effective
number of bits (ENOB) with a 20MHz analog input sig-
nal, or 5.7 ENOB with a 50MHz signal.
The MAX1003 operates with +5V analog and +3.3V digi-
tal supplies for easy interfacing to +3.3V-logic-compati-
ble digital signal processors and microprocessors. It
comes in a 36-pin SSOP package.
________________________Applications
Direct Broadcast Satellite (DBS) Receivers
VSAT Receivers
Wide Local Area Networks (WLANs)
Cable Television Set-Top Boxes
____________________________Features
o
Two Matched 6-Bit ADCs
o
High Sampling Rate: 90Msps per ADC
o
Low Power Dissipation: 350mW
o
Excellent Dynamic Performance:
5.85 ENOB with 20MHz Analog Input
5.7 ENOB with 50MHz Analog Input
o
1/4LSB INL and DNL (typ)
o
Internal Bandgap Voltage Reference
o
Internal Oscillator with Overdrive Capability
o
55MHz (-0.5dB) Bandwidth Input Amplifiers with
True Differential Inputs
o
User-Selectable Input Full-Scale Range
(125mVp-p, 250mVp-p, or 500mVp-p)
o
1/4LSB Channel-to-Channel Offset Matching (typ)
o
0.1dB Gain and 0.5 Phase Matching (typ)
o
Single-Ended or Differential Input Drive
o
Flexible, 3.3V, CMOS-Compatible Digital Outputs
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
________________________________________________________________
Maxim Integrated Products
1
MAX1003
DATA
BUFFER
Q
CLOCK
DRIVER
DI0DI5
DCLK
TNK+
TNK-
DQ0DQ5
INPUT
AMP
I
IIN+
IIN-
GAIN
QIN+
QIN-
CLOCK
OUT
DATA
BUFFER
I
6
ADC
I
ADC
Q
VREF
VREF
BANDGAP
REFERENCE
OFFSET
CORREC-
TION Q
OFFSET
CORREC-
TION I
INPUT
AMP
Q
QOCC+
QOCC-
IOCC+
IOCC-
6
6
6
_________________________________________________________Functional Diagram
19-1236; Rev 0; 6/97
PART
MAX1003CAX
0C to +70C
TEMP. RANGE
PIN-PACKAGE
36 SSOP
EVALUATION KIT
AVAILABLE
______________Ordering Information
Pin Configuration appears at end of data sheet.
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +5V 5%, V
CCO
= 3.3V 300mV, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CC
to GND ............................................................-0.3V to 6.5V
V
CCO
to OGND ........................................................-0.3V to 6.5V
GND to OGND ........................................................-0.3V to 0.3V
Digital and Clock Output Pins to OGND...-0.3V to V
CCO
(10sec)
All Other Pins to GND...............................................-0.3V to V
CC
Continuous Power Dissipation (T
A
= +70C)
SSOP (derate 11.8mW/C above +70C) ...................941mW
Operating Temperature Range...............................0C to +70C
Storage Temperature Range .............................-65C to +150C
Lead Temperature (soldering, <10sec)...........................+300C
CONDITIONS
LSB
-0.5
0.25
0.5
INL
Integral Nonlinearity
Bits
6
RES
Resolution
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
GAIN = open (mid gain)
GAIN = V
CC
(high gain)
No missing codes over temperature
237.5
250
262.5
V
FSM
118.75
125
131.25
V
FSH
LSB
-0.5
0.25
0.5
DNL
Differential Nonlinearity
Other analog input driven with external source
(Note 2)
Guaranteed by design
V
1.75
2.75
V
CM
GAIN = GND (low gain)
Common-Mode Voltage Range
pF
3
5
C
IN
Input Capacitance
k
13
20
29
R
IN
Input Resistance
V
2.25
2.35
2.45
V
AOC
Input Open-Circuit Voltage
mVp-p
475
500
525
V
FSL
Full-Scale Input Range
Other oscillator input tied to V
CC
+ 0.3V
I
SOURCE
= 50A
V
0.7V
CCO
V
OH
Digital Outputs Logic-High
Voltage
k
4.8
8
12.1
R
OSC
Oscillator Input Resistance
I
SINK
= 400A
V
0.5
V
OL
Digital Outputs Logic-Low
Voltage
V
CC
= 4.75V to 5.25V (Note 3)
20MHz, full-scale I and Q analog inputs,
C
L
= 15pF (Note 4)
mW
350
PD
Power Dissipation
mA
21
I
CCO
Digital Outputs Supply Current
dB
-75
-40
PSRR
Power-Supply Rejection Ratio
mA
63
104
I
CC
Supply Current
DC ACCURACY
(Note 1)
INVERTING AND NONINVERTING ANALOG INPUTS
OSCILLATOR INPUTS
DIGITAL OUTPUTS (DI0DI5, DQ0DQ5)
POWER SUPPLY
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
_______________________________________________________________________________________
3
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +5V 5%, V
CCO
= 3.3V 300mV, T
A
= +25C, unless otherwise noted.)
Note 1:
Best-fit straight-line linearity method.
Note 2:
A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4 and 5).
Note 3:
PSRR is defined as the change in the mid-gain full-scale range as a function of the variation in V
CC
supply voltage,
expressed in decibels.
Note 4:
The current in the V
CCO
supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran-
sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig-
ital outputs to a minimum.
Note 5:
Offset-correction compensation enabled, 0.22F at Q and I compensation inputs (Figures 2 and 3).
Note 6:
t
PD
and t
SKEW
are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. t
DCLK
is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-
itive load on the outputs is 15pF.
GAIN = GND, open, V
CC
GAIN = open (mid gain), f
IN
= 50MHz,
-1dB below full scale
GAIN = open (mid gain)
5.7
ENOB
M
5.6
5.85
Effective Number of Bits
GAIN = open (mid gain)
GAIN = GND (low gain)
Q channel
I channel
dB
CONDITIONS
MHz
55
BW
Analog Input -0.5dB Bandwidth
Msps
90
f
MAX
Maximum Sample Rate
-55
XTLK
GAIN = V
CC
(high gain)
Crosstalk Between ADCs
LSB
-0.5
0.5
OFF
Input Offset (Note 5)
-0.5
0.5
dB
35.5
37
SINAD
Signal-to-Noise plus Distortion
Ratio
Bits
5.85
ENOB
L
5.8
ENOB
H
(Note 5)
dB
-0.2
0.1
0.2
AM
Amplitude Match Between
ADCs
LSB
-0.5
0.25
0.5
OMM
Offset Mismatch Between ADCs
(Note 6)
(Note 6)
ns
1.5
t
SKEW
Data Valid Skew
ns
3.6
t
PD
Clock to Data Propagation
Delay
degrees
-2
0.5
2
PM
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Phase Match Between ADCs
TNK+ to DCLK (Note 6)
ns
5.3
t
DCLK
Input to DCLK Delay
Figure 8
ns
7.5
t
AD
Aperture Delay
Figure 8
clock
cycle
1
PD
Pipeline Delay
TIMING CHARACTERISTICS
(Data outputs: R
L
= 1M
, C
L
= 15pF)
DYNAMIC PERFORMANCE
(Gain = open, external 90MHz clock (Figure 7), V
INI
= V
INQ
= 20MHz sine, amplitude -1dB below
full scale, unless otherwise noted.)
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
4
_______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(V
CC
= +5V 5%, V
CCO
= 3.3V 300mV, f
CLK
= 90Msps, GAIN = open (midgain) MAX1003 evaluation kit, T
A
= +25C, unless
otherwise noted.)
6.0
5.0
10
100
EFFECTIVE NUMBER OF BITS
vs. ANALOG INPUT FREQUENCY
5.2
MAX1003-01
ANALOG INPUT FREQUENCY (MHz)
EFFECTIVE NUMBER OF BITS
5.4
5.6
5.8
f
CLK
= 90Msps
-1.0
1
10
100
ANALOG INPUT BANDWIDTH
-0.8
MAX1003-02
ANALOG INPUT FREQUENCY (MHz)
MAGNITUDE (dB) -0.6
-0.2
-0.4
0
5.5
1
10
100
EFFECTIVE NUMBER OF BITS
vs. SAMPLING/CLOCK FREQUENCY
5.6
MAX1003-03
CLOCK FREQUENCY (MHz)
EFFECTIVE NUMBER OF BITS
5.7
5.9
5.8
6.0
f
IN
= 20MHz
-50
1k
100k
1M
OSCILLATOR OPEN-LOOP PHASE NOISE
vs. FREQUENCY OFFSET
-110
-130
-90
-70
MAX1003-04
FREQUENCY OFFSET FROM CARRIER (Hz)
PHASE NOISE (dBc)
10k
0.50
-0.50
0
64
INTEGRAL NONLINEARITY
vs. CODE
-0.25
0.25
MAX1003-06
CODE
INL (LSB)
10
20
30
40
50
60
0
0.50
-0.50
0
64
DIFFERENTIAL NONLINEARITY
vs. CODE
-0.25
0.25
MAX1003-07
CODE
DNL (LSB)
10
20
30
40
50
60
0
-60
-40
-20
0
0
9
18
27
36
45
FFT PLOT
MAX1003-05
FREQUENCY (MHz)
AMPLITUDE (dB)
f
IN
= 19.9512MHz
f
CLK
= 90.000MHz
1024 POINTS
AC COUPLED
SINGLE ENDED
AVERAGED
_______________Detailed Description
Converter Operation
The MAX1003 contains two 6-bit analog-to-digital con-
verters (ADCs), a buffered voltage reference, and oscil-
lator circuitry. The ADCs use a flash conversion
technique to convert an analog input signal into a 6-bit
parallel digital output code. The MAX1003's unique
design includes 63 fully differential comparators and a
proprietary encoding scheme that ensures no more
than 1LSB dynamic encoding error. The control logic
interfaces easily to most digital signal processors
(DSPs) and microprocessors (Ps) with +3.3V CMOS-
compatible logic interfaces. Figure 1 shows the
MAX1003 in a typical application.
Programmable Input Amplifiers
The MAX1003 has two (I and Q) programmable-gain
input amplifiers with a -0.5dB bandwidth of 55MHz and
true differential inputs. To maximize performance in
high-speed systems, each amplifier has less than 5pF
of input capacitance. The input amplifier gain is pro-
grammed, via the GAIN pin, to provide three possible
input full-scale ranges (FSRs) as shown in Table 1.
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
_______________________________________________________________________________________
5
______________________________________________________________Pin Description
PIN
Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1).
GAIN
1
FUNCTION
NAME
Positive I-Channel Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
IOCC+
2
I-Channel Noninverting Analog Input
IIN+
4
Negative I-Channel Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
IOCC-
3
+5V 5% Supply. Bypass with a 0.01F capacitor to GND (pin 7).
V
CC
6
+5V 5% Supply. Bypass with a 0.01F capacitor to GND (pin 11).
V
CC
8
Analog Ground
GND
7, 11, 12,
18, 19
I-Channel Inverting Analog Input
IIN-
5
Negative Oscillator/Clock Input
TNK-
10
Q-Channel Inverting Analog Input
QIN-
14
+5V 5% Supply. Bypass with a 0.01F capacitor to GND (pin 12).
V
CC
13
Negative Q-Channel Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
QOCC-
16
Q-Channel Digital Outputs 05. DQ5 is the most significant bit (MSB).
DQ5DQ0
2025
Positive Q-Channel Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
QOCC+
17
Q-Channel Noninverting Analog Input
QIN+
15
Positive Oscillator/Clock Input
TNK+
9
Digital Output Ground
OGND
27
I-Channel Digital Outputs 05. DI5 is the most significant bit (MSB).
DI0DI5
3035
Digital Clock Output. Frames the output data.
DCLK
29
Digital Output Supply, +3.3V 300mV. Bypass each with a 47pF capacitor to OGND (pin 27).
V
CCO
26, 28
+5V 5% Supply. Bypass with a 0.01F capacitor to GND (pin 19).
V
CC
36
250
Open
125
V
CC
GAIN
500
GND
INPUT FULL-SCALE RANGE
(mVp-p)
Table 1. Input Amplifier Programming
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