General Description
The MAX1011 is a 6-bit analog-to-digital converter
(ADC) that combines high-speed, low-power operation
with a user-selectable input range, an internal refer-
ence, and a clock oscillator. The ADC converts analog
signals into binary-coded digital outputs at sampling
rates up to 90Msps. The ability to directly interface with
baseband signals makes the MAX1011 ideal for use in
a wide range of communications and instrumentation
applications.
The MAX1011's input amplifier features a true differential
input, a -0.5dB analog bandwidth of 55MHz, and a user-
programmable input full-scale range of 125mVp-p,
250mVp-p, or 500mVp-p. With an AC-coupled signal,
input offset is typically less than 1/4LSB. Dynamic per-
formance is 5.85 effective number of bits (ENOB) with a
20MHz analog input signal, or 5.7 ENOB with a 50MHz
signal.
The MAX1011 operates with +5V analog and +3.3V digi-
tal supplies for easy interfacing to +3.3V-logic-compatible
digital signal processors and microprocessors. It comes
in a 24-pin QSOP package.
Applications
IF Sampling Receivers
VSAT Receivers
Wide Local Area Networks (WLANs)
Instrumentation
Features
o
High Sampling Rate: 90Msps
o
Low Power Dissipation: 215mW
o
Excellent Dynamic Performance:
5.85 ENOB with 20MHz Analog Input
5.7 ENOB with 50MHz Analog Input
o
1/4LSB INL and DNL (typ)
o
1/4LSB Input Offset (typ)
o
Internal Bandgap Voltage Reference
o
Internal Oscillator with Overdrive Capability
o
55MHz (-0.5dB) Bandwidth Input Amplifier with
True Differential Input
o
User-Selectable Full-Scale Range
(125mVp-p, 250mVp-p, or 500mVp-p)
o
Single-Ended or Differential Input Drive
o
Flexible, 3.3V, CMOS-Compatible Digital Outputs
MAX1011
Low-Power, 90Msps, 6-Bit ADC
________________________________________________________________
Maxim Integrated Products
1
MAX1011
D0D5
DCLK
TNK+
TNK-
INPUT
AMP
IN+
IN-
GAIN
DATA
BUFFER
6
ADC
VREF
BANDGAP
REFERENCE
OCC+
OCC-
6
OFFSET
CORREC-
TION
CLOCK
OUT
CLOCK
DRIVER
Functional Diagram
19-1335; Rev 0a; 2/98
PART
MAX1011CEG
0C to +70C
TEMP. RANGE
PIN-PACKAGE
24 QSOP
EVALUATION KIT
AVAILABLE
Pin Configuration appears at end of data sheet.
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
For small orders, phone 408-737-7600 ext. 3468.
Ordering Information
MAX1011
Low-Power, 90Msps, 6-Bit ADC
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +5V 5%, V
CCO
= 3.3V 300mV,
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CC
to GND ..........................................................-0.3V to +6.5V
V
CCO
to OGND......................................................-0.3V to +6.5V
GND to OGND ......................................................-0.3V to +0.3V
Digital and Clock Output Pins to OGND...-0.3V to V
CCO
(10sec)
All Other Pins to GND...............................................-0.3V to V
CC
Continuous Power Dissipation (T
A
= +70C)
24-Pin QSOP (derate 10mW/C above +70C)...........800mW
Operating Temperature Range...............................0C to +70C
Storage Temperature Range .............................-65C to +150C
Lead Temperature (soldering, <10sec)...........................+300C
CONDITIONS
LSB
-0.5
0.25
0.5
INL
Integral Nonlinearity
Bits
6
RES
Resolution
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
GAIN = open (mid gain)
GAIN = V
CC
(high gain)
No missing codes over temperature
237.5
250
262.5
V
FSM
118.75
125
131.25
V
FSH
LSB
-0.5
0.25
0.5
DNL
Differential Nonlinearity
Other analog input driven with external source
(Note 2)
Guaranteed by design
V
1.75
2.75
V
CM
GAIN = GND (low gain)
Common-Mode Voltage Range
pF
1.5
3
C
IN
Input Capacitance
k
13
20
29
R
IN
Input Resistance
V
2.25
2.35
2.45
V
AOC
Input Open-Circuit Voltage
mVp-p
475
500
525
V
FSL
Full-Scale Input Range
Other oscillator input tied to V
CC
+ 0.3V
I
SOURCE
= 50A
V
0.7V
CCO
V
OH
Digital Outputs Logic-High
Voltage
k
4.8
8
12.1
R
OSC
Oscillator Input Resistance
I
SINK
= 400A
V
0.5
V
OL
Digital Outputs Logic-Low
Voltage
V
CC
= 4.75V to 5.25V (Note 3)
20MHz, full-scale analog inputs,
C
L
= 15pF (Note 4)
mW
215
PD
Power Dissipation
mA
8.5
13.8
I
CCO
Digital Outputs Supply Current
dB
-65
-40
PSRR
Power-Supply Rejection Ratio
mA
37
63.5
I
CC
Supply Current
DC ACCURACY
(Note 1)
INVERTING AND NONINVERTING ANALOG INPUTS
OSCILLATOR INPUTS
DIGITAL OUTPUTS (D0D5)
POWER SUPPLY
MAX1011
Low-Power, 90Msps, 6-Bit ADC
_______________________________________________________________________________________
3
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +5V 5%, V
CCO
= 3.3V 300mV,
T
A
= +25C
, unless otherwise noted.)
Note 1:
Best-fit straight-line linearity method.
Note 2:
A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4 and 5).
Note 3:
PSRR is defined as the change in the mid-gain, full-scale range as a function of the variation in V
CC
supply voltage,
expressed in decibels.
Note 4:
The current in the V
CCO
supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran-
sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig-
ital outputs to a minimum.
Note 5:
Offset-correction compensation enabled, 0.22F at compensation inputs (Figures 2 and 3).
Note 6:
t
PD
and t
SKEW
are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. t
DCLK
is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-
itive load on the outputs is 15pF.
GAIN = GND, open, V
CC
GAIN = open (mid gain), f
IN
= 50MHz,
-1dB below full scale
GAIN = open (mid gain)
5.7
ENOB
M
5.6
5.85
Effective Number of Bits
GAIN = open (mid gain)
GAIN = GND (low gain)
Guaranteed by design
CONDITIONS
MHz
55
BW
Analog Input -0.5dB Bandwidth
Msps
90
f
MAX
Maximum Sample Rate
GAIN = V
CC
(high gain)
LSB
OFF
Input Offset (Note 5)
-0.5
0.5
dB
35.5
37
SINAD
Signal-to-Noise Plus Distortion
Ratio
Bits
5.85
ENOB
L
5.8
ENOB
H
(Note 6)
(Note 6)
ns
1
t
SKEW
Data Valid Skew
ns
3.0
t
PD
Clock to Data Propagation
Delay
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
TNK+ to DCLK (Note 6)
ns
4.5
t
DCLK
Input to DCLK Delay
Figure 8
ns
5.5
t
AD
Aperture Delay
Figure 8
clock
cycle
1
PD
Pipeline Delay
TIMING CHARACTERISTICS
(Data outputs: R
L
= 1M
, C
L
= 15pF)
DYNAMIC PERFORMANCE
(Gain = open, external 90MHz clock (Figure 7), V
IN
= 20MHz sine, amplitude -1dB below
full scale, unless otherwise noted.)
MAX1011
Low-Power, 90Msps, 6-Bit ADC
4
_______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(V
CC
= +5V 5%, V
CCO
= 3.3V 300mV, f
CLK
= 90Msps, GAIN = open (midgain) MAX1011 evaluation kit, T
A
= +25C, unless
otherwise noted.)
6.0
5.0
10
100
EFFECTIVE NUMBER OF BITS
vs. ANALOG INPUT FREQUENCY
5.2
MAX1011-01
ANALOG INPUT FREQUENCY (MHz)
EFFECTIVE NUMBER OF BITS
5.4
5.6
5.8
f
CLK
= 90Msps
-1.0
1
10
100
ANALOG INPUT BANDWIDTH
-0.8
MAX1011-02
ANALOG INPUT FREQUENCY (MHz)
MAGNITUDE (dB) -0.6
-0.2
-0.4
0
5.5
1
10
100
EFFECTIVE NUMBER OF BITS
vs. SAMPLING/CLOCK FREQUENCY
5.6
MAX1011-03
CLOCK FREQUENCY (MHz)
EFFECTIVE NUMBER OF BITS
5.7
5.9
5.8
6.0
f
IN
= 20MHz
-50
1k
100k
1M
OSCILLATOR OPEN-LOOP PHASE NOISE
vs. FREQUENCY OFFSET
-110
-130
-90
-70
MAX1011-04
FREQUENCY OFFSET FROM CARRIER (Hz)
PHASE NOISE (dBc)
10k
0.50
-0.50
0
64
INTEGRAL NONLINEARITY
vs. CODE
-0.25
0.25
MAX1011-06
CODE
INL (LSB)
10
20
30
40
50
60
0
0.50
-0.50
0
64
DIFFERENTIAL NONLINEARITY
vs. CODE
-0.25
0.25
MAX1003-07
CODE
DNL (LSB)
10
20
30
40
50
60
0
-80
-60
-40
-20
0
0
9
18
27
36
45
FFT PLOT
MAX1011-05
FREQUENCY (MHz)
AMPLITUDE (dB)
f
IN
= 19.9512MHz
f
CLK
= 90.000MHz
1024 POINTS
AC-COUPLED
SINGLE-ENDED
AVERAGED
_______________Detailed Description
Converter Operation
The MAX1011 integrates a 6-bit analog-to-digital con-
verter (ADC), a buffered voltage reference, and oscilla-
tor circuitry. The ADC uses a flash conversion technique
to convert an analog input signal into a 6-bit parallel
digital output code. The MAX1011's unique design
includes 63 fully differential comparators and a propri-
etary encoding scheme that ensures no more than
1LSB dynamic encoding error. The control logic inter-
faces easily to most digital signal processors (DSPs)
and microprocessors (Ps) with +3.3V CMOS-compati-
ble logic interfaces. Figure 1 shows the MAX1011 in a
typical application.
Programmable Input Amplifier
The MAX1011 has a programmable-gain input amplifier
with a -0.5dB bandwidth of 55MHz and a true differen-
tial input. To maximize performance in high-speed
systems, the amplifier has less than 3pF of input
capacitance. The input amplifier gain is programmed
via the GAIN pin to provide three possible input full-
scale ranges (FSRs) as shown in Table 1.
Single-ended and differential AC-coupled input circuit
examples are shown in Figures 2 and 3. Each of the
MAX1011
Low-Power, 90Msps, 6-Bit ADC
_______________________________________________________________________________________
5
Pin Description
PIN
Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1).
GAIN
1
FUNCTION
NAME
Positive Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled inputs. Ground
pin 2 for DC-coupled inputs.
OCC+
2
Noninverting Analog Input
IN+
4
Negative Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled inputs. Ground
pin 3 for DC-coupled inputs.
OCC-
3
+5V 5% Supply. Bypass with a 0.01F capacitor to GND (pin 9).
V
CC
6
Analog Ground
GND
9, 10,
12, 13
Inverting Analog Input
IN-
5
+5V 5% Supply. Bypass with a 0.01F capacitor to GND (pin 10).
V
CC
11
Digital Clock Output. Frames the output data.
DCLK
18
Digital Output Supply, +3.3V 300mV. Bypass with a 47pF capacitor to OGND (pin 16).
V
CCO
17
Digital Outputs 05. D5 is the most significant bit (MSB).
D0D5
1924
250
Open
125
V
CC
GAIN
500
GND
INPUT FULL-SCALE RANGE
(mVp-p)
Table 1. Input Amplifier Programming
Positive Oscillator/Clock Input
TNK+
7
Negative Oscillator/Clock Input
TNK-
8
No Connection
N.C.
15
Digital Output Ground
OGND
16
+5V 5% Supply. Bypass with a 0.01F capacitor to GND (pin 13).
V
CC
14
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