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General Description
The MAX104 PECL-compatible, 1Gsps, 8-bit analog-to-
digital converter (ADC) allows accurate digitizing of
analog signals with bandwidths to 2.2GHz. Fabricated
on Maxim's proprietary advanced GST-2 bipolar
process, the MAX104 integrates a high-performance
track/hold (T/H) amplifier and a quantizer on a single
monolithic die.
The innovative design of the internal T/H, which has an
exceptionally wide 2.2GHz full-power input bandwidth,
results in high performance (greater than 7.5 effective
bits) at the Nyquist frequency. A fully differential com-
parator design and decoding circuitry reduce out-of-
sequence code errors (thermometer bubbles or sparkle
codes) and provide excellent metastable performance
of one error per 10
16
clock cycles. Unlike other ADCs
that can have errors resulting in false full- or zero-scale
outputs, the MAX104 limits the error magnitude to
1LSB.
The analog input is designed for either differential or
single-ended use with a 250mV input voltage range.
Dual, differential, PECL-compatible output data paths
ensure easy interfacing and include an 8:16 demulti-
plexer feature that reduces output data rates to one-half
the sampling clock rate. The PECL outputs can be
operated from any supply between +3V to +5V for com-
patibility with +3.3V or +5V referenced systems. Control
inputs are provided for interleaving additional MAX104
devices to increase the effective system sampling rate.
The MAX104 is packaged in a 25mm x 25mm, 192-con-
tact Enhanced Super-Ball Grid Array (ESBGATM) and is
specified over the commercial (0C to +70C) tempera-
ture range.
Applications
Digital RF/IF Signal Processing
Direct RF Downconversion
High-Speed Data Acquisition
Digital Oscilloscopes
High-Energy Physics
Radar/Sonar/ECM Systems
ATE Systems
Features
o
1Gsps Conversion Rate
o
2.2GHz Full-Power Analog Input Bandwidth
o
>7.5 Effective Bits at f
IN
= 500MHz (Nyquist
Frequency)
o
0.25LSB INL and DNL
o
50
Differential Analog Inputs
o
250mV Input Signal Range
o
On-Chip, +2.5V Precision Bandgap Voltage
Reference
o
Latched, Differential PECL Digital Outputs
o
Low Error Rate: 10
-16
Metastable States at 1Gsps
o
Selectable 8:16 Demultiplexer
o
Internal Demux Reset Input with Reset Output
o
192-Contact ESBGA Package
MAX104
5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
________________________________________________________________
Maxim Integrated Products
1
ESBGA
TOP VIEW
MAX104
19-1459; Rev 1; 5/99
PART
MAX104CHC
0C to +70C
TEMP. RANGE
PIN-PACKAGE
192 ESBGA
EVALUATION KIT
AVAILABLE
Typical Operating Circuit appears at end of data sheet.
192-Contact ESBGA
Ball Assignment Matrix
Ordering Information
ESBGA is a trademark of Amkor/Anam.
MAX104
5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
CC
A = V
CC
I = V
CC
D = +5.0V 5%, V
EE
= -5.0V 5%, V
CC
O = +3.0V to V
CC
D, REFIN connected to REFOUT, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25C.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CC
A to GNDA .........................................................-0.3V to +6V
V
CC
D to GNDD.........................................................-0.3V to +6V
V
CC
I to GNDI ............................................................-0.3V to +6V
V
CC
O to GNDD ........................................-0.3V to (V
CC
D + 0.3V)
AUXEN1, AUXEN2 to GND .....................-0.3V to (V
CC
D + 0.3V)
V
EE
to GNDI..............................................................-6V to +0.3V
Between GNDs......................................................-0.3V to +0.3V
V
CC
A to V
CC
D .......................................................-0.3V to +0.3V
V
CC
A to V
CC
I .........................................................-0.3V to +0.3V
PECL Digital Output Current ...............................................50mA
REFIN to GNDR ........................................-0.3V to (V
CC
I + 0.3V)
REFOUT Current ................................................+100A to -5mA
ICONST, IPTAT to GNDI .......................................-0.3V to +1.0V
TTL/CMOS Control Inputs (DEMUXEN,
DIVSELECT)..........................................-0.3V to (V
CC
D + 0.3V)
RSTIN+, RSTIN- ......................................-0.3V to (V
CC
O + 0.3V)
VOSADJ Adjust Input ................................-0.3V to (V
CC
I + 0.3V)
CLK+ to CLK- Voltage Difference..........................................3V
CLK+, CLK-.....................................(V
EE
- 0.3V) to (GNDD + 1V)
CLKCOM.........................................(V
EE
- 0.3V) to (GNDD + 1V)
VIN+ to VIN- Voltage Difference ............................................2V
VIN+, VIN- to GNDI................................................................2V
Continuous Power Dissipation (T
A
= +70C)
192-Contact ESBGA (derate 61mW/C above +70C) ......4.88W
(with heatsink and 200 LFM airflow,
derate 106mW/C above +70C) ........................................8.48W
Operating Temperature Range
MAX104CHC........................................................0C to +70C
Operating Junction Temperature.....................................+150C
Storage Temperature Range .............................-65C to +150C
T
A
= +25C
Referenced to GNDR
0 < I
SOURCE
< 2.5mA
Driving REFIN input only
VIN+ and VIN- to GNDI, T
A
= +25C
VOSADJ = 0 to 2.5V
Signal + offset w.r.t. GNDI
Note 1
T
A
= +25C
No missing codes guaranteed
CONDITIONS
k
4
5
R
REF
Reference Input Resistance
mV
5
REFOUT
Reference Output Load
Regulation
V
2.475
2.50
2.525
REFOUT
Reference Output Voltage
LSB
4
5.5
Input V
OS
Adjust Range
k
14
25
R
VOS
Input Resistance (Note 2)
LSB
-0.5
0.25
0.5
INL
Integral Nonlinearity (Note 1)
Bits
8
RES
Resolution
ppm/C
150
TC
R
Input Resistance Temperature
Coefficient
49
50
51
R
IN
Input Resistance
V
0.8
V
CM
Common-Mode Input Range
mVp-p
475
500
525
V
FSR
Full-Scale Input Range
LSB
-0.5
0.25
0.5
DNL
Differential Nonlinearity (Note 1)
Codes
None
Missing Codes
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ACCURACY
ANALOG INPUTS
VOS ADJUST CONTROL INPUT
REFERENCE INPUT AND OUTPUT
MAX104
5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
_______________________________________________________________________________________
3
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
A = V
CC
I = V
CC
D = +5.0V 5%, V
EE
= -5.0V 5%, V
CC
O = +3.0V to V
CC
D, REFIN connected to REFOUT, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25C.)
CLK+ and CLK- to CLKCOM, T
A
= +25C
V
IH
= 2.4V
V
IL
= 0
CONDITIONS
V
-1.475
V
IL
Digital Input Low Voltage
V
-1.165
V
IH
Digital Input High Voltage
A
-1
1
I
IL
Low-Level Input Current
ppm/C
150
TC
R
Input Resistance Temperature
Coefficient
48
50
52
R
CLK
Clock Input Resistance
A
50
I
IH
High-Level Input Current
V
0.8
V
IL
Low-Level Input Voltage
V
2.0
V
IH
High-Level Input Voltage
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
V
-1.810
-1.620
V
OL
Digital Output Low Voltage
V
-1.025
-0.880
V
OH
Digital Output High Voltage
W
5.25
P
DISS
Power Dissipation (Note 6)
mA
75
115
I
CC
O
Output Supply Current (Note 6)
mA
205
340
I
CC
D
Digital Supply Current
mA
-290
-210
I
EE
Negative Input Supply Current
mA
108
150
I
CC
I
Positive Input Supply Current
mA
480
780
I
CC
A
Positive Analog Supply Current
(Note 9)
VIN+ = VIN- = 0.1V
dB
40
73
PSRR+
Positive Power-Supply Rejection
Ratio (Note 8)
dB
40
68
CMRR
Common-Mode Rejection Ratio
(Note 7)
(Note 10)
dB
40
68
PSRR-
Negative Power-Supply
Rejection Ratio (Note 8)
CLOCK INPUTS
(Note 3)
TTL/CMOS CONTROL INPUTS (DEMUXEN, DIVSELECT)
DEMUX RESET INPUT
(Note 4)
PECL DIGITAL OUTPUTS
(Note 5)
POWER REQUIREMENTS
MAX104
5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(V
CC
A = V
CC
I = V
CC
D = +5.0V, V
EE
= -5.0V, V
CC
O = +3.3V, REFIN connected to REFOUT, f
S
= 1Gsps, f
IN
at -1dBFS, T
A
= +25C,
unless otherwise noted.)
f
IN1
= 124MHz, f
IN2
= 126MHz,
at -7dB below full-scale
f
IN
= 500MHz
f
IN
= 1000MHz
CONDITIONS
dB
-57.7
IMD
Two-Tone Intermodulation
7.40
ENOB
1000
GHz
2.2
BW
-3dB
Analog Input Full-Power
Bandwidth
V/V
1.1:1
VSWR
Analog Input VSWR
7.52
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Differential
Single-ended
f
IN
= 500MHz
7.49
ENOB
500
7.2
7.55
Differential
Single-ended
f
IN
= 1000MHz
46.4
SNR
1000
46.4
f
IN
= 125MHz
Differential
Single-ended
Bits
7.73
ENOB
125
Effective Number of Bits
(Note 11)
7.4
7.74
Differential
Single-ended
f
IN
= 500MHz
47.1
SNR
500
43.5
47.0
Differential
Single-ended
f
IN
= 125MHz
dB
47.4
SNR
125
Signal-to-Noise Ratio
(No Harmonics)
44.2
47.4
Differential
Single-ended
f
IN
= 500MHz
f
IN
= 1000MHz
-49.6
THD
1000
-52.6
-51.3
THD
500
Differential
Single-ended
-50
-52.5
Differential
Single-ended
f
IN
= 125MHz
dB
-67.4
THD
125
Total Harmonic Distortion
(Note 12)
-61
-66.2
Differential
Single-ended
f
IN
= 500MHz
f
IN
= 1000MHz
52.5
SFDR
1000
52.8
52.3
SFDR
500
Differential
Single-ended
50
52.3
Differential
Single-ended
f
IN
= 125MHz
dB
69.5
SFDR
125
Spurious-Free Dynamic Range
62
68.9
Differential
Single-ended
f
IN
= 500MHz
f
IN
= 1000MHz
46.3
SINAD
1000
47.0
46.9
SINAD
500
Differential
Single-ended
45.1
47.2
Differential
Single-ended
f
IN
= 125MHz
dB
48.3
SINAD
125
Signal-to-Noise Ratio and
Distortion (Note 11)
46.3
48.3
Differential
Single-ended
VOSADJ control input open
LSB
-1.5
0
+1.5
V
OS
Transfer Curve Offset
ANALOG INPUT
DYNAMIC SPECIFICATIONS
MAX104
5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
_______________________________________________________________________________________
5
Note 1:
Static linearity parameters are computed from a "best-fit" straight line through the code transition points. The full-scale
range (FSR) is defined as 256
slope of the line.
Note 2:
The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit
voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.
Note 3:
The clock input's termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings
on the CLK+ and CLK- inputs.
Note 4:
Input logic levels are measured with respect to the V
CC
O power-supply voltage.
Note 5:
All PECL digital outputs are loaded with 50
to V
CC
O - 2.0V. Measurements are made with respect to the V
CC
O power-
supply voltage.
Note 6:
The current in the V
CC
O power supply does not include the current in the digital output's emitter followers, which is a func-
tion of the load resistance and the V
TT
termination voltage.
Note 7:
Common-Mode Rejection Ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in
the common-mode voltage, expressed in dB.
Note 8:
Power-Supply Rejection Ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in
power-supply voltage, expressed in dB.
Note 9:
Measured with the positive supplies tied to the same potential; V
CC
A = V
CC
D = V
CC
I. V
CC
varies from +4.75V to +5.25V.
Note 10:
V
EE
varies from -5.25V to -4.75V.
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
A = V
CC
I = V
CC
D = +5.0V, V
EE
= -5.0V, V
CC
O = +3.3V, REFIN connected to REFOUT, f
S
= 1Gsps, f
IN
at -1dBFS, T
A
= +25C,
unless otherwise noted.)
Figure 17
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
Figure 15
Figure 4
Figure 4
CONDITIONS
Clock
Cycles
7.5
Primary Port Pipeline
Delay
ps
180
t
FDREADY
DREADY Fall Time
ps
220
t
RDREADY
DREADY Rise Time
ps
360
t
FDATA
DATA Fall Time
ns
0.45
t
PWL
Clock Pulse Width Low
Gsps
1
f
MAX
Maximum Sample Rate
ps
420
t
RDATA
DATA Rise Time
ps
0
t
SU
Reset Input Data Setup Time
(Note 13)
ps
100
t
AD
Aperture Delay
ps
<0.5
t
AJ
Aperture Jitter
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Figure 17
ns
0.45
5
t
PWH
Clock Pulse Width High
Figure 15
ps
0
t
HD
Reset Input Data Hold Time
(Note 13)
Figure 17
ns
2.2
t
PD1
CLK to DREADY Propagation
Delay
Figure 17
ps
-50
150
350
t
PD2
DREADY to DATA Propagation
Delay (Note 14)
8.5
Figures 6, 7, 8
Clock
Cycles
9.5
t
PDA
Auxiliary Port Pipeline
Delay
t
PDP
Figures 6, 7, 8
TIMING CHARACTERISTICS
DIV1, DIV2 modes
DIV4 mode
7.5
DIV1, DIV2 modes
DIV4 mode
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