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General Description
The MAX106 PECL-compatible, 600Msps, 8-bit analog-to-
digital converter (ADC) allows accurate digitizing of ana-
log signals with bandwidths to 2.2GHz. Fabricated on
Maxim's proprietary advanced GST-2 bipolar process, the
MAX106 integrates a high-performance track/hold (T/H)
amplifier and a quantizer on a single monolithic die.
The innovative design of the internal T/H, which has an
exceptionally wide 2.2GHz full-power input bandwidth,
results in high, 7.6 effective bits performance at the
Nyquist frequency. A fully differential comparator design
and decoding circuitry combine to reduce out-of-
sequence code errors (thermometer bubbles or sparkle
codes) and provide excellent metastable performance of
one error per 10
27
clock cycles. Unlike other ADCs, which
can have errors that result in false full- or zero-scale out-
puts, the MAX106 limits the error magnitude to 1LSB.
The analog input is designed for either differential or sin-
gle-ended use with a 250mV input voltage range. Dual,
differential, PECL-compatible output data paths ensure
easy interfacing and include an 8:16 demultiplexer feature
that reduces output data rates to one-half the sampling
clock rate. The PECL outputs can be operated from any
supply between +3V to +5V for compatibility with +3.3V or
+5V referenced systems. Control inputs are provided for
interleaving additional MAX106 devices to increase the
effective system sampling rate.
The MAX106 is packaged in a 25mm x 25mm, 192-con-
tact Enhanced Super-Ball-Grid Array (ESBGATM), and is
specified over the commercial (0C to +70C) temperature
range. For a pin-compatible higher speed upgrade, refer
to the MAX104 (1Gsps) and MAX108 (1.5Gsps) data
sheets.
Applications
Digital RF/IF Signal Processing
Direct RF Downconversion
High-Speed Data Acquisition
Digital Oscilloscopes
High-Energy Physics
Radar/ECM Systems
ATE Systems
Features
o
600Msps Conversion Rate
o
2.2GHz Full-Power Analog Input Bandwidth
o
7.6 Effective Bits at f
IN
= 300MHz
(Nyquist frequency)
o
0.25LSB INL and DNL
o
50
Differential Analog Inputs
o
250mV Input Signal Range
o
On-Chip, +2.5V Precision Bandgap Voltage
Reference
o
Latched, Differential PECL Digital Outputs
o
Low Error Rate: 10
-27
Metastable States
o
Selectable 8:16 Demultiplexer
o
Internal Demux Reset Input with Reset Output
o
192-Contact ESBGA
o
Pin Compatible with Faster MAX104/MAX108
MAX106
5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
________________________________________________________________
Maxim Integrated Products
1
19-1486; Rev 0; 7/99
PART
MAX106CHC
0C to +70C
TEMP. RANGE
PIN-PACKAGE
192 ESBGA
Typical Operating Circuit appears at end of data sheet.
Ordering Information
ESBGA
TOP VIEW
MAX106
192-Contact ESBGA
Ball Assignment Matrix
ESBGA is a trademark of Amkor/Anam.
MAX106
5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
CC
A = V
CC
I = V
CC
D = +5.0V 5%, V
EE
= -5.0V 5%, V
CC
O = +3.0V to V
CC
D, REFIN connected to REFOUT, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25C.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CC
A to GNDA .........................................................-0.3V to +6V
V
CC
D to GNDD.........................................................-0.3V to +6V
V
CC
I to GNDI ............................................................-0.3V to +6V
V
CC
O to GNDD ........................................-0.3V to (V
CC
D + 0.3V)
AUXEN1, AUXEN2 to GND .....................-0.3V to (V
CC
D + 0.3V)
V
EE
to GNDI..............................................................-6V to +0.3V
Between GNDs......................................................-0.3V to +0.3V
V
CC
A to V
CC
D .......................................................-0.3V to +0.3V
V
CC
A to V
CC
I .........................................................-0.3V to +0.3V
PECL Digital Output Current ...............................................50mA
REFIN to GNDR ........................................-0.3V to (V
CC
I + 0.3V)
REFOUT Current ................................................+100A to -5mA
ICONST, IPTAT to GNDI .......................................-0.3V to +1.0V
TTL/CMOS Control Inputs
(DEMUXEN, DIVSELECT) ....................-0.3V to (V
CC
D + 0.3V)
RSTIN+, RSTIN- ......................................-0.3V to (V
CC
O + 0.3V)
VOSADJ Adjust Input ................................-0.3V to (V
CC
I + 0.3V)
CLK+ to CLK- Voltage Difference..........................................3V
CLK+, CLK-.....................................(V
EE
- 0.3V) to (GNDD + 1V)
CLKCOM.........................................(V
EE
- 0.3V) to (GNDD + 1V)
VIN+ to VIN- Voltage Difference ............................................2V
VIN+, VIN- to GNDI................................................................2V
Continuous Power Dissipation (T
A
= +70C)
192-Contact ESBGA (derate 61mW/C above +70C) ...4.88W
(with heatsink and 200LFM airflow,
derate 106mW/C above +70C) ....................................8.48W
Operating Temperature Range
MAX106CHC........................................................0C to +70C
Operating Junction Temperature.....................................+150C
Storage Temperature Range .............................-65C to +150C
T
A
= +25 C
Referenced to GNDR
0 < I
SOURCE
< 2.5mA
Driving REFIN input only
VIN+ and VIN- to GNDI, T
A
= +25C
VOSADJ = 0 to 2.5V
Signal + offset w.r.t. GNDI
T
A
= +25 C
No missing codes guaranteed
CONDITIONS
k
4
5
R
REF
Reference Input Resistance
mV
5
REFOUT
Reference Output Load
Regulation
V
2.475
2.50
2.525
REFOUT
Reference Output Voltage
LSB
4
5.5
Input V
OS
Adjust Range
k
14
25
R
VOS
Input Resistance (Note 2)
ppm/C
150
TC
R
Input Resistance Temperature
Coefficient
LSB
-0.5
0.25
0.5
INL
Integral Nonlinearity (Note 1)
Bits
8
RES
Resolution
49
50
51
R
IN
Input Resistance
V
0.8
V
CM
Common-Mode Input Range
mVp-p
475
500
525
V
FSR
Full-Scale Input Range (Note 1)
LSB
-0.5
0.25
0.5
DNL
Differential Nonlinearity (Note 1)
Codes
None
Missing Codes
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ACCURACY
ANALOG INPUTS
V
OS
ADJUST CONTROL INPUT
REFERENCE INPUT AND OUTPUT
MAX106
5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
_______________________________________________________________________________________
3
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
A = V
CC
I = V
CC
D = +5.0V 5%, V
EE
= -5.0V 5%, V
CC
O = +3.0V to V
CC
D, REFIN connected to REFOUT, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25C.)
CLK+ and CLK- to CLKCOM, T
A
= +25C
CONDITIONS
ppm/C
150
TC
R
Input Resistance Temperature
Coefficient
48
50
52
R
CLK
Clock Input Resistance
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
(Note 10)
(Note 9)
VIN+ = VIN- = 0.1V
V
IH
= 2.4V
V
IL
= 0
dB
40
68
PSRR-
Negative Power-Supply
Rejection Ratio (Note 8)
dB
40
73
PSRR+
Positive Power-Supply Rejection
Ratio (Note 8)
dB
40
68
CMRR
Common-Mode Rejection Ratio
(Note 7)
W
5.25
P
DISS
Power Dissipation (Note 6)
Output Supply Current (Note 6)
mA
75
115
I
CC
O
mA
205
340
I
CC
D
Digital Supply Current
mA
-290
-210
I
EE
Negative Input Supply Current
mA
108
150
I
CCI
Positive Input Supply Current
mA
480
780
I
CCA
Positive Analog Supply Current
V
0.8
V
IL
Low-Level Input Voltage
V
2.0
V
IH
High-Level Input Voltage
V
-1.810
-1.620
V
OL
Digital Output Low Voltage
V
-1.025
-0.880
V
OH
Digital Output High Voltage
V
-1.475
V
IL
Digital Input Low Voltage
A
50
I
IH
High-Level Input Current
A
-1
1
I
IL
Low-Level Input Current
V
-1.165
V
IH
Digital Input High Voltage
CLOCK INPUTS
(Note 3)
TTL/CMOS CONTROL INPUTS
(DEMUXEN, DIVSELECT)
DEMUX RESET INPUT
(Note 4)
PECL DIGITAL OUTPUTS
(Note 5)
POWER REQUIREMENTS
MAX106
5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
4
_______________________________________________________________________________________
f
IN
= 600MHz
f
IN
= 500MHz
f
IN
= 125MHz
f
IN
= 300MHz
f
IN
= 600MHz
f
IN
= 600MHz
f
IN
= 125MHz
f
IN
= 300MHz
f
IN
= 125MHz
f
IN
= 300MHz
CONDITIONS
56.7
dB
57.4
SFDR
600
Spurious-Free Dynamic
Range
-67.5
-63.0
-67.5
THD
125
-56.5
-52.0
-56.5
THD
300
-56.1
dB
-57.0
THD
600
Total Harmonic Distortion
(Note 12)
47.4
44.2
47.4
SNR
125
47.1
43.8
47.1
SNR
300
46.8
V/V
1.1:1
VSWR
Analog Input VSWR
GHz
2.2
BW
-3dB
Analog Input Full-Power
Bandwidth
dB
46.8
SNR
600
Signal-to-Noise Ratio
(No Harmonics)
7.74
7.4
7.74
ENOB
125
7.65
Bits
7.63
ENOB
600
7.62
7.3
7.65
ENOB
300
Effective Number of Bits
(Note 11)
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
f
IN
= 125MHz
f
IN
= 300MHz
f
IN1
= 124MHz, f
IN2
= 126MHz,
at -7dB below full scale
f
IN
= 125MHz
f
IN
= 300MHz
63.0
69.9
SFDR
125
57.4
52.0
57.5
SFDR
300
dB
-61.8
IMD
Two-Tone Intermodulation
48.4
46.3
48.4
SINAD
125
47.8
69.9
dB
47.7
SINAD
600
Signal-to-Noise Ratio and
Distortion (Note 11)
47.6
45.7
47.8
SINAD
300
f
IN
= 600MHz
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
f
IN
= 600Hz
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
AC ELECTRICAL CHARACTERISTICS
(V
CC
A = V
CC
I = V
CC
D = +5.0V, V
EE
= -5.0V, V
CC
O = +3.3V, REFIN connected to REFOUT, f
S
= 600Msps, f
IN
at -1dBFS, T
A
= +25C,
unless otherwise noted.)
VOSADJ control input open
LSB
-1.5
0
1.5
V
OS
Transfer Curve Offset
ANALOG INPUT
DYNAMIC SPECIFICATIONS
MAX106
5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
_______________________________________________________________________________________
5
CONDITIONS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
Figure 17
Figure 17
Figure 15
Figure 15
Figure 4
Figure 17
ps
220
t
RDREADY
DREADY Rise Time
ps
360
t
FDATA
DATA Fall Time
ps
420
t
RDATA
DATA Rise Time
ps
-50
150
350
t
PD2
DREADY to DATA Propagation
Delay (Note 14)
ns
2.2
t
PD1
CLK to DREADY Propagation
Delay
ps
0
t
HD
Reset Input Data Hold Time
(Note 13)
ps
0
t
SU
Reset Input Data Setup Time
(Note 13)
ps
< 0.5
t
AJ
Aperture Jitter
ps
100
t
AD
Aperture Delay
DIV1, DIV2 modes
DIV1, DIV2 modes
20% to 80%, C
L
= 3pF
9.5
Clock
Cycles
8.5
t
PDA
Auxiliary Port Pipeline Delay
Clock
Cycles
7.5
t
PDP
Primary Port Pipeline Delay
ps
180
t
FDREADY
DREADY Fall Time
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
A = V
CC
I = V
CC
D = +5.0V, V
EE
= -5.0V, V
CC
O = +3.3V, REFIN connected to REFOUT, f
S
= 600Msps, f
IN
at -1dBFS, T
A
= +25C,
unless otherwise noted.)
Note 1:
Static linearity parameters are computed from a "best-fit" straight line through the code transition points. The full-scale
range (FSR) is defined as 256
slope of the line.
Note 2:
The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit
voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.
Note 3:
The clock input's termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings on
the CLK+ and CLK- inputs.
Note 4:
Input logic levels are measured with respect to the V
CC
O power-supply voltage.
Note 5:
All PECL digital outputs are loaded with 50
to V
CC
O - 2.0V. Measurements are made with respect to the V
CC
O power-
supply voltage.
Note 6:
The current in the V
CC
O power supply does not include the current in the digital output's emitter followers, which is a func-
tion of the load resistance and the V
TT
termination voltage.
Note 7:
Common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the
common-mode voltage, expressed in dB.
Note 8:
Measured with the positive supplies tied to the same potential, V
CC
A = V
CC
D = V
CC
I. V
CC
varies from +4.75V to +5.25V.
Note 9:
V
EE
varies from -5.25V to -4.75V.
Note 10:
Power-supply rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in power
supply voltage, expressed in dB.
Note 11:
Effective number of bits (ENOB) and signal-to-noise plus distortion (SINAD) are computed from a curve fit referenced to the
theoretical full-scale range.
7.5
Msps
600
f
MAX
Maximum Sample Rate
Figure 17
ns
0.75
t
PLW
Clock Pulse Width Low
Figure 17
ns
0.75
5
t
PWH
Clock Pulse Width High
TIMING CHARACTERISTICS
Figures 6, 7, 8
Figures 6, 7, 8
DIV4 mode
DIV4 mode
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