_______________General Description
The MAX1101 is a highly integrated IC designed pri-
marily for digitizing the output of a linear CCD array. It
provides the components required for all necessary
analog functions, including clamp circuitry for black-
level correction or correlated double sampling (CDS), a
three-input multiplexer (mux), and an 8-bit analog-to-
digital converter (ADC).
The MAX1101 operates with a sample rate up to 1MHz
and with a wide range of linear CCDs. The logic inter-
face is serial, and a single input sets the bidirectional
data line as either data in or data out, thus minimizing
the I/O pins required for communication.
Packaged in a 24-pin SO, the MAX1101 is available in
the commercial (0C to +70C) temperature range.
________________________Applications
Scanners
Fax Machines
Digital Copiers
CCD Imaging
____________________________Features
o
1.0 Million Pixels/sec Conversion Rate
o
Built-In Clamp Circuitry for Black-Level
Correction or Correlated Double Sampling
o
64-Step PGA, Programmable from Gain = -2 to -10
o
Auxiliary Mux Inputs for Added Versatility
o
Compatible with a Large Range of CCDs
o
8-Bit ADC Included
o
Space-Saving, 24-Pin SO Package
MAX1101
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
________________________________________________________________
Maxim Integrated Products
1
GND
V
DD
V
DD
0.1
F
0.1
F
0.1
F
24
22
23
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
GND
CLAMP
+5V DC (SUPPLY)
+5V DC (REFERENCE)
VIDSAMP
LOAD
DATA
SCLK
MODE
GND
REFBIAS
REF+
AIN2
REFGND
REF-
AIN1
GND
GND
GND
CCDIN
C
EXT
0.047
F
AUXILIARY
ANALOG INPUTS
CCD
ARRAY
7
11
1 2
12
MAX1101
P/
C/
STATE LOGIC
___________________________________________________Typical Operating Circuit
19-1166; Rev 0; 12/96
PART
MAX1101CWG
0C to +70C
TEMP. RANGE
PIN-PACKAGE
24 Wide SO
______________Ordering Information
Pin Configuration appears on last page.
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX1101
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
DD
= V
REFBIAS
= +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1F, C
EXT
= 47nF, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
DD
to GND ............................................................-0.3V to +12V
All Pins to GND...........................................-0.3V to (V
DD
+ 0.3V)
Current into Every Pin (except V
DD
) .................................20mA
Current into V
DD
...............................................................50mA
Continuous Power Dissipation (T
A
= +70C)
SO (derate 11.76mW/C above +70C) ......................941mW
Operating Temperature Range...............................0C to +70C
Storage Temperature Range .............................-65C to +150C
Lead Temperature (soldering, 10sec) .............................+300C
V
WHITE
=
(V
REF+
- V
REF-
) / G
PGA
nA
1
50
I
L(CCDIN)
Input Leakage (Note 2)
60
150
R
ON(BSS)
Black Sample Switch On-Resistance
% Gain
5
PGA Gain Error
V/V
0.125
Gain Adjust Step Size
Steps
64
Gain Adjust Resolution
V/V
-9.375
-9.875
-10.375
Maximum PGA Gain Setting
V/V
-1.9
-2
-2.1
Minimum PGA Gain Setting
V
0.25
V
WHITE
Maximum Peak CCD
Differential Signal Range
1.25
LSB
0.5
1
DNL
Differential Nonlinearity
Bits
8
N
Resolution
ns
10
t
AP
Aperture Delay
MHz
1
Input Full-Power Bandwidth
kHz
1
Minimum Sample Rate
MHz
0.67
1.2
f
s
Maximum Sample Rate
LSB
1
1.5
INL
Integral Nonlinearity
LSB
2.5
TUE
Total Unadjusted Error
%V/C
125
TCVOS
Zero-Scale Drift
%FS/C
0.016
TCFS
Full-Scale Drift
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Including black sample switch off-leakage
No-missing-codes guaranteed
G
PGA
= -10
G
PGA
= -2
V
IN
= 2.5Vp-p
(Note 1)
Best straight-line fit
CONDITIONS
CCD Interface Offset Voltage
V
OS(CCD)
V
VIDEO
= V
RESET
(Figure 4)
0
4
8
LSB
Input Voltage Range
V
IN
V
REF-
V
REF+
V
C
IN(ON)
Channel on
45
Input Capacitance (Note 1)
C
IN(OFF)
Channel off
10
pF
On-Resistance
R
ON
120
ANALOG-TO-DIGITAL CONVERTER
ANALOG INPUT--CCD INTERFACE
ANALOG INPUT--AUXILIARY INPUTS
MAX1101
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= V
REFBIAS
= +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1F, C
EXT
= 47nF, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
V
1.5
V
IL
Digital Input Voltage Low
V
3.5
V
IH
Digital Input Voltage High
mA
20
40
I
DD
Supply Current
dB
48
60
PSRR
PSRR, PGA and ADC
V
4.75
5
5.25
V
DD
Positive Supply-Voltage Range
V
0.49
0.50
0.51
V
REF-
Negative Reference Voltage
V
2.94
3.00
3.06
V
REF+
Positive Reference Voltage
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Internally generated, V
REFBIAS
= 5V
4.75V
V
DD
5.25V
Internally generated, V
REFBIAS
= 5V
CONDITIONS
Digital Input Leakage Current
I
IL
-10
10
A
Digital Output Voltage High
V
OH
I
SOURCE
= 4mA
V
DD
- 0.5
V
Digital Output Voltage Low
V
OL
I
SINK
= 4mA
0.5
V
Digital Output Leakage Current
I
OL
Output in high-impedance mode
-10
10
A
SCLK Frequency
f
SCLK
10
MHz
VIDSAMP Pulse Width
t
VS
500
ns
VIDSAMP to CLAMP Separation
t
VB
50
ns
LOAD Pulse Width
t
LD
50
ns
VIDSAMP Fall to SCLK Rise Time
t
VLS
MODE = 1
50
ns
VIDSAMP Fall to DATA
t
VLD
MODE = 1
60
ns
SCLK Rise to DATA
t
SD
60
ns
DATA Set-Up Time
t
DSU
20
ns
DATA Hold Time
t
DH
20
ns
LOAD Fall to SCLK Rise Time
t
LS
MODE = 0
50
ns
SCLK Rise to LOAD Rise Time
t
SL
MODE = 0
50
ns
MODE Setup Time
t
MSU
Same as bus-relinquish time
50
ns
CLAMP Pulse Width
t
BS
300
ns
CLAMP Fall to Video Update
t
BC
(Note 1)
20
ns
Digital Quiet Time (Note 3)
t
Q
around VIDSAMP falling edge
20
ns
SCLK Pulse Width
t
SPW
50
ns
Reset to CLAMP Separation
t
RB
(Note 2)
50
ns
Note 1:
Due to leakage in the PGA and ADC, operation at sample rates below 1ksps is not recommended, as
performance may degrade, particularly at high temperatures.
Note 2:
Production test equipment settling time prohibits leakage measurements below 1nA.
Lab equipment has shown the MAX1101 switch input leakage below 1pA at T
A
= +25C, and below 50pA at T
A
= +70C.
Note 3:
Not a test parameter. Recommended for optimal performance.
VIDSAMP to Reset Separation
t
VR
(Note 2)
50
ns
REFERENCE VOLTAGE INPUT
POWER SUPPLIES
DIGITAL INPUTS/OUTPUTS
DIGITAL TIMING SPECIFICATIONS
(t
r
r
, t
f
10ns, C
L
50pF, unless otherwise noted)
MAX1101
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
4
_______________________________________________________________________________________
______________________________________________________________Pin Description
NAME
FUNCTION
1, 3, 5, 7,
10, 16, 24
GND
Ground
2
CCDIN
CCD Input. Connect CCD through a series 0.047F capacitor (C
EXT
).
PIN
4
AIN1
Auxiliary Analog Input Channel 1
6
AIN2
Auxiliary Analog Input Channel 2
12
REF-
Lower Limit of Reference Span. Sets the zero-code voltage. Range is GND
REF-
REF+.
Nominally 0.5V.
11
REFGND
Reference Ground. Ground reference for all analog signals.
8, 9, 10
I.C.
Internally Connected. Do not connect to this pin.
18
SCLK
Serial Clock Input
17
MODE
Control Input. Set high, DATA is an output of the ADC. Set low, DATA enables programming of the
PGA and mux.
15, 23
V
DD
Power Supply, +5V. Bypass to ground very close to the device and connect the two pins together,
close to the MAX1101.
14
REFBIAS
Reference Power Supply. Connect to external +5.0V to set V
REF+
to +3.0V and V
REF-
to +0.5V.
13
REF+
Upper Limit of Reference Span. Sets the full-scale input. Voltage range is REF-
REF+
V
DD
.
Nominally 3.0V.
19
DATA
Data Input or Output, as controlled by MODE
20
LOAD
Control Input. Loads serial shift-register data to PGA and multiplexer registers when MODE = 0.
21
VIDSAMP
Control Input. Samples the video level and initiates the ADC conversion.
22
CLAMP
Control Input. Samples black level. Can be used for correlated double sampling.
_______________Detailed Description
Overview
The MAX1101 directly processes the pixel stream from
a monochrome CCD, and removes black level, offset,
and noise errors through an internal clamp circuit,
which can be used as a correlated double sampler
(CDS). It uses a 6-bit, programmable-gain amplifier
(PGA) to adjust gain. A three-input multiplexer (mux)
selects either the PGA output or two unassigned inputs
(AIN1, AIN2). The processed analog signal is digitized
by an 8-bit, half-flash analog-to-digital converter (ADC),
and output serially through the DATA pin.
Digital data is input and output through the bidirectional
serial pin (DATA) synchronously with the external serial
clock (SCLK). When MODE = 0, the mux channels and
the PGA gain can be programmed via DATA. With MODE
= 1 (high), ADC serial data is output through this pin.
PGA
GAIN
CLAMP
CIRCUIT
MUX
ADC
REGISTER
REGISTER
6
2
6
2
1
0
2
8
8
SERIAL
PORT
DATA
SCLK
LOAD
MODE
REFBIAS
REF+
REF-
REFGND
AIN2
AIN1
CLAMP
CCDIN
VIDSAMP
REGISTER
Figure 1. MAX1101 Functional Diagram
MAX1101
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
_______________________________________________________________________________________
5
Programmable-Gain Amplifier
The PGA amplifies the differential video signal from the
CCD (at CCDIN). Gain is settable with the 6-bit con-
trol word from -2 to -10 in 64 steps, in increments of
-0.125. The PGA also provides for periodic DC restora-
tion of the capacitively coupled input.
As shown in Figure 2, the switched-capacitor amplifier's
gain is set by the ratio C
I
/C
F
. The input is sampled on
the C
I
capacitors, which is a set of equal capacitors.
The 6-bit gain control word determines the number
of capacitors used. Thus the PGA gain is set from
-2 to -10.
A voltage equal to V
REF-
is applied to the PGA's nonin-
verting input. This offsets the PGA output to be within
the range of the ADC (V
REF-
to V
REF+
).
Clamp Circuit
As shown in Figure 2, the CCD output is connected to
the MAX1101 input (CCDIN) through an external
capacitor, which removes the potentially large DC
common-mode voltages from the input signal.
Whenever CLAMP is high, the CLAMP switch is closed
and C
EXT
is charged to V
REF+
. It can be actuated
either once per pixel (sampling reset level) or less fre-
quently (such as for restoring optical black level once
per line), as required by the application.
VIDSAMP controls the sampling of the video signal
and offset nulling of the PGA. To null out the offset,
VIDSAMP causes switches S1 and S1P to close, plac-
ing the amplifier in a unity-gain configuration, as shown
in Figure 3a. This configuration causes the amplifier's
offset voltage to be stored on CF. In the next portion of
the cycle, when VIDSAMP returns low, the S1 switches
are opened and S2 is closed (Figure 3b). This is the
standard inverting op-amp configuration. The only dif-
ference is that capacitors are used to set the gain, and
the amplifier's offset voltage has been stored on these
capacitors and is thus canceled. The amplifier's output
is [C
F
/C
I
] x V
VIDEO
+ V
REF-
. The CDS function is shown
in Figure 4.
ADC
The ADC uses a recycling half-flash conversion tech-
nique in which a 4-bit flash ADC section achieves an
8-bit result in two steps (Figure 5). Using 15 compara-
tors, the flash ADC compares the unknown input
voltage to the reference ladder (using REF+ and REF-)
and provides the upper four data bits.
An internal digital-to-analog converter (DAC) uses the
four most significant bits (MSBs) to generate the analog
result from the first flash conversion and a residue volt-
age that is the difference between the unknown voltage
Figure 2. PGA Functional Diagram
S1
S2
S1P
C
I
S2
S1
CLAMP
CF
C
EXT
0.047
F
REF-
REF-
REF+
REF+
TO
ADC
FROM
CCD
VIDSAMP
S1
S2
S1P
ON
ON
ON
OFF
OFF
OFF
* INTERNALLY GENERATED SIGNALS
*
*
*
REF-
C
F
C
I
REF+
REF-
V
OUT
= V
REF
- V
0S
C
I
C
F
REF-
V
REF
+
- V
VIDEO
(FROM DC
RESTORE)
Figure 3a. PGA Connection with VIDSAMP = Low
Figure 3b. PGA Connection with VIDSAMP = High
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