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General Description
The MAX1123 is a monolithic 10-bit, 210Msps analog-
to-digital converter (ADC) optimized for outstanding
dynamic performance at high IF frequencies up to
500MHz. The product operates with conversion rates of
up to 210Msps while consuming only 460mW.
At 210Msps and an input frequency of 100MHz, the
MAX1123 achieves a spurious-free dynamic range
(SFDR) of 74.5dBc. Its excellent signal-to-noise ratio
(SNR) of 57.4dB at 10MHz remains flat (within 1.5dB)
for input tones up to 500MHz. This makes the MAX1123
ideal for wideband applications such as digital predis-
tortion in cellular base-station transceiver systems.
The MAX1123 requires a single 1.8V supply. The ana-
log input is designed for either differential or single-
ended operation and can be AC- or DC-coupled. The
ADC also features a selectable on-chip divide-by-2
clock circuit, which allows the user to apply clock fre-
quencies as high as 420MHz. This helps to reduce the
phase noise of the input clock source. A differential
LVDS sampling clock is recommended for best perfor-
mance. The converter's digital outputs are LVDS com-
patible, and the data format can be selected to be
either two's complement or offset binary.
The MAX1123 is available in a 68-pin QFN with
exposed paddle (EP) and is specified over the industri-
al (-40C to +85C) temperature range.
For pin-compatible, lower and higher speed versions of
the MAX1123, refer to the MAX1122 (170Msps) and the
MAX1124 (250Msps) data sheets. For a higher speed,
pin-compatible 8-bit version of the MAX1123, refer to
the MAX1121 data sheet.
Applications
Wireless and Wired Broadband Communication
Cable-Head End Systems
Digital Predistortion Receivers
Communications Test Equipment
Radar and Satellite Subsystems Antenna Array
Processing
Features
210Msps Conversion Rate
SNR = 57.4dB/56dB at f
IN
= 100MHz/500MHz
SFDR = 74.5dBc/62.6dBc at f
IN
= 100MHz/500MHz
NPR = 53.6dB at f
NOTCH
= 28.8MHz
Single 1.8V Supply
460mW Power Dissipation at 210Msps
On-Chip Track-and-Hold and Internal Reference
On-Chip Selectable Divide-by-2 Clock Input
LVDS Digital Outputs with Data Clock Output
Evaluation Kit Available (Order MAX1124EVKIT)
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
________________________________________________________________
Maxim Integrated Products
1
58
59
60
61
62
54
55
56
57
63
38
39
40
41
42
43
44
45
46
47
AV
CC
AGND
AV
CC
TOP VIEW
AV
CC
OGND
OV
CC
ORP
ORN
D9P
D9N
D8P
D8N
52
53
D7P
D7N
AGND
AGND
AV
CC
CLKN
CLKP
AV
CC
AGND
OV
CC
OGND
N.C.
OV
CC
N.C.
N.C.
N.C.
D4P
D4N
OGND
OV
CC
DCLKP
DCLKN
OV
CC
D3P
D3N
D2P
35
36
37
D2N
D1P
D1N
AGND
INN
INP
AGND
AV
CC
AGND
AGND
AV
CC
AV
CC
AV
CC
AGND
REFADJ
REFIO
AGND
48
D5N
AV
CC
64
AGND
65
66
67
AGND
AGND
AV
CC
68
T/B
23
22
21
20
19
27
26
25
24
18
29
28
32
31
30
D0N
D0P
34
33
49
50
D6N
D5P
51
D6P
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
CLKDIV
17
MAX1123
EP
Pin Configuration
Ordering Information
19-3028; Rev 1; 2/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
PART
TEMP RANGE
PIN-PACKAGE
MAX1123EGK
-40
C to +85
C
68 QFN-EP*
*EP = Exposed paddle.
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AV
CC
to AGND ......................................................-0.3V to +2.1V
OV
CC
to OGND .....................................................-0.3V to +2.1V
AGND to OGND ....................................................-0.3V to +0.3V
Analog Inputs to AGND ...........................-0.3V to (AV
CC
+ 0.3V)
Digital Inputs to AGND.............................-0.3V to (AV
CC
+ 0.3V)
REF, REFADJ to AGND............................-0.3V to (AV
CC
+ 0.3V)
Digital Outputs to OGND .........................-0.3V to (OV
CC
+ 0.3V)
ESD on All Pins (Human Body Model).............................2000V
Continuous Power Dissipation (T
A
= +70C)
68-Pin QFN (derate 41.7mW/C above +70C) .........3333mW
Operating Temperature Range ...........................-40C to +85C
Junction Temperature ......................................................+150C
Storage Temperature Range .............................-60C to +150C
Lead Temperature (soldering, 10s) .................................+300C
Maximum Current into Any Pin............................................50mA
ELECTRICAL CHARACTERISTICS
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 210MHz, differential sine-wave clock input drive, 0.1F capacitor on REFIO,
internal reference, digital output pins differential R
L
= 100 1%, C
L
= 5pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. 25C guar-
anteed by production test, <25C guaranteed by design and characterization. Typical values are at T
A
= +25C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity
INL
(Note 1)
-2
0.4
+2
LSB
Differential Nonlinearity
DNL
No missing codes (Note 1)
-1.0
0.3
+1.5
LSB
T
A
+25C
-25
+25
Transfer Curve Offset
V
OS
(Note 1)
(Note 2)
-37
+37
LSB
Offset Temperature Drift
20
V/
C
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range
V
FS
(Note 1)
1100
1250
1375
mV
P-P
Full-Scale Range Temperature
Drift
130
ppm/
C
Common-Mode Input Range
V
CM
1.38
0.18
V
Input Capacitance
C
IN
3
pF
Differential Input Resistance
R
IN
3.00
4.3
6.25
k
Full-Power Analog Bandwidth
FPBW
Figure 8
600
MHz
REFERENCE (REFIO, REFADJ)
Reference Output Voltage
V
REFIO
1.18
1.24
1.30
V
Reference Temperature Drift
90
ppm/
C
REFADJ Input High Voltage
V
REFADJ
Used to disable the internal reference
AV
CC
-
0.3
V
SAMPLING CHARACTERISTICS
Maximum Sampling Rate
f
SAMPLE
210
MHz
Minimum Sampling Rate
f
SAMPLE
20
MHz
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 210MHz, differential sine-wave clock input drive, 0.1F capacitor on REFIO,
internal reference, digital output pins differential R
L
= 100 1%, C
L
= 5pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. 25C guar-
anteed by production test, <25C guaranteed by design and characterization. Typical values are at T
A
= +25C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Clock Duty Cycle
Set by clock management circuit
40 to 60
%
Aperture Delay
t
AD
350
ps
Aperture Jitter
t
AJ
0.21
ps
RMS
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude
(Note 2)
200
500
mV
P-P
Clock Input Common-Mode
Voltage Range
1.15
0.2
V
Clock Differential Input
Resistance
R
CLK
11
25%
k
Clock Differential Input
Capacitance
C
CLK
5
pF
DYNAMIC CHARACTERISTICS
(at -0.5dBFS)
f
IN
= 10MHz, T
A
+25
C
56
57.5
f
IN
= 100MHz, T
A
+25
C
55.5
57.1
f
IN
= 180MHz
57
Signal-to-Noise Ratio
SNR
f
IN
= 500MHz
56
dB
f
IN
= 10MHz, T
A
+25
C
55.5
57.4
f
IN
= 100MHz, T
A
+25
C
55
57
f
IN
= 180MHz
56.5
Signal-to-Noise
and Distortion
SINAD
f
IN
= 500MHz
55
dB
f
IN
= 10MHz, T
A
+25
C
63
77
f
IN
= 100MHz, T
A
+25
C
61
72
f
IN
= 180MHz
66.3
Spurious-Free
Dynamic Range
SFDR
f
IN
= 500MHz
62.5
dBc
f
IN
= 10MHz
-77
f
IN
= 100MHz
-72
f
IN
= 180MHz
-66.3
Worst Harmonics
(HD2 or HD3)
f
IN
= 500MHz
-62.5
dBc
IMD
100
f
IN1
= 99MHz at -7dBFS,
f
IN2
= 101MHz at -7dBFS
-75
Two-Tone Intermodulation
Distortion
IMD
500
f
IN1
= 498.5MHz at -7dBFS,
f
IN2
= 502.5MHz at -7dBFS
-58
dBc
LVDS DIGITAL OUTPUTS (D0P/ND9P/N, DCLKP/N)
Differential Output Voltage
|V
OD
|
250
400
mV
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 210MHz, differential sine-wave clock input drive, 0.1F capacitor on REFIO,
internal reference, digital output pins differential R
L
= 100 1%, C
L
= 5pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. 25C guar-
anteed by production test, <25C guaranteed by design and characterization. Typical values are at T
A
= +25C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Offset Voltage
OV
OS
1.125
1.310
V
LVCMOS DIGITAL INPUTS (CLKDIV,
T
/B)
Digital Input Voltage Low
V
IL
0.2 x
AV
CC
V
Digital Input Voltage High
V
IH
0.8 x
AV
CC
V
TIMING CHARACTERISTICS
CLK to Data Propagation Delay
t
PDL
Figure 4
1.5
ns
CLK to DCLK Propagation Delay
t
CPDL
Figure 4
3.01
ns
Data Valid to DCLK Rising Edge
t
CPDL
-
t
PDL
Figure 4 (Note 2)
1.23
1.51
1.84
ns
LVDS Output Rise-Time
t
RISE
20% to 80%, C
L
= 5pF
460
ps
LVDS Output Fall-Time
t
FALL
20% to 80%, C
L
= 5pF
460
ps
Output Data Pipeline Delay
t
LATENCY
8
Clock
cycles
POWER REQUIREMENTS
Analog Supply Voltage Range
AV
CC
1.7
1.8
1.9
V
Digital Supply Voltage Range
OV
CC
1.7
1.8
1.9
V
Analog Supply
I
AVCC
f
IN
= 100MHz
210
280
mA
Digital Supply Current
I
OVCC
f
IN
= 100MHz
45
75
mA
Analog Power Dissipation
P
DISS
f
IN
= 100MHz
460
640
mW
Offset
1.6
mV/V
Power-Supply Rejection Ratio
(Note 3)
PSRR
Gain
1.9
%FS/V
Note 1: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-
scale range is defined as 1023 x slope of the line.
Note 2: Parameter guaranteed by design and characterization; T
A
= T
MIN
to T
MAX
.
Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
_______________________________________________________________________________________
5
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
0
40
60
80
20
100
120
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1123 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
f
SAMPLE
= 210.0057MHz
f
IN
= 11.5103MHz
A
IN
= -0.542dBFS
SNR = 57.5dB
SFDR = 79.5dBc
HD2 = -82dBc
HD3 = -86.3dBc
HD2
HD3
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
0
40
60
80
20
100
120
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1123 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
f
SAMPLE
= 210.0057MHz
f
IN
= 60.1152MHz
A
IN
= -0.4885dBFS
SNR = 57.4dB
SFDR = 76.2dBc
HD2 = -83.9dBc
HD3 = -76.2dBc
HD2
HD3
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
0
40
60
80
20
100
120
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1123 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
f
SAMPLE
= 210.0057MHz
f
IN
= 183.5242MHz
A
IN
= -0.5245dBFS
SNR = 57dB
SFDR = 66.6dBc
HD2 = -82.9dBc
HD3 = -66.9dBc
HD2
HD3
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
0
40
60
80
20
100
120
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1123 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
f
SAMPLE
= 210.0057MHz
f
IN
= 500.0196MHz
A
IN
= -0.4975dBFS
SNR = 55.9dB
SFDR = 62.5dBc
HD2 = -69.5dBc
HD3 = -62.5dBc
HD3
HD2
SNR vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 210.0057MHz, A
IN
= -0.5dBFS)
MAX1123 toc05
f
IN
(MHz)
SNR (dB)
400
300
200
100
54
55
57
56
58
59
50
51
52
53
0
500
SFDR vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 210.0057MHz, A
IN
= -0.5dBFS)
MAX1123 toc06
f
IN
(MHz)
SFDR (dBc)
400
300
200
100
45
50
65
55
60
35
40
70
75
85
80
30
0
500
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 210.0057MHz, A
IN
= -0.5dBFS)
MAX1123 toc07
f
IN
(MHz)
HD2/HD3 (dBc)
400
300
200
100
-90
-80
-70
-60
-50
-100
0
500
HD2
HD3
27
37
32
52
47
42
57
62
-28
-16
-12
-24
-20
-8
-4
0
SNR vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 210.0057MHz, f
IN
= 60.0126MHz)
MAX1123 toc08
ANALOG INPUT AMPLITUDE (dBFS)
SNR (dB)
50
60
55
70
65
75
80
-28
-16
-12
-24
-20
-8
-4
0
SFDR vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 210.0057MHz, f
IN
= 60.0126MHz)
MAX1123 toc09
ANALOG INPUT AMPLITUDE (dBFS)
SFDR (dBc)
Typical Operating Characteristics
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 210.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins
differential R
L
= 100, T
A
= +25C.)
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