General Description
The MAX1418 is a 5V, high-speed, high-performance
analog-to-digital converter (ADC) featuring a fully differ-
ential wideband track-and-hold (T/H) and a 15-bit con-
verter core. The MAX1418 is optimized for multichannel,
multimode receivers, which require the ADC to meet very
stringent dynamic performance requirements. With a
noise floor of -78.2dBFS, the MAX1418 allows for the
design of receivers with superior sensitivity.
The MAX1418 achieves two-tone, spurious-free dynamic
range (SFDR) of -85dBc for input tones of 69MHz and
71MHz. Its excellent signal-to-noise ratio (SNR) of 73.6dB
and single-tone SFDR performance (SFDR1/SFDR2) of
88dBc/92dBc at f
IN
= 70MHz and a sampling rate of
65Msps make this part ideal for high-performance digital
receivers.
The MAX1418 operates from an analog 5V and a digital
3V supply, features a 2.56V
P-P
full-scale input range,
and allows for a sampling speed of up to 65Msps. The
input T/H operates with a -1dB full-power bandwidth of
260MHz.
The MAX1418 features parallel, CMOS-compatible out-
puts in two's-complement format. To enable the interface
with a wide range of logic devices, this ADC provides a
separate output driver power-supply range of 2.3V to
3.5V. The MAX1418 is manufactured in an 8mm x 8mm,
56-pin QFN package with exposed paddle (EP) for low
thermal resistance, and is specified for the extended
industrial (-40C to +85C) temperature range.
Note that IF parts MAX1418, MAX1428, and MAX1430
(see Pin-Compatible Higher/Lower Speed Versions
Selection table) are recommended for applications that
require high dynamic performance for input frequen-
cies greater than f
CLK
/3. Unlike its baseband counter-
part MAX1419, the MAX1418 is optimized for input
frequencies greater than f
CLK
/3.
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Single- and Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
Power Amplifier Linearity Correction
Antenna Array Processing
Features
o 65Msps Minimum Sampling Rate
o -78.2dBFS Noise Floor
o Excellent Dynamic Performance
73.6dB SNR at f
IN
= 70MHz and A
IN
= -2dBFS
88dBc/92dBc Single-Tone SFDR1/SFDR2 at
f
IN
= 70MHz and A
IN
= -2dBFS
-85dB Multitone SFDR at f
IN1
= 69MHz
and f
IN2
= 71MHz
o Less than 0.25ps Sampling Jitter
o Fully Differential Analog Input Voltage Range of
2.56V
P-P
o CMOS-Compatible Two's-Complement Data Output
o Separate Data Valid Clock and Overrange Outputs
o Flexible-Input Clock Buffer
o EV Kit Available for MAX1418
(Order MAX1427EVKIT)
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
________________________________________________________________ Maxim Integrated Products
1
Ordering Information
19-3022; Rev 0; 10/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Pin Configuration appears at end of data sheet.
PART
TEMP RANGE
PIN-PACKAGE
MAX1418ETN
-40C to +85C
56 QFN-EP*
Pin-Compatible Higher/Lower
Speed Versions Selection
PART
SPEED GRADE
(Msps)
TARGET
APPLICATION
MAX1418
65
IF
MAX1419
65
Baseband
MAX1427
80
Baseband
MAX1428*
80
IF
MAX1429*
100
Baseband
MAX1430*
100
IF
*Future product--contact factory for availability.
*EP = Exposed paddle.
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 65MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25C, unless otherwise noted.
+25C guaranteed by production test, <+25C guaranteed by design and char-
acterization.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AV
CC
, DV
CC
, DRV
CC
to GND.................................. -0.3V to +6V
INP, INN, CLKP, CLKN, CM to GND........-0.3V to (AV
CC
+ 0.3V)
D0D14, DAV, DOR to GND..................-0.3V to (DRV
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70C)
56-Pin QFN (derate 47.6mW/C above +70C) ......3809.5mW
Operating Temperature Range ...........................-40C to +85C
Thermal Resistance
J
A
...................................................21C/W
Junction Temperature ......................................................+150C
Storage Temperature Range .............................-60C to +150C
Lead Temperature (soldering, 10s) .................................+300
C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
15
Bits
Integral Nonlinearity
INL
f
IN
= 15MHz
1.5
LSB
Differential Nonlinearity
DNL
f
IN
= 70MHz, no missing codes guaranteed
0.4
LSB
Offset Error
-12
+12
mV
Gain Error
-4
+4
%FS
ANALOG INPUT (INP, INN)
D i ffer enti al Inp ut V ol tag e Rang e
V
DIFF
Fully differential inputs drive, V
DIFF
= V
INP
- V
INN
2.56
V
P-P
Common-Mode Input Voltage
V
CM
Self-biased
4.17
V
Differential Input Resistance
R
IN
1
15%
k
Differential Input Capacitance
C
IN
1
pF
Full-Power Analog Bandwidth
FPBW
-1dB
-1dB rolloff for a full-scale input
260
MHz
CONVERSION RATE
Maximum Clock Frequency
f
CLK
65
MHz
Minimum Clock Frequency
f
CLK
20
MHz
Aperture Jitter
t
AJ
0.21
ps
RMS
CLOCK INPUT (CLKP, CLKN)
Full-Scale Differential Input
Voltage
V
DIFFCLK
Fully differential input drive, V
CLKP
- V
CLKN
0.5 to
3.0
V
Common-Mode Input Voltage
V
CM
Self-biased
2.4
V
Differential Input Resistance
R
INCLK
2
15%
k
Differential Input Capacitance
C
INCLK
1
pF
DYNAMIC CHARACTERISTICS
Thermal + Quantization
Noise Floor
NF
Analog input <-35dBFS
-78.2
dBFS
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 65MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25C, unless otherwise noted.
+25C guaranteed by production test, <+25C guaranteed by design and char-
acterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
IN
= 5MHz at -2dBFS
75
f
IN
= 15MHz at -2dBFS
75
f
IN
= 35MHz at -2dBFS
74.8
f
IN
= 70MHz at -2dBFS
72
73.6
Signal-to-Noise Ratio (Note 1)
SNR
f
IN
= 170MHz at -6dBFS
68.5
dB
f
IN
= 5MHz at -2dBFS
74.8
f
IN
= 15MHz at -2dBFS
74.8
f
IN
= 35MHz at -2dBFS
74.4
f
IN
= 70MHz at -2dBFS
71
73.3
Signal-to-Noise and Distortion
(Note 2)
SINAD
f
IN
= 170MHz at -6dBFS
64.4
dB
f
IN
= 5MHz at -2dBFS
90
f
IN
= 15MHz at -2dBFS
90
f
IN
= 35MHz at -2dBFS
88
f
IN
= 70MHz at -2dBFS
78
88
Spurious-Free Dynamic Range
(HD2 and HD3)
(Note 2)
SFDR1
f
IN
= 170MHz at -6dBFS
67.5
dBc
f
IN
= 5MHz at -2dBFS
95
f
IN
= 15MHz at -2dBFS
95
f
IN
= 35MHz at -2dBFS
93
f
IN
= 70MHz at -2dBFS
84.5
92
Spurious-Free Dynamic Range
(HD4 and Higher)
(Note 2)
SFDR2
f
IN
= 170MHz at -6dBFS
82
dBc
Two-Tone Intermodulation
Distortion
TTIMD
f
IN1
= 69MHz at -8dBFS;
f
IN2
= 71MHz at -8dBFS
-85
dBc
Two-Tone Spurious-Free
Dynamic Range
SFDR
TT
f
IN1
= 69MHz at -12dBFS < f
IN1
< -100dBFS;
f
IN2
= 71MHz at -12dBFS < f
IN2
< -100dBFS
(Note 2)
-100
dBFS
DIGITAL OUTPUTS (D0D14, DAV, DOR)
Digital Output-Voltage Low
V
OL
0.5
V
Digital Output-Voltage High
V
OH
DV
CC
-
0.5
V
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 2.5V) Figure 4
CLKP/CLKN Duty Cycle
Duty cycle
50
5
%
Effective Aperture Delay
t
AD
230
ps
Output Data Delay
t
DAT
(Note 3)
3.0
4.5
7.5
ns
Data Valid Delay
t
DAV
(Note 3)
5.3
6.5
8.7
ns
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
4
_______________________________________________________________________________________
Note 1: Dynamic performance is based on a 32,768-point data record with a sampling frequency of f
SAMPLE
= 65.0117120MHz, an
input frequency of f
IN
= f
SAMPLE
x (35283/32768) = 70.001472MHz, and a frequency bin size of 1984Hz. Close-in (f
IN
23.8kHz) and low-frequency (DC to 47.6kHz) bins are excluded from the spectrum analysis.
Note 2: Apply the same voltage levels to DV
CC
and DRV
CC
Note 3: Guaranteed by design and characterization.
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 65MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25C, unless otherwise noted.
+25C guaranteed by production test, <+25C guaranteed by design and char-
acterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Pipeline Latency
t
LATENCY
3
Clock
cycles
CLKP Rising Edge to DATA
Not Valid
t
DNV
(Note 3)
2.6
3.8
5.7
ns
CLKP Rising Edge to DATA
Valid (Guaranteed)
t
DGV
(Note 3)
3.4
5.2
8.6
ns
DATA Setup Time
(Before DAV Rising Edge)
t
SETUP
(Note 3)
t
CLKP
-
0.5
t
CLKP
+ 1.3
t
CLKP
+ 2.4
ns
DATA Hold Time
(After DAV Rising Edge)
t
HOLD
(Note 3)
t
CLKN
-
3.6
t
CLKN
-
2.8
t
CLKN
-
2.0
ns
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 3.3V) Figure 4
CLKP/CLKN Duty Cycle
Duty cycle
50
5
%
Effective Aperture Delay
t
AD
230
ps
Output Data Delay
t
DAT
(Note 3)
2.8
4.1
6.5
ns
Data Valid Delay
t
DAV
(Note 3)
5.3
6.3
8.6
ns
Pipeline Latency
t
LATENCY
3
Clock
cycles
CLKP Rising Edge to
DATA Not Valid
t
DNV
(Note 3)
2.5
3.4
5.2
ns
CLKP Rising Edge to
DATA Valid (Guaranteed)
t
DGV
(Note 3)
3.2
4.4
7.4
ns
DATA Setup Time
(Before DAV Rising Edge)
t
SETUP
(Note 3)
t
CLKP
+ 0.2
t
CLKP
+ 1.7
t
CLKP
+ 2.8
ns
DATA Hold Time
(After DAV Rising Edge)
t
HOLD
(Note 3)
t
CLKN
-
3.5
t
CLKN
-
2.7
t
CLKN
-
2.0
ns
POWER REQUIREMENTS
Analog Supply Voltage Range
AV
CC
5 3%
V
Digital Supply Voltage Range
DV
CC
(Note 2)
2.5 to 3.5
V
Output Supply Voltage Range
DRV
CC
(Note 2)
2.5 to 3.5
V
Analog Supply Current
I
AVCC
382
447
mA
D i g i tal + Outp ut S up p l y C ur r ent
I
DVCC
+
DRV
CC
f
CLK
= 65MHz, C
LOAD
= 5pF
35.5
42
mA
Analog Power Dissipation
PDISS
2000
mW
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
_______________________________________________________________________________________
5
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1418 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
30
25
20
15
10
5
-100
-80
-60
-40
-20
0
-120
0
f
CLK
= 65.0117MHz
f
IN
= 15.0010MHz
A
IN
= -1.97dBFS
SNR = 75dB
SFDR1 = 87.8dBc
SFDR2 = 94.7dBc
HD2 = -96.9dBc
HD3 = -87.8dBc
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1418 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
30
25
20
15
10
5
-100
-80
-60
-40
-20
0
-120
0
f
CLK
= 65.0117MHz
f
IN
= 34.9997MHz
A
IN
= -1.98dBFS
SNR = 74.8dB
SFDR1 = 86.55dBc
SFDR2 = 93.5dBc
HD2 = -92.6dBc
HD3 = -86.4dBc
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1418 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
30
25
20
15
10
5
-100
-80
-60
-40
-20
0
-120
0
f
CLK
= 65.0117MHz
f
IN
= 70.0015MHz
A
IN
= -2.02dBFS
SNR = 73.7dB
SFDR1 = 85.6dBc
SFDR2 = 91.2dBc
HD2 = -85.6dBc
HD3 = -96.9dBc
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1418 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
30
25
20
15
10
5
-100
-80
-60
-40
-20
0
-120
0
f
CLK
= 65.0117MHz
f
IN
= 169.9992MHz
A
IN
= -6.01dBFS
SNR = 68.5dBc
SFDR1 = 67.5dBc
SFDR2 = 82.1dBc
HD2 = -67.5dBc
HD3 = -73.6dBc
68
70
69
73
72
71
75
76
74
77
5
65
85
25
45
105 125 145 165 185
SNR vs. ANALOG INPUT FREQUENCY
(f
CLK
= 65.0117MHz, A
IN
= -2dBFS)
MAX1418toc05
f
IN
(MHz)
SNR (dB)
55
65
85
75
95
105
5
65
85
25
45
105 125 145 165 185
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 65.0117MHz, A
IN
= -2dBFS)
MAX1418toc06
f
IN
(MHz)
SFDR1/SFDR2 (dBc)
SFDR2
SFDR1
Typical Operating Characteristics
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, INP and INN driven differentially with a -2dBFS amplitude, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 65MHz, T
A
= 25C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
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