e
m

r
y

All data sheets are subject to change without notice

(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com

32 Megabit (4M x 8-Bit)

29F0408

Flash Memory

11.08.02 Rev 2

EATURES

· Single 5.0 V supply
· Excellent Single Event Effect

- SEL

: > 60 MeV/mg/cm

- SEU

: = 37 MeV/mg/cm

- SEU saturated cross section: 2E-6 cm

/bit

· Organization:

- Memory cell array: (4M + 128k) bit x 8bit
- Data register: (512 + 16) bit x 8bit

· Automatic program and erase

- Page program: (512 + 16) Byte
- Block erase: (8K + 256) Byte
- Status register

· 528-Byte page read operation

- Random access: 10 µ s (max)
- Serial page access: 50 ns (min)

· Fast write cycle time

- Program time: 250 µ s (typ)
- Block erase time: 2 ms (typ)

· Command/address/data multiplexed I/O port
· Hardware data protection

- Program/erase lockout during power transitions

· Reliable CMOS floating-gate technology

- Endurance: 1,000,000 program/erase cycles
- Data retention: 10 years

· Command register operation
· 44 pin flat package

ESCRIPTION

Maxwell Technologies' 29F0408 high-performance flash mem-
ory. The 29F0408 is a 4M (4,194,304) x 8-bit NAND Flash
Memory with a spare 128K (131,072) x 8-bit. A program oper-
ation programs the 528-byte page in 250 µ s and an erase
operation can be performed in 2 ms on an 8K-byte block. Data
within a page can be read out at 50 ns cycle time per byte.
The on-chip write controller automates all program and erase
functions, including pulse repetition, where required, and inter-
nal verify and margining of data. Even write-intensive systems
can take advantage of the 29F0408's extended reliability of
1,000,000 program/erase cycles by providing either ECC
(Error Correction Code) or real time mapping-out algorithm.
These algorithms have been implemented in many mass stor-
age applications. The spare 16 bytes of a page combined with
the other 512 bytes can be utilized by system-level ECC. The
29F0408 is an optimum solution for large non-volatile storage
applications such as solid state storage, digital voice recorder,
digital still camera and other portable applications requiring
nonvolatility.

Maxwell Technologies' patented R

-P

® packaging technol-

ogy incorporates radiation shielding in the microcircuit pack-
age. Capable of surviving in space environments, the
29F0408 is ideal for satellite, spacecraft, and space probe
missions. It is available with packaging and screening up to
Class S.

Logic Diagram

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

ABLE

1. P

INOUT

ESCRIPTION

YMBOL

ESCRIPTION

Command Latch

Enable (CLE)

The CLE input controls the path activation for commands sent to the command register.
When active high, commands are latched into the command register through the I/O ports
on the rising edge of the WE signal.

Address Latch Enable

(ALE)

The ALE input controls the path activation for address and input data to the internal
address/data register. Addresses are latched on the rising edge or WE with ALE high, and
input data is latched when ALE is low.

Chip Enable (CE)

The CE input is the device selection control. When CE goes high during a read operation,
the device is returned to standby mode. However, when the device is in the busy state dur-
ing program or erase, CE high is ignored, and does not return the device to standby mode.

Write Enable (WE)

The WE input controls writes to the I/O port. Commands, address and data are latched on
the rising edge of the WE pulse.

Read Enable (RE)

The RE inputs is the serial data-out control, and when active drives the data onto the I/O
bus. Data is valid t

REA

after the falling edge of RE which also increments the internal column

address counter by one.

Spare Area Enable

(SE)

The SE input controls the spare area selection when SE is high, the device is deselected
the spare area during Read1, Sequential data input and page Program.

18-21,

24-27

I/O Port: I/O0 ~ I/O7

The I/O pins are used to input command, address and data, and to output data during read
operations. The I/O pins float to High-Z when the chip is deselected or when the outputs are
disabled.

Write Protect (WP)

The WP pin provides inadvertent write/erase protection during power transitions. The inter-
nal high voltage generator is reset when the WP pin is active low.

Read/Busy (R/B)

The R/B output indicates the status of the device operation. When low, it indicates that a
program, erase or random read operation is in process and returns to high state upon com-
pletion. It is an open drain output and does not float to High-Z condition when the chip is
deselected or when outputs are disabled.

6-17, 28-39

Not Connected

1, 22

Ground

Supply Voltage

Output Buffer Voltage

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

ABLE

2. 29F0408 A

BSOLUTE

AXIMUM

ATINGS 1,2

1. Minimum DC voltage is -0.3 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 30 ns.

Maximum DC voltage on input/output pins is V

+ 0.3 V which, during transitions, may overshoot to V

+ 2.0 V for periods <

20 ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be

restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect reliability.

ARAMETER

YMBOL

NIT

Voltage on any pin relative to V

-0.6

7.0

Operating Temperature

BIAS

-40

125

Storage temperature

STG

-65

150

Short circuit output current

ABLE

3. 29F0408 R

ECOMMENDED

PERATING

ONDITIONS

OLTAGE REFERENCE TO

GND, T

= -40

125

ARAMETER

YMBOL

NIT

Supply voltage

4.5

5.0

5.5

Supply voltage

Input High Voltage

2.4

±0.5

Input Low Voltage

-0.3

0.8

ABLE

4. D

ELTA

IMITS

ARAMTER

ONDITION

±10%

ABLE

5. 29F0408 AC T

EST

ONDITION

= 5 V ± 10%, T

= -40

125

UNLESS OTHERWISE NOTED

)

ARAMETER

NIT

Input pulse levels

0.4

2.6

Input rise times

5.0

Input and output timing levels

0.8

2.0

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

ABLE

6. 29F0408 DC

AND

PERATING

HARACTERISTICS

= 5 V ± 10%, T

= -40

125

UNLESS OTHERWISE NOTED

)

ARAMETER

YMBOL

EST

ONDITIONS

UBGROUPS

NIT

Operating current

Sequential

read

CC1

CYCLE

= 50 ns

CE = V

OUT

= 0 mA

1, 2, 3

Program

CC2

1, 2, 3

Erase

CC3

1, 2, 3

Stand-by-current (TTL)

SB1

CE = V

, WP = SE = 0V/V

1, 2, 3

Stand-by current (CMOS)

SB2

CE = V

- 0.2, WP = SE =

0V/V

1, 2, 3

100

Input leakage current

= 0 to 5.5 V

1, 2, 3

-10

Output leakage current

OUT

= 0 to 5.5 V

1, 2, 3

-10

Input high voltage, all inputs

1, 2, 3

2.0

Input low voltage, all inputs

1, 2, 3

0.8

Output high voltage level

= -400 µ A

1, 2, 3

2.4

Output low voltage level

= 2.1 mA

1, 2, 3

0.4

Outuput low current (R/B)

(R/B)

= 0.4 V

1, 2, 3

ABLE

7. 29F0408 C

APACITANCE 1

1. Capacitance Guarenteed by design.

ARAMETER

YMBOL

EST

ONDITION

NIT

Input/Output capacitance

I/O

= 0V

Input capacitance

= 0V

ABLE

8. 29F0408 M

ODE

ELECTION

CLE

ALE

ODE

Read Mode

Command Input

Address Input (3
Clock)

Write Mode

Command Input

Address Input (3
Clock)

L/H

Data Input

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

L/H

Sequential Read & Data Output

L/H

During Read (Busy)

L/H

During Program (Busy)

During Erase (Busy)

Write Protect

0V/V

Stand-by

1. When SE is high, spare area is deselected.

2. X can be V

or V

3. WP should be biased to CMOS high or CMOS low for standby.

ABLE

9. 29F0408 P

ROGRAM

RASE

HARACTERISTICS

= 5 V ± 10%, T

=-40

+125C,

UNLESS OTHERWISE NOTED

)

ARAMETER

YMBOL

NIT

Program time

PROG

0.25

1.5

Number of partial program cycles in the same page

cycles

Block erase time

BERS

ABLE

8. 29F0408 M

ODE

ELECTION

CLE

ALE

ODE

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

ABLE

10. 29F0408 AC T

IMING

HARACTERISTICS FOR

OMMAND

DDRESS

ATA

NPUT

= 5 V ± 10%, T

=-40

+125 C,

UNLESS OTHERWISE NOTED

)

ARAMETER

YMBOL

UBGROUPS

NIT

CLE set-up time

CLS

9, 10, 11

CLE hold time

CLH

9, 10, 11

CE setup time

9, 10, 11

CE hold time

9, 10, 11

WE pulse width

9, 10, 11

ALE setup time

ALS

9, 10, 11

ALE hold time

ALH

9, 10, 11

Data setup time

9, 10, 11

Data hold time

9, 10, 11

Write cycle time

9, 10, 11

WE high hold time

9, 10, 11

ABLE

11. 29F0408 AC C

HARACTERISTICS FOR

PERATION

= 5 V ± 10%, T

= -40

+125

UNLESS OTHERWISE NOTED

)

ARAMETER

YMBOL

UBGROUPS

NIT

Data transfer from cell to register

9, 10, 11

µ s

ALE to RE delay (read ID)

AR1

9, 10, 11

150

ALE to RE delay (read cycle)

AR2

9, 10, 11

CE to RE delay (ID read)

9, 10, 11

100

Ready to RE low

9, 10, 11

RE pulse width

9, 10, 11

WE high to busy

9, 10, 11

100

Read cycle time

9, 10, 11

RE access time

REA

9, 10, 11

RE high to output Hi-Z

RHZ

9, 10, 11

CE high to output Hi-Z

CHZ

9, 10, 11

RE high hold time

REH

9, 10, 11

Output Hi-Z to RE low

9, 10, 11

Last RE high to busy (at sequential read)

9, 10, 11

100

CE high to ready (in case of interception by CE at
read)

CRY

9, 10, 11

50 + tr (R/B)

CE high hold time (at the last serial read)

CEH

9, 10, 11

100

RE low to status output

RSTO

9, 10, 11

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

NAND F

LASH

ECHNICAL

OTES

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by the
manufacturer. Typically, an invalid block will contain a single bad bit. The information regarding the invalid block(s) is
called as the invalid block information. The invalid block information is written to the 1st or the 2nd page of the invalid
block(s) with 00h data. Devices with invalid block(s) have the same quality level as devices with all valid blocks and
have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s)
because it is isolated from the bit line and the common source line by a select transistor. The system design must be
able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaran-
teed to be a valid block.

Identifying Invalid Block(s)

All device locations are erased (FFh) except locations where the invalid block information is written prior to shipping.
Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it
has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid

CE low to status output

CSTO

9, 10, 11

RE high to WE low

RHW

9, 10, 11

WE high to RE low

WHR

9, 10, 11

RE access time (read ID)

READID

9, 10, 11

Device resetting time (read/program/erase/after
erase suspend)

RST

9, 10, 11

5/10/500

µ s

1. Not Tested

2. If CE goes high within 30 ns after the rising edge of the last RE, R/B will not return to V

3. The time to Ready depends on the value of the pull-up resistor tied to R/B pin.

4. To break the sequential read cycle, CE must be held high for longer than t

CEH

ABLE

12. 29F0408 V

ALID

LOCK 1,2

1. The device may include valid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to

access these invalid blocks for program and erase. During its lifetime of 10 years and/or 1 million program/erase cycles, the
minimum number of valid blocks are guaranteed though its initial number could be reduced. (Refer to following technical note)

2. The 1st block, which is placed on the 00h block address, is guaranteed to be a valid block.

ARAMETER

YMBOL

NIT

Valid Block Number

502

508

512

Blocks

ABLE

11. 29F0408 AC C

HARACTERISTICS FOR

PERATION

= 5 V ± 10%, T

= -40

+125

UNLESS OTHERWISE NOTED

)

ARAMETER

YMBOL

UBGROUPS

NIT

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

block information and create the invalid block table via the following suggested flow chart (Figure 1). Any intentional
erasure of the original block information is prohibited.

IGURE

1. F

LOW CHART TO CREATE INVALID BLOCK TABLE

Error in write or read operation

Over its lifetime, the additional invalid blocks may occur. Through the tight process control and intensive testing, addi-
tional block failure rate is minimized which is projected below 0.1% until 1 million program/erase cycles. Refer to the
qualification report for the actual data. The following possible failure modes should be considered to implement a
highly reliable system. In the case of status read failure after erase or program, block replacement should be done. To
improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error
be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those
reclaimed blocks.

ECC: Error Correcting Code

Hamming Code, etc.

Example. 1-bit correction and 2-bit detection

AILURE

ODE

ETECTION AND

OUNTERMEASURE

Write

Erase failure

Status read after erase

Block replacement

Program failure

Status read after program

Block replacement

Read back (verify after program)

Block replacement or

ECC correction

Read

Single bit failure

Verify ECC

ECC correction

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

Pointer Operation:

The 29F0408 has three modes to set the destination of the pointer. The pointer is set to "A" area by the "00h" com-
mand, to "B" area by the "01h" command, and to "C" area by the "50h" command. The Destination Pointer Table shows
the destination of the pointer, and the block diagram shows the diagram of its operation.

ABLE

12. D

ESTINATION OF

OINTER

ABLE

IGURE

6. B

LOCK

IAGRAM OF

OINTER

PERATION

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

IGURE

7. E

XAMPLES OF

ROGRAMMING WITH

UCCESSIVE

OINTER

PERATION

ABLE

13. P

OINT

TATUS

FTER

ACH

PERATION

System Interface Using CE don't-care.

For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below.
The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets
more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-acti-
vating CE during the data-loading and reading would provide significant savings in power consumption.

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

IGURE

8. P

ROGRAM

PERATION WITH

CE D

ARE

IGURE

9. R

EAD

PERATION

ITH

CE D

ARE

Timing requirements: If CE is is exerted high
during data-loading, tCS must be minimum
10ns and tWC must be increased accord-
ingly.

Timing requirements: If CE is is exerted high
during sequentialdata-reading, the falling edge
of CE to valid data(tCEA) must be kept greater
than 45ns.

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

DEVICE OPERATION

PAGE READ

Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing
00h to the command register along with three address cycles. Once the command is latched, it does not
need to be written for the following page read operation. Three types of operations are available : random
read, serial page read and sequential read.

The random read mode is enabled when the page address is changed. The 528 bytes of data within the
selected page are transferred to the data registers in less than 10 ms(t

). The CPU can detect the comple-

tion of this data transfer(t

) by analyzing the output of R/B pin. Once the data in a page is loaded into the

registers, they may be read out in 50 ns cycle time by sequentially pulsing RE with CE staying low. High to
low transitions of the RE clock output the data starting from the selected column address up to the last col-
umn address(column 511 or 527 depending on state of SE pin).

After the data of last column address is clocked out, the next page is automatically selected for sequential
read.

Waiting 10 µ s again allows for reading of the selected page. The sequential read operation is terminated by
bringing CE high. The way the Read1 and Read2 commands work is like a pointer set to either the main
area or the spare area. The spare area of bytes 512 to 527 may be selectively accessed by writing the
Read2 command with SE pin low. Toggling SE during operation is prohibited. Addresses A0 to A3 set the
starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted,
the page address is automatically incremented for sequential read as in Read1 operation and spare sixteen
bytes of each page may be sequentially read. The Read1 command (00h/01h) is needed to move the
pointer back to the main area. Figures 22 thru 25 show typical sequence and timings for each read opera-
tion.

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programming of
a byte or consecutive bytes up to 528, in a single page program cycle. The number of consecutive partial
page programming operation within the same page without an intervening erase operation must not exceed
ten. The addressing may be done in any random order in a block. A page program cycle consists of a serial
data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-
volatile programming period where the loaded data is programmed into the appropriate cell. Serial data
loading can be started from 2nd half array. About the pointer operation, please refer to the attached technical
notes.The serial data loading period begins by inputting the Serial Data Input command (80H), followed by
the three cycle address input and then serial data loading. The bytes other than those to be programmed do
not need to be loaded.

The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without
perviously entering the serial data will not initiate the programming process. The internal write controller
automatically executes the algorithms and timings necessary for program and verify, thereby freeing the
CPU for other tasks. Once the program process starts, the Read Status Register command may be entered,
with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by
monitoring the R/B output, or the Status bit (I/O6) of the Status Register. Only the Read Status command
and Reset command are valid while programming is in progress. When the Page Program is complete, the
Write Status Bit (I/O0) may be checked (Figure 26). The internal write verify detects only errors for "1"s that
are not successfully programmed to "0"s. The command register remains in Read Status command mode
until another valid command is written to the command register.

IGURE

26. P

ROGRAM

& R

EAD

TATUS OPERATION

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

BLOCK ERASE

The Erase operation can erase on a block (8K Byte) basis. Block address loading is accomplished in two
cycles initiated by an Erase Setup command (60h). Only address A13 to A21 is valid while A9 to A12 is
ignored. The addresses of the block to be erased to FFh. The Erase Confirm command (D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by
execution ensures that memory contents are not accidentally erased due to external noise conditions. At the
rising edge of WE after the erase confirm command input, the internal write controller handles erase and
erase-verify. When the erase operation is completed, the Write Status Bit (I/O0) may be checked. Figure 27
details the sequence.

IGURE

27. B

LOCK

RASE

PERATION

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is
complete, and whether the program or erase operation completed successfully. After writing 70h command
to the command register, a read cycle outputs the contents of the Status Register to the I/O pins on the fall-
ing edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of
each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not
need to be toggled for updated status. Refer to table 14 for specific Status Register definitions. The com-
mand register remains in Status Read mode until further commands are issued to it. Therefore, if the status
register is read during a random read cycle, a read command (00h or 50h) should be given before sequential
page read cycle.

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

ABLE

14. R

EAD

TATUS

EGISTER

EFINITION

READ ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed
by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device
code (E3h) respectively. The command register remains in Read ID mode until further commands are issued
to it. Figure 28 shows the operation sequence.

IGURE

28. R

EAD

ID O

PERATION

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in
Busy state during random read, program or erase modes, the reset operation will abort these operation. The
contents of memory cells being altered are no longer valid, as the data will be partially programmed or
erased. Internal address registers are cleared to "0"s and data registers to "1"s. The command register is
cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high.
Refer to table 15 for device status after reset operation. If the device is already in reset state a new reset
command will not be accepted to by the command register. The R/B pin transitions to low for t

RST

after the

Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 29 below.

IGURE

29. RESET O

PERATION

ABLE

15. D

EVICE

TATUS

DATA PROTECTION

The device is designed to offer protection from any involuntary program/erase during power-transitions. An
internal voltage detector disables all functions whenever V

is below about 2V. WP pin provides hardware

protection and is recommended to be kept at V

during power-up and power-down as shown in Figure 30.

The two step command sequence for program/erase provides additional software protection.

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

IGURE

30. AC W

AVEFORMS FOR

OWER

RANSITION

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page pro-
gram, erase and random read completion. The R/B pin is normally high but transitions to low after program
or erase command is written to the command register or random read is begin after address loading. It
returns to high when the internal controller has finished the operation. The pin is an open-drain driver
thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper
operation and the value may be calculated by following equation.

All data sheets are subject to change without notice

32 Megabit (4M x 8-Bit) Flash Memory

29F0408

11.08.02 Rev 2

Important Notice:

These data sheets are created using the chip manufacturer's published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.

Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech-
nologies. Maxwell Technologies' liability shall be limited to replacement of defective parts.

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 29F0408RPFE