e
m

r
y

All data sheets are subject to change without notice

(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

EATURES

· 512k x 8-bit CMOS architecture
· R

-P

® technology hardened against natural space radi-

ation

· Total dose hardness:

- > 100 krad (Si), depending upon space mission

· Single event effect:

- SEL

: > 68 MeV/mg/cm

- SEU

: < 3MeV/mg/cm

- SEU saturated cross section: 6E-9 cm

/bit

· Package:

-36 pin R

-P

® flat pack

· Fast propagation time:

-20, 25, 30 ns maximum access time

· Single 5V + 10% power supply
· Low power dissipation:

- Standby: 60mA (TTL); 10mA (CMOS)
- Operating: 180 mA (20 ns); 170 mA (25 ns); 160 mA (30

ns)

· TTL compatible inputs and outputs
· Fully static operation

- No clock or refresh required

· Three state outputs

ESCRIPTION

Maxwell Technologies' 32C408B high-speed 4 Megabit SRAM
microcircuit features a greater than 100 krad (Si) total dose
tolerance, depending upon space mission. Using R

-P

packaging technology, the 32C408B realizes higher density,
higher performance and lower power consumption, and is well
suited for high-speed system application. Its fully static design
eliminates the need for external clocks, while the CMOS cir-
cuitry reduces power consumption and provides higher reli-
ability. The 32C408B is equipped with eight common input/
output lines, chip select and output enable, allowing for
greater system flexibility and eliminating bus contention.

Maxwell Technologies' patented R

-P

packaging technol-

ogy incorporates radiation shielding in the microcircuit pack-
age. In a GEO orbit, R

-P

can provides true greater than

100 krad (Si) total radiation dose tolerance; dependent upon
space mission. The patented radiation-hardened R

-P

technology incorporates radiation shielding in the microcircuit
package. It eliminates the need for box shielding while provid-
ing the required radiation shielding for a lifetime in orbit or a
space mission. This product is available with packaging and
screening up to Class S.

A18

I/O1

I/O2

Vcc

Vss

I/O3

I/O4

A17

A16

A15

I/O8

I/O7

Vss

Vcc

A14

A13

A12

A11

A10

I/O5

I/O6

ROW

DECODER

INPUT

DATA

CONTROL

MEMORY MATRIX

1024 ROWS x 4096 COLUMNS

COLUMN I/O

COLUMN DECODER

A13

DQ0

DQ7

DQ0

DQ7

A14

A15

A16

A17

A18

A12

A11

A10

32C408B

Logic Diagram

e
m

r
y

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

ABLE

1. 32C408B A

BSOLUTE

AXIMUM

ATINGS

ARAMETER

YMBOL

NIT

Voltage on any pin relative to V

, V

OUT

-0.5

+0.5

Voltage on V

supply relative to V

-0.5

7.0

Power Dissipation

1.0

Storage Temperature

-65

+150

Operating Temperature

-55

+125

ABLE

2. 32C408B R

ECOMMENDED

PERATING

ONDITIONS

ARAMETER

YMBOL

NIT

Supply Voltage

4.5

5.5

Ground

Input High Voltage

1. V

(max) = V

+ 2.0V ac(pulse width < 10ns) for I < 20mA.

2.2

+0.5

Input Low Voltage

2. V

(min) = -2.0V ac(pulse width < 10ns) for I < 20mA.

-0.5

0.8

Thermal Impedance

0.63

°C/W

ABLE

3. 32C408B DC E

LECTRICAL

HARACTERISTICS

=5V +/- 10%, T

= -55

+1`25C, U

NLESS

TERWISE

PECIFIED

ARAMETER

ONDITION

YMBOL

UBGROUPS

NIT

Input Leakage Current

= V

to V

1, 2, 3

-2

µ A

Output Leakage Current

CS=V

or OE=V

or WE=V

OUT

to V

1, 2, 3

-2

µ A

Output Low Voltage

= 8mA

1, 2, 3

0.4

Output High Voltage

= -4mA

1, 2, 3

2.4

Average Operating Cur-
rent

-20
-25
-30

Min cycle, 100% Duty, CS=V

OUT

=0mA, V

= V

or V

1, 2, 3

--
--
--

180
170
160

Standby Power Supply
Current

CS = V

1, 2, 3

f = 0MHz, CS > V

- 02V, V

- 0.2V or V

< 0.2V

SB1

1, 2, 3

Input Capacitance

1. Guaranteed by Design

= 0V, f = 1MHz, T

= 25 °C.

1, 2, 3

Output Capacitance

I/O

= 0V

I/O

1, 2, 3

e
m

r
y

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

ABLE

4. 32C408B AC C

HARACTERISTICS

FOR

EAD

YCLE

=5V +/- 10%, T

= -55

+1`25C, U

NLESS

TERWISE

PECIFIED

ARAMETER

YMBOL

UBGROUPS

NIT

Read Cycle Time

-20
-25
-30

9, 10, 11

20
25
30

--
--
--

Address Access Time

-20
-25
-30

9, 10, 11

--
--
--

20
25
30

Chip Select Access Time

-20
-25
-30

9, 10, 11

--
--
--

20
25
30

Output Enable to Output Valid

-20
-25
-30

9, 10, 11

--
--
--

10
12
14

Chip Select to Output in Low-Z

-20
-25
-30

9, 10, 11

--
--
--

3
3
3

--
--
--

Output Enable to Output in Low-Z

-20
-25
-30

OLZ

9, 10, 11

--
--
--

0
0
0

--
--
--

Chip Deselect to Output in High-Z

-20
-25
-30

9, 10, 11

--
--
--

5
6
8

--
--
--

Output Disable to Output in High-Z

-20
-25
-30

OHZ

9, 10, 11

--
--
--

5
6
8

--
--
--

Output Hold from Address Change

-20
-25
-30

9, 10, 11

3
5
5

--
--
--

Chip Select to Power Up Time

-20
-25
-30

9, 10, 11

--
--
--

0
0
0

--
--
--

Chip Select to Power Down Time

-20
-25
-30

9, 10, 11

--
--
--

10
15
20

--
--
--

e
m

r
y

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

ABLE

5. 32408B F

UNCTIONAL

ESCRIPTION

1. X = don't care.

ODE

I/O P

UPPLY

URRENT

Not Select

High-Z

, I

SB1

Output Disable

High-Z

Read

OUT

Write

ABLE

6. 32C408B AC C

HARACTERISTICS

FOR

RITE

YCLE

=5V +/- 10%, T

= -55

+1`25C, U

NLESS

TERWISE

PECIFIED

ARAMETER

YMBOL

UBGROUPS

NIT

Write Cycle Time

-20
-25
-30

9, 10, 11

20
25
30

--
--
--

Chip Select to End of Write

-20
-25
-30

9, 10, 11

14
15
17

--
--
--

Address Setup Time

-20
-25
-30

9, 10, 11

0
0
0

--
--
--

Address Valid to End of Write

-20
-25
-30

9, 10, 11

14
15
17

--
--
--

Write Pulse Width (OE High)

-20
-25
-30

9, 10, 11

14
15
17

--
--
--

Write Recovery Time

-20
-25
-30

9, 10, 11

0
0
0

--
--
--

Write to Output in High-Z

-20
-25
-30

WHZ

9, 10, 11

--
--
--

5
5
6

--
--
--

e
m

r
y

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

IGURE

1. T

IMING

AVEFORM

RITE

YCLE

(1) (OE C

LOCK

)

Write Pulse Width(OE Low)

-20
-25
-30

WP1

9, 10, 11

--
--
--

20
25
30

--
--
--

Data to Write Time Overlap

-20
-25
-30

9, 10, 11

10
11

--
--
--

End Write to Output Low-Z 1

-20
-25
-30

tOW

9, 10, 11

--
--
--

6
7
8

--
--
--

Data Hold from Write Time

-20
-25
-30

9, 10, 11

0
0
0

--
--
--

ABLE

6. 32C408B AC C

HARACTERISTICS

FOR

RITE

YCLE

=5V +/- 10%, T

= -55

+1`25C, U

NLESS

TERWISE

PECIFIED

ARAMETER

YMBOL

UBGROUPS

NIT

e
m

r
y

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

IGURE

2. T

IMING

AVEFORM

RITE

YCLE

(OE L

IXED

)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and

WE going low: A write ends at the earliest transition among CS going high or WE going high. t

is measured from beginning

of write to end of write.

3. t

is measured from the later of CS going low to end of write.

4. t

is measured from the address valid to the beginning of write.

5. t

is measured from the end of write to the address change. TWR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write

cycle.

8. IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.

9. D

OUT

is the read data of the new address.

10.When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

IGURE

3. T

IMING

AVEFORM

EAD

YCLE(1)

DDRESS

ONTROLLED

, CS = OE = V

, WE = V

)

e
m

r
y

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

IGURE

4. T

IMING

AVEFORM

EAD

YCLE(2)

(WE = V

)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. t

and t

OHZ

are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V

levels.

4. At any given temperature and voltage condition, t

HZ(max)

is less than t

LZ(min)

both for a given device and from device to device.

5. Transition is measured +200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS = V

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention is necessary during read and

write cycle.

IGURE

5. SRAM H

EAVY

ROSS

ECTION

e
m

r
y

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

F36-01

Note: All dimensions in inches

36 P

LAT

-P

® P

ACKAGE

YMBOL

IMENSION

0.122

0.135

0.148

0.015

0.017

0.019

0.008

0.010

0.012

0.930

0.940

0.638

0.645

0.652

0.690

0.560

0.565

0.005

0.040

0.050 BSC

0.390

0.400

0.410

0.088

0.098

0.108

0.005

0.032

e
m

r
y

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

Important Notice:

These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.

Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech-
nologies. Maxwell Technologies' liability shall be limited to replacement of defective parts.

e
m

r
y

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

Product Ordering Options

Model Number

Feature

Option Details

32C408B

-XX

Access Time

Screening Flow

Package

Radiation Feature

Base Product
Nomenclature

20 = 20 ns
25 = 25 ns
30 = 30 ns

Monolithic
S = Maxwell Class S
B = Maxwell Class B
E = Engineering (testing @ +25°C)
I = Industrial (testing @ -55°C,
+25°C, +125°C)

F = Flat Pack

RP = R

-P

® package

CMOS 512kword x 8-bit Static
RAM

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 32C408BRPFI-25

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 32C408BRPFI-25