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(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com

4 Megabit (512K x 8-Bit)

33LV408

CMOS SRAM

04.02.04 REV 2

EATURES

· R

-P

Technology radiation-hardened against natural

space radiation

· 524,288 x 8 bit organization

Total dose hardness:

- > 100 krad (Si), depending upon space mission

· Excellent Single Event Effect

- SEL

: > 101 MeV/mg/cm

- SEU

: = 3 MeV/mg/cm

- SEU saturated cross section: 6E-9 cm

/bit

· Package:

- 32-Pin R

-P

® flat pack

· Fast access time:

- 20, 25, 30 ns maximum times available

· Single 3.3V + 10% power supply
· Fully static operation

- No clock or refresh required

· Three state outputs
· TTL compatible inputs and outputs
· Low power:

- Standby: 60 mA (TTL); 10 mA (CMOS)

- Operation: 150 mA (20 ns); 140 mA (25 ns);

130 mA (30 ns)

ESCRIPTION

Maxwell Technologies' 33LV408 high-density 4 Megabit
SRAM microcircuit features a greater than 100 krad (Si) total
dose tolerance, depending upon space mission. Using Max-
well's radiation-hardened R

-P

® packaging technology, the

33LV408 realizes a high density, high performance, and low
power consumption. Its fully static design eliminates the need
for external clocks, while the CMOS circuitry reduces power
consumption and provides higher reliability. The 33LV408 is
equipped with eight common input/output lines, chip select
and output enable, allowing for greater system flexibility and
eliminating bus contention. The 33LV408 features the same
advanced 512K x 8-bit SRAM, high-speed, and low-power
demand as the commercial counterpart.

Maxwell Technologies' patented R

-P

® packaging technol-

ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R

-P

® provides greater than 100

krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.

Logic Diagram

33LV408

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4 Megabit (512K x 8-Bit) CMOS SRAM

33LV408

04.02.04 REV 2

ABLE

1. P

INOUT

ESCRIPTION

YMBOL

ESCRIPTION

12-5, 27, 26, 23, 25, 4,

28, 3, 31, 2, 30, 1

A0-A18

Address Inputs

Write Enable

Chip Select

Output Enable

13-15, 17-21

I/O 1-I/O 8

Data Inputs/Outputs

Power

Ground

ABLE

2. 33LV408 A

BSOLUTE

AXIMUM

ATINGS

ARAMETER

YMBOL

NIT

Voltage on V

supply relative to V

-0.5

7.0

Voltage on any pin relative to V

, V

OUT

-0.5

+0.5

Power Dissipation

1.0

Storage Temperature

-65

+150

Operating Temperature

-55

+125

ABLE

3. D

ELTA

IMITS

ARAMETER

ARIATION

±10% of stated vaule in Table 6

SB1

±10% of stated vaule in Table 6

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4 Megabit (512K x 8-Bit) CMOS SRAM

33LV408

04.02.04 REV 2

ABLE

4. 33LV408 R

ECOMMENDED

PERATING

ONDITIONS

= 3.3 + 10%, T

= -55

+125

UNLESS

OTHERWISE

NOTED

)

ARAMETER

YMBOL

NIT

Supply Voltage

3.0

3.6

Ground

Input High Voltage

1. V

(max) = V

+2.0V ac (pulse width < 10 ns) for I < 20 mA

2.2

+0.3

Input Low Voltage

2. V

(min) = -2.0V ac(pulse width < 10 ns) for I < 20 mA

-0.3

0.8

Thermal Impedance

1.21

°C/W

Weight

Grams

ABLE

5. 33LV408 C

APACITANCE

(f = 1.0 MH

, V

= 3.3 V, T

= 25

ARAMETER

YMBOL

EST

ONDITIONS

NITS

Input Capacitance

CS1 - CS4,
OE, WE
I/O0-7, I/O8-15, I/O16-23, I/O24-31

1. Guaranteed by design.

= 0 V

Input / Output Capacitance

OUT

I/O

= 0 V

ABLE

6. 33LV408 DC E

LECTRICAL

HARACTERISTICS

= 3.3V + 10%, T

= -55

+125

UNLESS

OTHERWISE

SPECIFIED

)

ARAMETER

YMBOL

ONDITION

UBGROUPS

NIT

Input Leakage Current

= V

to V

1, 2, 3

-2

µ A

Output Leakage Current

CS=V

or OE=V

or WE=V

OUT

to V

1, 2, 3

-2

µ A

Output Low Voltage

= 8mA

1, 2, 3

0.4

Output High Voltage

= -4mA

1, 2, 3

2.4

Operating Current

-20
-25
-30

Min cycle, 100% Duty, CS=V

, I

OUT

=0mA,

= V

or V

1, 2, 3

--
--
--

150
140
130

Standby Power Supply
Current

CS = V

, Min Cycle

1, 2, 3

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4 Megabit (512K x 8-Bit) CMOS SRAM

33LV408

04.02.04 REV 2

Standby Power Supply
Current - CMOS

SB1

CS > V

- 0.2V; V

> V

- 0.2V

or V

< 0.2V

1, 2, 3

Input Capacitance

= 0V, f = 1MHz, T

= 25 °C

1, 2, 3

Output Capacitance

I/O

= 0V

1, 2, 3

1. Guaranteed by design.

ABLE

7. 33LV408 AC O

PERATING

ONDITIONS

AND

HARACTERISTICS

= 3.3 + 10%, T

= -55

+125

UNLESS

OTHERWISE

NOTED

)

ARAMETER

NITS

Input Pulse Level

0.0

3.0

Output Timing Measurement Reference Level

1.5

Input Rise/Fall Time

3.0

Input Timing Measurement Reference Level

1.5

ABLE

8. 33LV408 AC C

HARACTERISTICS

FOR

EAD

YCLE

= 3.3V + 10%, T

= -55

+125

UNLESS

OTHERWISE

SPECIFIED

)

ARAMETER

YMBOL

UBGROUPS

NIT

Read Cycle Time

-20
-25
-30

9, 10, 11

20
25
30

--
--
--

Address Access Time

-20
-25
-30

9, 10, 11

--
--
--

20
25
30

Chip Select Access Time

-20
-25
-30

9, 10, 11

--
--
--

20
25
30

Output Enable to Output Valid

-20
-25
-30

9, 10, 11

--
--
--

10
12
14

Chip Enable to Output in Low-Z

-20
-25
-30

9, 10, 11

--
--
--

3
3
3

--
--
--

ABLE

6. 33LV408 DC E

LECTRICAL

HARACTERISTICS

= 3.3V + 10%, T

= -55

+125

UNLESS

OTHERWISE

SPECIFIED

)

ARAMETER

YMBOL

ONDITION

UBGROUPS

NIT

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4 Megabit (512K x 8-Bit) CMOS SRAM

33LV408

04.02.04 REV 2

Output Enable to Output in Low-Z

-20
-25
-30

OLZ

9, 10, 11

--
--
--

0
0
0

--
--
--

Chip Deselect to Output in High-Z

-20
-25
-30

9, 10, 11

--
--
--

5
6
8

--
--
--

Output Disable to Output in High-Z

-20
-25
-30

OHZ

9, 10, 11

--
--
--

5
6
8

--
--
--

Output Hold from Address Change

-20
-25
-30

9, 10, 11

3
5
6

--
--
--

Chip Select to Power Up Time

-20
-25
-30

9, 10, 11

--
--
--

0
0
0

--
--
--

Chip Select to Power Down Time

-20
-25
-30

9, 10, 11

--
--
--

10
15
20

--
--
--

ABLE

9. 33LV408 F

UNCTIONAL

ESCRIPTION

ODE

I/O P

UPPLY

URRENT

1. X = don't care.

Not Select

High-Z

, I

SB1

Output Disable

High-Z

Read

OUT

Write

ABLE

8. 33LV408 AC C

HARACTERISTICS

FOR

EAD

YCLE

= 3.3V + 10%, T

= -55

+125

UNLESS

OTHERWISE

SPECIFIED

)

ARAMETER

YMBOL

UBGROUPS

NIT

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4 Megabit (512K x 8-Bit) CMOS SRAM

33LV408

04.02.04 REV 2

ABLE

10. 33LV408 AC C

HARACTERISTICS

FOR

RITE

YCLE

= 3.3V + 10%, T

= -55

+125

UNLESS

OTHERWISE

SPECIFIED

)

ARAMETER

YMBOL

UBGROUPS

NIT

Write Cycle Time

-20
-25
-30

9, 10, 11

20
25
30

--
--
--

Chip Select to End of Write

-20
-25
-30

9, 10, 11

14
15
17

--
--
--

Address Setup Time

-20
-25
-30

9, 10, 11

0
0
0

--
--
--

Address Valid to End of Write

-20
-25
-30

9, 10, 11

14
15
17

--
--
--

Write Pulse Width (OE High)

-20
-25
-30

9, 10, 11

14
15
17

--
--
--

Write Recovery Time

-20
-25
-30

9, 10, 11

0
0
0

--
--
--

Write to Output in High-Z

-20
-25
-30

WHZ

9, 10, 11

--
--
--

5
5
6

--
--
--

Write Pulse Width (OE Low)

-20
-25
-30

WP1

9, 10, 11

--
--
--

20
25
30

--
--
--

Data to Write Time Overlap

-20
-25
-30

9, 10, 11

--
--
--

End Write to Output Low-Z

-20
-25
-30

9, 10, 11

--
--
--

6
7
8

--
--
--

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4 Megabit (512K x 8-Bit) CMOS SRAM

33LV408

04.02.04 REV 2

IGURE

1: T

IMING

AVEFORM

EAD

YCLE

(1)

IGURE

2: T

IMING

AVEFORM

EAD

YCLE

(2)

Read Cycle Notes:
1.

WE is high for read cycle.

All read cycle timing is referenced form the last valid address to the first transition address.

and t

OHZ

are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V

levels.

At any given temperature and voltage condition, t

HZ(max)

is less than t

LZ(min)

both for a given device and from device to device.

Transition is measured + 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

Device is continuously selected with CS = V

IL.

Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention condition is necessary during read and write cycle.

Data Hold from Write Time

-20
-25
-30

9, 10, 11

0
0
0

--
--
--

ABLE

10. 33LV408 AC C

HARACTERISTICS

FOR

RITE

YCLE

= 3.3V + 10%, T

= -55

+125

UNLESS

OTHERWISE

SPECIFIED

)

ARAMETER

YMBOL

UBGROUPS

NIT

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4 Megabit (512K x 8-Bit) CMOS SRAM

33LV408

04.02.04 REV 2

IGURE

5: T

IMING

AVEFORM

RITE

YCLE

(3)

RITE

YCLE

OTE

All write cycle timing is referenced from the last valid address to the first transition address.

A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and

WE going low: A write ends at the earliest transition among CS going high and WE going high. t

is measured from begin-

ning of write to the end of write.

is measured from the later of CS going low to end of write.

is measured from the address valid to the beginning of write.

is measured form the end of write to the address change. TWR applied in case a write ends as CS, or WR going high.

If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite
phase of the output must not be applied because bus contention can occur.

For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.

IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.

OUT

is the read data of the new address.

10.

When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should
not be applied.

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4 Megabit (512K x 8-Bit) CMOS SRAM

33LV408

04.02.04 REV 2

Note: All dimensions in inches

32 P

-P

® F

LAT

ACKAGE

YMBOL

IMENSION

0.122

0.135

0.155

0.015

0.017

0.019

0.008

0.010

0.012

0.930

0.940

0.635

0.645

0.655

0.690

0.550

0.565

0.040

0.050 BSC

0.390

0.400

0.410

0.088

0.098

.108

0.082

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4 Megabit (512K x 8-Bit) CMOS SRAM

33LV408

04.02.04 REV 2

Important Notice:

These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.

Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech-
nologies. Maxwell Technologies' liability shall be limited to replacement of defective parts.

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4 Megabit (512K x 8-Bit) CMOS SRAM

33LV408

04.02.04 REV 2

Product Ordering Options

Model Number

Feature

Option Details

33LV408

-XX

Access Time

Screening Flow

Package

Radiation Feature

Base Product
Nomenclature

20 = 20 ns
25 = 25 ns
30 = 30 ns

Monolithic
S = Maxwell Class S
B = Maxwell Class B
I = Industrial (testing @ -55°C,
+25°C, +125°C)
E = Engineering (testing @ +25°C)

F = Flat Pack

RP = R

-P

® package

4 Megabit CMOS SRAM

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 33LV408RPFE-20

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 33LV408RPFE-20