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16-Bit, 20 KHz A/D Converter

01.17.05 R

5102ALP

EATURES

· Monolithic CMOS A/D converters

- Inherent sampling architecture
- 2-channel input multiplexer
- Flexible serial output port

· Conversion time

- 5102A: 40 µ s

· Linearity error: ±0.001% FS

- Guaranteed no missing codes

· Self-calibration maintains accuracy

- Over time and temperature

· Fully latchup protected

ESCRIPTION

Maxwell Technologies' 5102ALPRP is a 16-bit mono-
lithic CMOS analog-to-digital converter capable of 20
kHz throughput. On-chip self-calibration achieves nonlin-
earity of ±0.001% of FS and guarantees 16-bit no miss-
ing codes over the entire specified temperature range.
Offset and full-scale errors are minimized during the cali-
bration cycle, eliminating the need for external trimming.

The 5102ALP each consist of a 2-channel input multi-
plexer, DAC, conversion and calibration microcontroller,
clock generator, comparator, and serial communications
port. The inherent sampling architecture of the device
eliminates the need for an external track and hold ampli-
fier.

Maxwell Technologies' patented R

-P

® packaging

technology incorporates radiation shielding in the micro-
circuit package. It eliminates the need for box shielding
while improving the TID performance in most space
environments. This product is available with screening
up to Maxwell Technologies self-defined Class K.

Clock

Generator

Control

Calibration

SRAM

Microcontroller

16-Bit charge

Redistribution

DAC

Comparator

CLKIN

XOUT

REFBUF

VREF

AIN1

AIN2

CH1/2

AGND

VA+

VA-

DGND

VD-

VD+

SCLK

TEST

SCKMOD

OUTMOD

HOLD

SLEEP

RST

STBY

CODE

BP/UP

CRS/FIN

TRK1

TRK2

SSH/SDL

SDATA

+VDIG

DGND

-VDIG

RST

CLKIN

XOUT

STBY

DGND

+VDIG

TRK1

TRK2

CRS/FIN

SSH/SDL

HOLD

CH1/2

SCLK

+LPTBIT

-VDIG

DGND

+VDIG

+VAN

AGND

-VANLOG

-LPTV

+LPTV

SDATA

CODE

BP/UP

OUTMOD

AIN1

VREF

REFBUF

AGND

-VANLOG

AIN2

+VANLOG

LPTSTATUS

SCKMOD

SLEEP

-VANLOG

AGND

+VANLOG

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5102ALP

16-Bit, 20 KHz A/D Converter

ABLE

1. 5102ALP A

BSOLUTE

AXIMUM

ATINGS

(AGND, DGND = 0V,

ALL

VOLTAGES

WITH

RESPECT

GROUND

)

ARAMETER

YMBOL

NIT

DC Power Supplies:

Positive Digital
Negative Digital
Positive Analog
Negative Analog

1. In addition, VD+ must not be greater than (VA+) 0.3V.

VD+

VD-

VA+

VA-

-0.3

0.3

-0.3

0.3

6.0

-6.0

6.0

-6.0

Input Current, Any Pin Except Supplies

2. Transient currents of up to 100 mA will not cause SCR latchup.

±10

Analog Input Voltage (AIN and V

REF

pins)

INA

(VA-) -0.3

(VA+) 0.3

Digital Input Voltage

IND

-0.3

(VA+) 0.3

Ambient Operating Temperature

-15

Storage Temperature

STG

-65

150

ABLE

2. 5102ALP R

ECOMMENDED

PERATING

ONDITIONS

(AGND, DGND = 0V,

ALL

VOLTAGES

WITH

RESPECT

GROUND

)

ARAMETER

YMBOL

NIT

DC Power Supplies:

Positive Digital
Negative Digital
Positive Analog
Negative Analog

VD+

VD-

VA+

VA-

4.5

-4.5

4.5

-4.5

5.0

-5.0

5.0

-5.0

VA+

-5.5

5.5

-5.5

Analog Reference Voltage

VREF

2.5

4.5

(VA+) -0.5

Analog Input Voltage

Unipolar
Bipolar

1. The 5102ALPRP can accept input voltage up to the analog supplies (VA+ and VA-). They will produce an output of all 1s for

inputs above V

REF

and all 0s for inputs below AGND in unipolar mode and -V

REF

in bipolar mode, with binary coding (CODE =

low).

AIN

AGND

-V

REF

--
--

REF

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5102ALP

16-Bit, 20 KHz A/D Converter

ABLE

3. A

NALOG

HARACTERISTICS

= T

MIN

MAX

; VA+, VD+ = 5V; VA-, VD- = -5V; V

REF

= 4.5V; F

ULL

-S

CALE

NPUT

INEWAVE

, 200 H

; CLKIN = 1.6 MH

; f

= 20

;

IPOLAR

ODE

;

FRN M

ODE

; AIN1

AND

AIN2

TIED

TOGETHER

EACH

CHANNEL

TESTED

SEPARATELY

; A

NALOG

OURCE

MPEDANCE

= 50 W

WITH

1000

AGND

UNLESS

OTHERWISE

SPECIFIED

)

ARAMETER

YMBOL

NIT

Accuracy

Resolution

RES

Bits

Full Scale Error

Drift

FSE

--
--

±1
±2

±5

LSB

DLSB

Unipolar Offset

Drift

VOFF

--
--

±1
±2

±5

LSB

DLSB

Bipolar Offset

Drift

BOFF

--
--

±2
±2

±5

LSB

DLSB

Bipolar Negative Full Scale Error

Drift

BNFSE

--
--

±2
±2

±5

LSB

DLSB

Integral Nonlinearity

INL

±3

LSB

Differential Nonlinearity

DNL

±1

LSB

Dynamic Performance (Bipolar Mode)

Peak Harmonic or Spurious Noise

100

Total Harmonic Distortion

0.002

Signal-to-Noise Ratio

2, 4

0 dB Input
-60 dB Input

90
30

--
--

Noise

Unipolar Mode
Bipolar Mode

--
--

35
70

--
--

µ Vrms

Analog Input

Aperture Time

Aperture Jitter

100

Input Capacitance

Unipolar Mode
Bipolar Mode

--
--

335
215

--
--

Conversion and Throughput

Conversion Time

40.625

µ s

Acquisition Time

9.375

µ s

Throughput

kHz

Power Supplies

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5102ALP

16-Bit, 20 KHz A/D Converter

Power Supply Current

Positive Analog
Negative Analog

(SLEEP High) Positive Digital

Negative Digital

A+

A-

D+

D-

--
--
--
--

8.5

-7.7

0.5

-0.5

-11
1.5

-1.5

Power Consumption

11, 12

(SLEEP High)
(SLEEP Low)

--
--

85
45

130

Power Supply Rejection

Positive Supplies
Negative Supplies

PSR
PSR

--
--

84
84

--
--

1. Minimum resolution for which no missing codes are guaranteed over the specified temperature range.

2. Applies after calibration at any temperature within the specified temperature range.

3. Total drift over specified temperature range after calibration at power-up at 25°C.

4. Guaranteed by characterization (5102A die).

5. Wideband noise aliased into the baseband. Referred to the input.

6. Applied only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF.

7. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback (FRN

mode). In PDT, RBT, and SSC modes, asynchronrous delay between the falling edge of HOLD and the start of conversion may
add to the apparent conversion time. This delay will not exceed 1 master clock cycle + 140 ns.

8. The 5102ALPRP requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µ s of fine charge. FRN mode

allows 9 clock cycles for fine charge which provides for the minimum 5.625 µ s with a 1.6 MHz clock; however, in PDT, RBT, or
SSC modes, at clock frequencies less than 1.6 MHz, fine charge may be less than 9 clock cycles.

9. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting acquisition

and conversion times described above.

10.Typical value (measured).

11. All outputs unloaded. All inputs at VD+ or DGND.

12.Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low).

13.With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB in the unipo-

lar mode to 90 dB.

ABLE

4. 5102ALP S

WITCHING

HARACTERISTICS

= T

MIN

MAX

; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; I

NPUTS

: L

OGIC

0 = 0V, L

OGIC

1 = VD+; C

= 50

ARAMETER

YMBOL

NIT

CLKIN Period

1, 2

clk

0.5

µ s

CLKIN Low Time

clkl

200

CLKIN High Time

clkh

200

ABLE

3. A

NALOG

HARACTERISTICS

= T

MIN

MAX

; VA+, VD+ = 5V; VA-, VD- = -5V; V

REF

= 4.5V; F

ULL

-S

CALE

NPUT

INEWAVE

, 200 H

; CLKIN = 1.6 MH

; f

= 20

;

IPOLAR

ODE

;

FRN M

ODE

; AIN1

AND

AIN2

TIED

TOGETHER

EACH

CHANNEL

TESTED

SEPARATELY

; A

NALOG

OURCE

MPEDANCE

= 50 W

WITH

1000

AGND

UNLESS

OTHERWISE

SPECIFIED

)

ARAMETER

YMBOL

NIT

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5102ALP

16-Bit, 20 KHz A/D Converter

Crystal Frequency

1, 2

xtal

1.6

MHz

SLEEP Rising to Oscillator Stable

RST Pulse Width

rst

150

RST to STBY Falling

drrs

100

RST Rising to STBY Rising

cal

2,882,040

tclk

CH1/2 Edge to TRK1, TRK2 Rising

drsh1

CH1/2 Edge to TRK1, TRK2 Falling

dfsh4

68t

clk

+ 260

HOLD to SSH Falling

dfsh2

HOLD to TRK1, TRK2, Falling

dfsh1

66t

clk

68t

clk

+ 260

HOLD to TRK1, TRK2, SSH Rising

drsh

120

HOLD Pulse Width

hold

clk

+ 20

63t

clk

HOLD to CH1/2 Edge

dhlri

300

64t

clk

HOLD Falling to CLKIN Falling

hcf

275

clk

+ 10

PDT and RBT Modes

SCLK Input Pulse Period

sclk

1000

SCLK Input Pulse Width Low

sckll

500

SCLK Input Pulse Width High

sclkh

500

SCLK Input Falling to SDATA Valid

dss

100

150

HOLD Falling to SDATA Valid - PDT Mode

dhs

140

230

TRK1, TRK2 Falling to SDATA Valid

dts

125

FRN and SSC Modes

SCLK Output Pulse Width Low

slkl

clk

SCLK Output Pulse Width High

slkh

clk

SDATA Valid Before Rising SCLK

clk

- 100

SDATA Valid After Rising SCLK

clk

- 100

SDL Falling to 1st Rising SCLK

rsclk

clk

Last Rising SCLK to SDL Rising

rsdl

clk

+ 200

HOLD Falling to 1st Falling SCLK

hfs

clk

+ 200

CH1/2 Edge to 1st Falling SCLK

chfs

clk

1. Minimum CLKIN period is 0.625 µ s is FRN mode (20 kHz sample rate).

2. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency is 1.6 MHz in FRN mode

(20 kHz sample rate).

3. With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 MW parallel resistor.

4. Guaranteed by initial characterization (5102A die).

5. These times are for FRN mode.

6. These times are for PDT and RBT modes.

ABLE

4. 5102ALP S

WITCHING

HARACTERISTICS

= T

MIN

MAX

; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; I

NPUTS

: L

OGIC

0 = 0V, L

OGIC

1 = VD+; C

= 50

ARAMETER

YMBOL

NIT

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5102ALP

16-Bit, 20 KHz A/D Converter

LPTTM O

PERATION

Latchup Protection Technology (LPTTM) automatically detects an increase in the supply current of the 5102ALP con-
verter due to a single event effect and internally cycle the power to the converter off, then on, which restores the
steady state operation of the device.

If data outputs are connected to a bus with other bus driver circuits, all external data bus drivers must be tri-stated and
individual pull up resistors to the supply voltage (if used on the data bus) must no be less than 10 K ohm typical to
assure proper single event effect recovery.

STATUS can also be used to generate an input to the system data processor indicating that an LPTTM cycle has
occurred, and the protected device output accuracy may not be met until after the respective recovery time to the
event. The STATUS signal is generated from an advanced CMOS logic gate output. This output may not exhibit a
monotonic fall time and may even oscillate briefly while power is being restored to the protected device and the decou-
pling capacitance is charged. Loading on the STATUS output should be minimized because this signal is used inter-
nally by the 5102ALP. It is recommended that load current not exceed 2 mA and load capacitance be kept will below
1000 pF.

7. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched by a falling

edge of CLKIN. Conversion will begin on the next rising edge of CLKIN after HOLD is latched.

8. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then SDATA is valid t

dss

time after

the next falling SCLK.

ABLE

5. 5102ALP D

IGITAL

HARACTERISTICS

= T

MIN

X; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%)

ARAMETER

YMBOL

NIT

Calibration Memory Retention Power Supply Voltage
VA+ & VD+

1. VA- and VD- can be any value from zero to -5V for memory retention. Neither VA- or VD- should be allowed to go positive.

AIN1, AIN2 or V

REF

must not be greater than VA+ or VD+. This parameter is guaranteed by characterization.

2.0

High-Level Input Voltage

2.0

Low-Level Input Voltage

0.8

High-Level Output Voltage

2. I

OUT

= -100 µ A. This specification guarantees TTL compatibility (V

= 2.4V @ I

OUT

= -40 µ A.

(VD+) -1.0

Low-Level Output Voltage - I

OUT

= 1.6 mA

0.4

Input Leakage Current

µ A

Digital Output Pin Capacitance

OUT

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5102ALP

16-Bit, 20 KHz A/D Converter

5102ALP LPT

LOCK

IAGRAM

ATCH

ROTECTION

IRCUIT

(LPT) P

ESCRIPTION

AME

UNCTION

LPTBIT The LPT circuit will crowbar the power supplies to the SEI5102ALPRP for as long as a logi-

cal high is applied. Used to verify operation of the LPT. Normally a logical low or ground is
applied to this input.

-LPTV

Negative power supply. VA- and VD- are connected and can be measured on this pin. Nor-
mally -5V.

+LPTV Positive power supply. VA+ and VD+ are connected and can be measured on this pin. Nor-

mally +5V.

5102A

owbar

Switch

Current

Sense

Timer

Control Logic

Switch

Current

Sense

AIN 1

AIN 2

VREF

+VDIG

+VANA

-VDIG

-VANA

+LPTV

-LPTV

LPTBIT

LPTSTATUS

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5102ALP

16-Bit, 20 KHz A/D Converter

IGURE

7. B

YPASS

IRCUIT

Note:

1. Cap must be connected to the device for proper operation. 4.7 µ F analog side. 1 µ F digital side.

2. Unused logic inputs should be tied to +VD or DGND.

IGURE

8. P

OWER

ESET

IRCUIT

+VDIG

DGND

-VDIG

RST

CLKIN

XOUT

STBY

DGND

+VDIG

TRK1

TRK2

CRS/FIN

SSH/SDL

HOLD

CH1/2

SCLK

+LPTBIT

-VDIG

DGND

+VDIG

+VANLOG

AGND

-VANLOG

-LPTV

+LPTV

SDATA

CODE

BP/UP

OUTMOD

AIN1

VREF

REFBUF

AGND

-VANLOG

AIN2

+VANLOG

LPTSTATUS

SCKMOD

SLEEP

-VANLOG

AGND

+VANLOG

µF

4.7

µF

4.7

µF

+VD

RST

1N4148

+5V

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5102ALP

16-Bit, 20 KHz A/D Converter

Important Notice:

These data sheets are created using the chip manufacturers published specifications. MAxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.

Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.

Any claim against MAxwell TechnologiesInc. must be made within 90 days from the date of shipment from Maxwell
Technologies. Maxwell Technologies' liability shall be limited to replacement of defective parts.

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5102ALP

16-Bit, 20 KHz A/D Converter

Model Number

5102ALP - RP - F - X

Screening Flow

Multi Chip Module (MCM)

K = Maxwell Self-Defined Class K
H = Maxwell Self-Defined Class H
I = Industrial (testing @ -40°C,
+25°C, +110°C)
E = Engineering (testing @ +25°C)

F = Flat Pack

RP = R

-P

® package

16-Bit 20KHz A/D Converter

1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K flows.

Package

Radiation Feature

Base Product
Nomenclature

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 5102ALP-RP-F-E

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 5102ALP-RP-F-E