Memory

All data sheets are subject to change without notice

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CMOS Logic Hex

54HC4049

Inverting Buffers

12.20.01 Rev1

1000589

54HC4049

EATURES

· High speed CMOS logic hex inverting Buffers
· R

-P

® radiation hardened against natural space radia-

tion

· Single Event Effects:

- SEL: > 120 MeV/mg/cm2

· Total dose hardness:
· - > 100 Krad (Si), depending upon space mission
· Package:

-16 Pin R

-P

® Flat Pack

· Typical propagation delay:

- 6ns at V

= 5V, C

= 15pF, TA = 25°C

· High-to-Low voltage level converter for up to V

= 16V

· Fanout (over temperature range)

-10 LSTTL loads (Standard Outputs)
-15 LSTTL loads (Bus Driver Outputs)

· Balanced propagation delay and transition times
· Significant power reduction compared to LSTTL logic ICs
· 2V to 6V operation
· High noise immunity
· -N

= 30%, N

= 30% of V

at V

= 5V

ESCRIPTION

Maxwell Technologies' 54HC4049 high speed CMOS Logic
Hex Inverting Buffers features a greater than 100 krad(Si) total
dose tolerance, depending upon space misssion. These parts
have a modified input protection structure that enables them
to be used as logic level translators which will convert high-
level logic to a low-level logic while operating off the low-level
logic supply. For example, 15V input pulse levels can be
down-converted to 0V to 5V logic levels. The modified input
protection structure protects the input from negative electro-
static discharge. The 54HC4049 can be used as simple buff-
ers or inverters without level translation.

Maxwell Technologies' patented R

-P

® packaging technol-

ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R

-P

provides greater than 100

krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.

Logic Diagram

Memory

All data sheets are subject to change without notice

CMOS Logic Hex Inverting Buffers

54HC4049

12.20.01 Rev1

1000589

ABLE

1. 54HC4049 P

INOUT

ESCRIPTIONS

YMBOL

ESCRIPTION

Power supply

Ground

13, 16

Not Connected

3, 5, 7, 9, 11, 14

A - F

Inputs

G = A

Inverted Output

H = B

Inverted Output

I = C

Inverted Output

J = D

Inverted Output

K = E

Inverted Output

L = F

Inverted Output

ABLE

2. 54HC4049 A

BSOLUTE

AXIMUM

ATINGS

ARAMETER

YMBOL

NIT

Storage Temperature

-65

150

°C

Operating Temperature Range

-55

125

°C

DC Supply Voltage

-0.5

7.0

DC Input Diode Current
For V

< -0.5V or V

> V

+0.5V

-20

+20

DC Output Diode Current
For V

< -0.5V or V

> V

+0.5V

-20

+20

DC Output Source or Sink Current per Output Pin
For V

> -0.5V or V

< V

+0.5V

-25

+25

DC V

or Ground Current

or I

GND

-50

+50

ABLE

3. D

ELTA

IMITS

ARAMETER

ARIATION

±10% of specified value in Table 5

Memory

All data sheets are subject to change without notice

CMOS Logic Hex Inverting Buffers

54HC4049

12.20.01 Rev1

1000589

ABLE

4. 54HC4049 R

ECOMMENDED

PERATING

ONDITIONS

ARAMETER

YMBOL

NIT

Supply Voltage

DC Input or output Voltage

, V

Input Rise and Fall Time
2V
4.5V
6V

1000

500
400

Temperature Range

-55

125

°C

ABLE

5. 54HC4049 DC E

LECTRICAL

HARACTERISTICS

= 5V ±10%, T

= -55

125°C,

UNLESS

OTHERWISE

SPECIFIED

)

ARAMETER

YMBOL

EST

ONDITIONS

NIT

High Level Output Voltage
CMOS Loads

= V

or V

, I

= -0.02mA

= 2V

= 4.5V

= 6V

1.9
4.4
5.9

--
--
--

High Level Output Voltage
TTL Loads

= V

or V

, I

= -4mA

= 4.5V

+25°C

3.98

-55 to 125°C

3.7

= V

or V

, I

= -5.2mA

= 6V

+25°C

5.48

-55 to 125°C

5.2

Low Level Output Voltage
CMOS Loads

= V

or V

, I

= -0.02mA

= 2V

= 4.5V

= 6V

0.1
0.1
0.1

Low Level Output Voltage
TTL Loads

= V

or V

, I

= 4mA

= 4.5V

+25°C

0.26

-55 to 125°C

0.4

= V

or V

, I

= 5.2mA

= 6V

+25°C

0.26

-55 to 125°C

0.4

High Level Input Voltage

= 2V

= 4.5V

= 6V

1.5

3.15

4.2

--
--
--

Low Level Input Voltage

= 2V

= 4.5V

= 6V

--
--
--

0.5

1.35

1.8

Input Leakage Current

= 6V, V

= V

or GND

+25°C

±0.1

µA

-55 to 125°C

±1

= 6V, V

= 15V

+25°C

±0.5

-55 to 125°C

±5

Memory

All data sheets are subject to change without notice

CMOS Logic Hex Inverting Buffers

54HC4049

12.20.01 Rev1

1000589

Quiescent Device Current

= V

or GND, I

= 0mA

= 6V

+25°C

µA

-55 to 125°C

ABLE

6. 54HC4049 AC E

LECTRICAL

HARACTERISTICS

= 5V ±10%, T

= -55

125°C,

UNLESS

OTHERWISE

SPECIFIED

)

ARAMETER

YMBOL

EST

ONDITION

NIT

Propogation Delay
nA to nY

PLH,

PHL

= 50pF

= 2V

+25°C

-55 to 125°C

130

= 4.5V

+25°C

-55 to 125°C

= 6V

+25°C

-55 to 125°C

Transition Times
(Figure 1)

TLH,

THL

= 50pF

= 2V

+25°C

-55 to 125°C

110

= 4.5V

+25°C

-55 to 125°C

= 6V

+25°C

-55 to 125°C

ABLE

7. 54HC4049 C

APACITANCE1

1. Guaranteed by design.

ARAMETER

YMBOL

EST

ONDITIONS

NIT

Input Capacitance

Power Dissipation Capacitance

2, 3

2. C

is used to determine the dynamic power consumption, per gate.

3. P

= V

fi (C

+ C

) where fi = Input Frequency, C

= Output Load Capacitance, V

= Supply Voltage.

= 5V

ABLE

5. 54HC4049 DC E

LECTRICAL

HARACTERISTICS

= 5V ±10%, T

= -55

125°C,

UNLESS

OTHERWISE

SPECIFIED

)

ARAMETER

YMBOL

EST

ONDITIONS

NIT

Memory

All data sheets are subject to change without notice

CMOS Logic Hex Inverting Buffers

54HC4049

12.20.01 Rev1

1000589

F16-01

Note: All dimensions in inches

16-P

-P

® F

LAT

ACKAGE

YMBOL

IMENSION

0.115

0.135

0.150

0.015

0.017

0.019

0.004

0.005

0.007

0.407

0.415

0.423

0.275

0.280

0.285

0.500

0.150

0.156

0.162

0.030

0.062

0.050 BSC

0.325

0.335

0.345

0.020

0.033

0.045

0.005

0.024

0.045

Memory

All data sheets are subject to change without notice

CMOS Logic Hex Inverting Buffers

54HC4049

12.20.01 Rev1

1000589

Important Notice:

These data sheets are created using the chip manufacturer's published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.

Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech-
nologies. Maxwell Technologies' liability shall be limited to replacement of defective parts.

Memory

All data sheets are subject to change without notice

CMOS Logic Hex Inverting Buffers

54HC4049

12.20.01 Rev1

1000589

Product Ordering Options

Model Number

Feature

Option Details

54HC4049 RP

Screening Flow

Package

Radiation Feature

Base Product
Nomenclature

Monolithic
S = Maxwell Class S
B = Maxwell Class B
E = Engineering (testing @ +25°C)
I = Industrial (testing @ -55°C,
+25°C, +125°C)

F = Flat Pack

RP = R

-P

® package

CMOS Logic Hex Inverting Buffers

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