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(858) 503-3300 Fax: (858) 503-3301- www.maxwell.com

16-Bit Latchup Protected ADC

7805ALP

01.10.05 Rev 9

EATURES

· 16-bit organization
· Latchup Protection TechnologyTM
· R

-P

® radiation-hardened against natural space radia-

tion

· Total dose hardness:

- > 50 krads(Si), depending upon space mission

· Latchup converted to reset.

- Rate based on cross section and mission.

· Package:

- 28 pin R

-P

® flat pack

- 28 pin R

-P

® DIP

· 100 kHz min sampling rate
· Standard ± 10V input range
· Advance CMOS technology

- 86 dB min SINAD with 20 kHz input
- Single 5V supply operation
- Utilizes internal or external reference
- Full parallel data output
- Power dissipation: 132 mW max

ESCRIPTION

Maxwell Technologies' 7805ALP high-speed analog-to-digital
converter features a greater than 50 krad (Si) total dose toler-
ance, depending upon space mission. Using Mawell's radia-
tion-hardened R

-P

® packaging technology, the 7805ALP

incorporates the commercial ADS7805 from Burr Brown. This
device is latchup protected by Maxwell Technologies' LPTTM
technology. The 7805ALP, 16-bit sampling CMOS A/D . The
device contains a complete 16-bit capacitor-based SAR A/D
with S/H, reference, clock, interface for microprocessor use,
and three-state output drivers. The 7805ALP is specified at a
100 kHz sampling rate, and guaranteed over the full tempera-
ture range. Laser-trimmed scaling resistors provide an indus-
try-standard ± 10V input range, while the innovative design
allows operation from a single 5V supply, with power dissipa-
tion of under 132 mW.

Maxwell Technologies' patented R

-P

® packaging technol-

ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R

-P

® provides greater than 50

krad (Si) radiation dose tolerance. This product is available
with screening up to Maxwell Technologies self-defiened
Class K.

Logic Diagram

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All data sheets are subject to change without notice

16-Bit Latchup Protected ADC

7805ALP

01.10.05 Rev 9

ABLE

1. 7805ALP P

INOUT

ESCRIPTION

UMBER

AME

IGITAL

I/O

ESCRIPTION

Analog input.

AGND1

Analog ground. Used internally as ground reference point.

REF

Reference input/output. 2.2 µ F tantalum capacitor to ground

CAP

Reference buffer capacitor. 2.2 µ F tantalum capacitor to ground.

AGND2

Analog ground.

D15 (MSB)

Data bit 15. Most Significant Bit (MSB) of conversion results. When STATUS is
HIGH*, D15 must not be driven high.

D14

Data bit 14. When STATUS is HIGH*, D14 must not be driven high.

D13

Data bit 13. When STATUS is HIGH*, D13 must not be driven high.

D12

Data bit 12. When STATUS is HIGH*, D12 must not be driven high.

D11

Data bit 11. When STATUS is HIGH*, D11 must not be driven high.

D10

Data bit 10. When STATUS is HIGH*, D10 must not be driven high.

Data bit 9. When STATUS is HIGH*, D9 must not be driven high.

Data bit 8. When STATUS is HIGH*, D8 must not be driven high.

DGND

Digital Ground

Data bit 7. When STATUS is HIGH*, D7 must not be driven high.

Data bit 6. When STATUS is HIGH*, D6 must not be driven high.

Data bit 5. When STATUS is HIGH*, D5 must not be driven high.

Data bit 4. When STATUS is HIGH*, D4 must not be driven high.

Data bit 3. When STATUS is HIGH*, D3 must not be driven high.

Data bit 2. When STATUS is HIGH*, D2 must not be driven high.

Data bit 1. When STATUS is HIGH*, D1 must not be driven high.

D0 (LSB)

Data bit 0. Least Significant Bit (LSB) of conversion results. When STATUS is
HIGH*, D0 must not be driven high.

STATUS*

STATUS when HIGH indicates latchup protection is active and output data is
invalid. Capacitive loading should not exceed 1000 pF.

R/C

With CS LOW and BUSY HIGH, a falling edge of R/C initiates a new conversion.
When STATUS is HIGH*, CS and R/C must not be driven high.

Internally OR'd with R/C. If R/C LOW, a falling edge on CS initiates a new conver-
sion. When STATUS is HIGH*, CS and R/C must not be driven high.

BUSY

At the start of a conversion, BUSY goes LOW and stays LOW until the conversion
is completed and the digital outputs have been updated.

DECPLNG

Supply voltage high speed decoupling pin. Decouple to ground with 1.0 µ F ceramic
capacitor.

Supply input. Nominally 5V. Decouple to ground with 10 µ F tantalum capacitor.

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All data sheets are subject to change without notice

16-Bit Latchup Protected ADC

7805ALP

01.10.05 Rev 9

ABLE

2. 7805ALP A

BSOLUTE

AXIMUM

ATINGS

ARAMETER

YMBOL

NIT

Analog Inputs

CAP
REF

-25

--
--
--

AGND2 - 0.3

Ground Voltage Difference

DGND

AGND1
AGND2

-0.3
-0.3
-0.3

--
--
--

0.3
0.3
0.3

Supply Input

Digital Inputs

-0.3

VS + 0.3

Thermal Impedance

C/W

Internal Power Dissipation

825

Maximum Junction Temperature

165

ABLE

3. 7805ALP DC A

CCURACY

PECIFICATIONS

= 5V, T

= -40

+85

C U

NLESS

THERWISE

PECIFIED

)

ARAMETER

ONDITIONS

UBGROUPS

NIT

Integral Linearity Error

±3

LSB

Differential Linearity Error

4, -1

LSB

No Missing Codes

1. Guaranteed by design

Bits

Transition Noise

2. Typical rms noise at worst case transitions and temperatures.

1.3

LSB

Full Scale Error

3,4

3. Measured with various fixed resistors.

4. Full scale error is worst case - Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided

by the transition voltage (not divided by the full-scale range) and included the effect of offset error.

±0.5

Full Scale Error Drift

±7

ppm/

Bipolar Zero Error

±10

Bipolar Zero Error Drift

±2

ppm/

Power Supply Sensitivity

4.8V < V

< 5.25V

±8

LSB

ABLE

4. 7805ALP D

IGITAL

NPUTS

= 5V, T

= -40

+85

C U

NLESS

THERWISE

PECIFIED

)

ARAMETER

UBGROUPS

NIT

1, 2, 3

-0.3

0.8

2.0

+0.3

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All data sheets are subject to change without notice

16-Bit Latchup Protected ADC

7805ALP

01.10.05 Rev 9

, I

1, 2, 3

±10

µ A

ABLE

5. 7805ALP A

NALOG

NPUTS

= 5V, T

= -40

+85

C U

NLESS

THERWISE

PECIFIED

)

ARAMETER

UBGROUPS

NIT

Voltage Ranges

1. Tested by application of signal.

1, 2, 3

-10

±10

Impedance

1, 2, 3

Capacitance

2. Guarenteed by design

ABLE

6. 7805ALP T

HROUGHPUT

PEED

= 5V, T

= -40

+85

C U

NLESS

THERWISE

PECIFIED

)

ARAMETER

UBGROUPS

NIT

Conversion Time

9, 10, 11

7.6

µ s

Complete Cycle (Acquire and Convert)

9, 10, 11

µ s

Throughput Rate

1. Guaranteed by design

100

kHz

ABLE

7. 7805ALP AC A

CCURACY

PECIFICATIONS

= 5V, T

= -40

+85

C U

NLESS

THERWISE

PECIFIED

)

ARAMETER

EST

ONDITIONS

UBGROUPS

NIT

Spurious-Free Dynamic Range

1,2

1. All specifications in dB are referred to a full-scale 10V input.

2. Guaranteed by design.

= 45 kHz

4, 5, 6

Total Harmonic Distortion

1,2

= 45 kHz

4, 5, 6

-90

Signal-to-(Noise + Distortion)

1,2

= 45 kHz

4, 5, 6

-60dB Input

4, 5, 6

Signal-to-Noise

1,2

= 45 kHz

4, 5, 6

Full-Power Bandwidth

3. Full-power bandwidth defined as full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB or 10 bits of

accuracy.

4, 5, 6

250

kHz

ABLE

4. 7805ALP D

IGITAL

NPUTS

= 5V, T

= -40

+85

C U

NLESS

THERWISE

PECIFIED

)

ARAMETER

UBGROUPS

NIT

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All data sheets are subject to change without notice

16-Bit Latchup Protected ADC

7805ALP

01.10.05 Rev 9

ABLE

8. 7805ALP S

AMPLING

YNAMICS

= 5V, T

= -40

+85

C U

NLESS

THERWISE

PECIFIED

)

ARAMETER

EST

ONDITIONS

UBGROUPS

NIT

Aperture Delay

9, 10, 11

Transient Response

FS Step

9, 10, 11

µ S

Overvoltage Recovery

1. Recovers to specified performance after 2 x f

input overvoltage.

9, 10, 11

150

ABLE

9. 7805ALP R

EFERENCE

ABLE

10.

= 5V, T

= -40

+85

C U

NLESS

THERWISE

PECIFIED

)

ARAMETER

UBGROUPS

NIT

Internal Reference Voltage

1, 2, 3

2.48

2.5

2.52

Internal Reference Source Current (Must use external buffer)

1, 2, 3

µ A

Internal Reference Drift

1, 2, 3

ppm/

External Reference Voltage Range for Specified Linearity

1. Tested by application of signal.

1, 2, 3

2.5

External Reference Current Drain

2. Guaranteed by design

100

µ A

ABLE

11. 7805ALP D

IGITAL

UTPUTS

= 5V, T

= -40

+85

C U

NLESS

THERWISE

PECIFIED

)

ARAMETER

EST

ONDITIONS

UBGROUPS

NIT

Data Formatting

(Parallel 16-bits Binary Two's Complement)

Data Coding

Binary Two's Complement

SINK

= 1.6mA) 4.0

1, 2, 3

0.4

SOURCE

= -400 µ A)

1, 2, 3

4.0

Leakage Current

High-Z State, V

OUT

= 0V

to V

1, 2, 3

±5

µ A

Output Capacitance

1. Guarenteed by design

High-Z State

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