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REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

2M-BIT[256K x 8]CMOS FLASH MEMORY

FEATURES

262,144x 8 only

Fast access time: 55/70/90/120ns

Low power consumption

- 30mA maximum active current

- 1uA typical standby current@5MHz

Programming and erasing voltage 5V

10%

Command register architecture

- Byte Programming (7us typical)

- Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte

x1, and 64K-Byte x 3)

Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors or

the whole chip with Erase Suspend capability.

- Automatically programs and verifies data at speci-

fied address

Erase Suspend/Erase Resume

- Suspends an erase operation to read data from, or

program data to, a sector that is not being erased,

then resumes the erase operation.

Status Reply

- Data polling & Toggle bit for detection of program

and erase cycle completion.

Chip protect/unprotect for 5V only system or 5V/12V

system

100,000 minimum erase/program cycles

Latch-up protected to 100mA from -1 to VCC+1V

Boot Code Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

Hardware RESET pin

- Resets internal state machine to read mode

Low VCC write inhibit is equal to or less than 3.2V

Package type:

- 32-pin PDIP

- 32-pin PLCC

- 32-pin TSOP (Type 1)

20 years data retention

GENERAL DESCRIPTION

The MX29F022T/B is a 2-mega bit Flash memory
organized as 256K bytes of 8 bits only. MXIC's Flash
memories offer the most cost-effective and reliable read/
write non-volatile random access memor y. The
MX29F022T/B is packaged in 32-pin PDIP, PLCC and
32-pin TSOP(I). It is designed to be reprogrammed and
erased in-system or in-standard EPROM programmers.

The standard MX29F022T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29F022T/B has separate chip enable (CE) and
output enable (OE) controls.

MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F022T/B uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining
maximum EPROM compatibility.

MXIC's Flash technology reliably stores memory
contents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The MX29F022T/
B uses a 5.0V

10% VCC supply to perform the High

Reliability Erase and auto Program/Erase algorithms.

The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.

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REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

PIN CONFIGURATIONS

32 PDIP

SECTOR STRUCTURE

32 PLCC

32 TSOP (TYPE 1)

(NORMAL TYPE)

SYMBOL

PIN NAME

A0~A17

Address Input

Q0~Q7

Data Input/Output

Chip Enable Input

Write Enable Input

RESET

Hardware Reset Pin/Sector Protect Unlock

Output Enable Input

VCC

Power Supply Pin (+5V)

GND

Ground Pin

PIN DESCRIPTION:

MX29F022T Sector Architecture

MX29F022B Sector Architecture

1 6 K - B Y T E

8 K - B Y T E

3 2 K - B Y T E

0 0 0 0 0 H

3 F F F F H

( B O O T S E C T O R )

6 4 K - B Y T E

3 B F F F H

3 9 F F F H

3 7 F F F H

2 F F F F H

1 F F F F H

0 F F F F H

A 1 7 ~ A 0

1 6 K - B Y T E

8 K - B Y T E

3 2 K - B Y T E

0 0 0 0 0 H

( B O O T S E C T O R )

6 4 K - B Y T E

3 F F F F H

2 F F F F H

1 F F F F H

0 7 F F F H

0 5 F F F H

0 3 F F F H

0 F F F F H

A 1 7 ~ A 0

MX29F022T/B

RESET

A16

A15

A12

GND

NC on MX29F022NT/B

VCC

A17

A14

A13

A11

A10

A11

A9
A8

A13
A14
A17

VCC

RESET

A16
A15
A12

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

MX29F022T/B

(NC on

MX29F022NT/B)

A14

A13

A11

A10

VSS

A12

A15

A16

RESET

VCC

A17

MX29F022T/B

NC on MX29F022NT/B

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REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

AUTOMATIC PROGRAMMING

The MX29F022T/B is byte programmable using the
Automatic Programming algorithm. The Automatic
Programming algorithm does not require the system to
time out or verify the data programmed. The typical chip
programming time of the MX29F022T/B at room tem-
perature is less than 2 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10ms erase pulses
according to MXIC's High Reliability Chip Erase
algorithm. Typical erasure at room temperature is
accomplished in less than two second. The device is
erased using the Automatic Erase algorithm. The
Automatic Erase algorithm automatically programs the
entire array prior to electrical erase. The timing and
verification of electrical erase are internally controlled
within the device.

AUTOMATIC SECTOR ERASE

The MX29F022T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically pro-
grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are inter-
nally controlled by the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the
user to only write a program set-up commands (include
2 unlock write cycle and A0H) include 2 unlock write
cycle and A0H and a program command (program data
and address). The device automatically times the pro-
gramming pulse width, verifies the program verification,
and counts the number of sequences. A status bit simi-
lar to DATA polling and a status bit toggling between con-
secutive read cycles, provides feedback to the user as
to the status of the programming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will au-
tomatically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
verifies the erase, and counts the number of sequences.
A status bit similar to DATA polling and status bit tog-
gling between consecutive read cycles provides feed-
back to the user as to the status of the programming
operation.

Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine which
controls the erase and programming circuitry. During
write cycles, the command register internally latches
address and data needed for the programming and erase
operations. During a system write cycle addresses are
latched on the falling edge, and data are latched on the
rising edge of WE .

MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29F022T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed one
byte at a time using the EPROM programming mecha-
nism of hot electron injection.

During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.

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MX29F022/022NT/B

First Bus

Second Bus Third Bus

Fourth Bus

Fifth Bus

Sixth Bus

Command

Bus

Cycle

Addr

Data Addr

Data

Addr

Data Addr

Data Addr Data

Reset

XXXH F0H

Read

Read Silicon ID

555H

AAH 2AAH 55H

555H 90H

ADI

DDI

Chip Protect Verify

555H

AAH 2AAH 55H

555H 90H

(SA)

00H

X02H

01H

Program

555H

AAH 2AAH 55H

555H A0H

Chip Erase

555H

AAH 2AAH 55H

555H 80H

555H

AAH 2AAH 55H 555H 10H

Sector Erase

555H

AAH 2AAH 55H

555H 80H

555H

AAH 2AAH 55H SA

30H

Sector Erase Suspend

XXXH B0H

Sector Erase Resume

XXXH 30H

Unlock for chip

555H

AAH 2AAH 55H

555H 80H

555H

AAH 2AAH 55H 555H 20H

protect/unprotect

Note:
1. ADI = Address of Device identifier; A1=0,A0 =0 for manufacture code,A1=0, A0 =1 for device code (Refer to Table

3).
DDI = Data of Device identifier : C2H for manufacture code, 36H/37H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.

Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A17 in either state.

4. For Chip Protect Verify operation: If read out data is 01H, it means the chip has been protected. If read out data is

00H, it means the chip is still not being protected.

TABLE 1. SOFTWARE COMMAND DEFINITIONS

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MX29F022/022NT/B

Pins

Q0~Q7

Mode

Read Silicon ID

(2)

C2H

Manufacturer Code(1)

Read Silicon ID

(2)

36H/37H

Device Code(1)

Read

OUT

Standby

HIGH Z

Output Disable

HIGH Z

Write

(3)

Chip Protect with 12V

(2)

system (6)

Chip Unprotect with 12V

(2)

system (6)

Verify chip Protect

(2)

Code (5)

with 12V system

Chip Protect without 12V

system (6)

Chip Unprotect without 12V

system (6)

Verify Chip Protect/Unprotect

Code(5)

without 12V system (7)

Reset

HIGH Z

NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H means unprotected.

Code=01H means protected.

6. Refer to chip protect/unprotect algorithm and waveform.
Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system"

command.

7. The "verify chip protect/unprotect without 12V system" is only following "chip protect/unprotect without 12V sys-

tem"
command.

TABLE 2. MX29F022T/B BUS OPERATION

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MX29F022/022NT/B

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.

If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage. However, multiplexing high voltage onto
address lines is not generally desired system design prac-
tice.

The MX29F022T/B contains a Silicon-ID-Read opera-
tion to supplement traditional PROM programming meth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis-
ter. Following the command write, a read cycle with
A1=VIL, A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of 36H for MX29F022T, 37H for MX29F022B.

Pins

Code(Hex)

Manufacture code

VIL

C2H

Device code

VIH

VIL

36H

for MX29F022T

Device code

VIH

VIL

37H

for MX29F022B

Chip Protection Verification

VIH

01H (Protected)

VIH

00H (Unprotected)

TABLE 3. EXPANDED SILICON ID CODE

SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS

Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero pat-
tern, a self-timed chip erase and verification begin. The
erase and verification operations are completed when
the data on Q7 is "1" at which time the device returns to
the Read mode. The system is not required to provide
any control or timing during these operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verify command is required).

If the Erase operation was unsuccessful, the data on Q5
is "1" (see Table 4), indicating the erase operation of ex-
ceed internal timing limit.

The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.

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MX29F022/022NT/B

The Automatic Sector Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Set-up Sector Erase command and Automatic
Sector Erase command. Upon executing the Automatic
Sector Erase command, the device will automatically
program and verify the sector(s) memory for an all-zero
data pattern. The system does not require to provide
any control or timing during these operations.

When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verifi-
cation begin. The erase and verification operations are
complete when the data on Q7 is "1" and the data on Q6
stops toggling for two consecutive read cycles, at which
time the device returns to the Read mode. The system
does not required to provide any control or timing
during these operations.

When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
set-up command-80H. Two more "unlock" write cycles
are then followed by the sector erase command-30H.
The sector address is latched on the falling edge of WE,
while the command(data) is latched on the rising edge
of WE. Sector addresses selected are loaded into
internal register on the sixth falling edge of WE. Each
successive sector load cycle started by the falling edge
of WE must begin within 30us from the rising edge of
the preceding WE. Otherwise, the loading period ends
and internal auto sector erase cycle starts. (Monitor Q3
to determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command
other than Sector Erase (30H) or Erase Suspend (B0H)
during the time-out period resets the device to read mode.

ERASE SUSPEND

This command is only valid while the state machine is
executing Automatic Sector Erase operation, and
therefore will only be responded during Automatic/Sec-
tor Erase operation. Writing the Erase Suspend com-
mand during the Sector Erase time-out immediately ter-
minates the time-out period and suspends the erase op-

eration. After this command has been executed, the
command register will initiate erase suspend mode. The
state machine will return to read mode automatically af-
ter suspend is ready. At this time, state machine only
allows the command register to respond to the Read
Memory Array, Erase Resume and Program commands.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspended
program operation is complete, the system can once
again read array data within non-suspended sectors.

SET-UP AUTOMATIC SECTOR ERASE COM-
MANDS

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MX29F022/022NT/B

Note:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5 : Exceeded Timing Limits" for more information.

Status

Note1

Note2

Byte Program in Auto Program Algorithm

Toggle

N/A

No Toggle

Auto Erase Algorithm

Toggle

Erase Suspend Read

N/A

Toggle

In Progress

(Erase Suspended Sector)

Toggle

Erase Suspended Mode

Erase Suspend Read

Data

(Non-Erase Suspended Sector)

Erase Suspend Program

Toggle

N/A

Byte Program in Auto Program Algorithm

Toggle

N/A

No Toggle

Exceeded

Auto Erase Algorithm

Toggle

Time Limits Erase Suspend Program

Toggle

N/A

TABLE 4. WRITE OPERATION STATUS

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MX29F022/022NT/B

ERASE RESUME

This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all other
conditions. Another Erase Suspend command can be
written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM COMMANDS

To initiate Automatic Program mode, A three-cycle com-
mand sequence is required. There are two "unlock" write
cycles. These are followed by writing the Automatic Pro-
gram command A0H.

Once the Automatic Program command is initiated, the
next WE pulse causes a transition to an active program-
ming operation. Addresses are latched on the falling edge,
and data are internally latched on the rising edge of the
WE pulse. The rising edge of WE also begins the pro-
gramming operation. The system does not require to pro-
vide further controls or timings. The device will automati-
cally provide an adequate internally generated program
pulse and verify margin.

If the program operation was unsuccessful, the data on
Q5 is "1", indicating the program operation of internally
exceed timing limit. The automatic programming opera-
tion is complete when the data read on Q6 stops tog-
gling for two consecutive read cycles and the data on
Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read mode(no
program verify command is required).

WRITE OPERATION STATUS DATA POLLING-
Q7

The MX29F022T/B also features Data Polling as a
method to indicate to the host system that the Auto-
matic Program or Erase algorithms are either in progress
or completed.

While the Automatic Programming algorithm is in
operation, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an
attempt to read the device will produce the true data last
written to Q7. The Data Polling feature is valid after the

rising edge of the second WE pulse of the two write pulse
sequences.

While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is compete. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data Polling feature is valid after the rising
edge of the second WE pulse of two write pulse se-
quences.

The Data Polling feature is active during Automatic Pro-
gram/Erase algorithm or sector erase time-out. (see sec-
tion Q3 Sector Erase Timer)

Q6 : Toggle BIT I

The MX29F022T/B features a "Toggle Bit" as a method
to indicate to the host system that the Auto Program/
Erase algorithms are either in progress or complete.

During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE or CE to con-
trol the read cycles. When the operation is complete, Q6
stops toggling.

After an erase command sequence is written, if the chip
is protected, Q6 toggles and returns to reading array data.

The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended.
When the device is actively erasing (that is, the Auto-
matic Erase algorithm is in progress), Q6 toggling. When
the device enters the Erase Suspend mode, Q6 stops
toggling. However, the system must also use Q2 to de-
termine which sectors are erasing or erase-suspended.
Alternatively, the system can use Q7(see the subsec-
tion on Q7 : Data Polling).

If a program address falls within a protected sector, Q6
toggles for approximately 2us after the program com-
mand sequence is written, then returns to reading array
data.

Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo-
rithm is complete.

The Write Operation Status table shows the outputs for
Toggle Bit I on Q6. Refer to the toggle bit algorithm.

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MX29F022/022NT/B

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether
that sector is erase-suspended. Toggle Bit I is valid after
the rising edge of the final WE pulse in the command
sequence.

Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-
parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sectors and mode information. Refer to
Table 4 to compare outputs for Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Refer to the toggle bit algorithm for the following
discussion. Whenever the system initially begins
reading toggle bit status, it must read Q7-Q0 at least
twice in a row to determine whether a toggle bit is
toggling. Typically, the system would note and store the
value of the toggle bit after the first read. After the
second read, the system would compare the new value
of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase
operation. The system can read array data on Q7-Q0 on
the following read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase opera-
tion. If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.

The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the

status as described in the previous paragraph.
Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of the toggle bit algorithm
flow chart).

Q5
Exceeded Timing Limits

Q5 will indicate if the program or erase time has
exceeded the specified limits (internal pulse count). Under
these conditions Q5 will produce a "1". This time-out con-
dition indicates that the program or erase cycle was not
successfully completed. Data Polling and Toggle Bit are
the only operating functions not of the device under this
condition.

If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other
sectors. Write the Reset command sequence to the de-
vice, and then execute program or erase command se-
quence. This allows the system to continue to use the
other active sectors in the device.

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.

If this time-out condition occurs during the byte
programming operation, it specifies that the entire
sector containing that byte is bad and this sector may
not be reused, (other sectors are still functional and can
be reused).

The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the
Automatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops
toggling. Once the Device has exceeded timing limits,
the Q5 bit will indicate a "1". Please note that this is not
a device failure condition since the device was
incorrectly used.

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MX29F022/022NT/B

Q3
Sector Erase Timer

After the completion of the initial sector erase command
sequence the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase com-
mand sequence.

If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the
command has been accepted, the system software
should check the status of Q3 prior to and following each
subsequent sector erase command. If Q3 were high on
the second status check, the command may not have
been accepted.

DATA PROTECTION

The MX29F022T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with its
control register architecture, alteration of the memory
contents only occurs after successful completion of spe-
cific command sequences. The device also incorporates
several features to prevent inadvertent write cycles re-
sulting from VCC power-up and power-down transition or
system noise.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns (typical) on CE or WE will
not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND.

CHIP PROTECTION WITH 12V SYSTEM

The MX29F022T/B features hardware chip protection,
which will disable both program and erase operations. To
activate this mode, the programming equipment must
force VID on address pin A9 and control pin OE, (sug-
gest VID = 12V) A6 = VIL and CE = VIL.(see Table 2)
Programming of the protection circuitry begins on the
falling edge of the WE pulse and is terminated on the
rising edge. Please refer to chip protect algorithm and
waveform.

To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 ( with CE and OE at VIL and WE at VIH. When A1=1,
it will produce a logical "1" code at device output Q0 for
the protected status. Otherwise the device will produce
00H for the unprotected status. In this mode, the ad-
dresses, except for A1, are in "don't care" state. Ad-
dress locations with A1 = VIL are reserved to read manu-
facturer and device codes.(Read Silicon ID)

It is also possible to determine if the chip is protected in
the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected status.

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F022T/B also features the chip unprotect mode,
so that all sectors are unprotected after chip unprotect is
completed to incorporate any changes in the code.

To activate this mode, the programming equipment must
force VID on control pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.(see
Table 2) Refer to chip unprotect algorithm and waveform
for the chip unprotect algorithm. The unprotection mecha-
nism begins on the falling edge of the WE pulse and is
terminated on the rising edge.

It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.

P/N:PM0556

REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

ABSOLUTE MAXIMUM RATINGS

RATING

VALUE

Ambient Operating Temperature

C to 70

Storage Temperature

-65

C to 125

Applied Input Voltage

-0.5V to 7.0V

Applied Output Voltage

-0.5V to 7.0V

VCC to Ground Potential

-0.5V to 7.0V

-0.5V to 13.5V

NOTICE:
Stresses greater than those listed under ABSOLUTE MAXI-
MUM RATINGS may cause permanent damage to the de-
vice. This is a stress rating only and functional operational
sections of this specification is not implied. Exposure to ab-
solute maximum rating conditions for extended period may
affect reliability.

NOTICE:
Specifications contained within the following tables are sub-
ject to change.

Performing a read operation with A1=VIH, it will produce
00H at data outputs (Q0-Q7) for an unprotected chip. It
is noted that all sectors are unprotected after the chip
unprotect algorithm is complete.

CHIP PROTECTION WITHOUT 12V SYSTEM

The MX29F022T/B also feature a hardware chip
protection method in a system without 12V power sup-
ply. The programming equipment do not need to supply
12 volts to protect all sectors. The details are shown in
chip protect algorithm and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F022T/B also feature a hardware chip
unprotection method in a system without 12V power sup-
ply. The programming equipment do not need to supply
12 volts to unprotect all sectors. The details are shown
in chip unprotect algorithm and waveform.

POWER-UP SEQUENCE

The MX29F022T/B powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of a two-step command sequence.
Vpp and Vcc power up sequence is not required.

P/N:PM0556

REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

CAPACITANCE TA = 25

C, f = 1.0 MHz

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

CIN1

Input Capacitance

VIN = 0V

CIN2

Control Pin Capacitance

VIN = 0V

COUT

Output Capacitance

VOUT = 0V

READ OPERATION

DC CHARACTERISTICS TA = 0

C TO 70

C, VCC = 5V

10% (VCC=5V

5% for 29F022/022N-55)

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

ILI

Input Leakage Current

VIN = GND to VCC

ILO

Output Leakage Current

VOUT = GND to VCC

ISB1

Standby VCC current

CE = VIH

ISB2

CE = VCC + 0.3V

ICC1

Operating VCC current

IOUT = 0mA, f=5MHz

ICC2

IOUT = 0mA, f=10MHz

VIL

Input Low Voltage

-0.3(NOTE1)

0.8

VIH

Input High Voltage

2.0

VCC + 0.3

VOL

Output Low Voltage

0.45

IOL = 2.1mA

VOH1

Output High Voltage(TTL)

2.4

IOH =-2mA

VOH2

Output High Voltage(CMOS)VCC-0.4

IOH =-100uA,VCC=VCC

MIN

NOTES:

1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.

P/N:PM0556

REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

AC CHARACTERISTICS TA = 0

C to 70

C, VCC = 5V

±±
±±
±

10%(VCC = 5V

±±
±±
±

5% for 29F022T/B-55)

29F022T/B-55

29F022T/B-70

SYMBOL PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT CONDITIONS

tACC

Address to Output Delay

CE=OE=VIL

tCE

CE to Output Delay

OE=VIL

tOE

OE to Output Delay

CE=VIL

tDF

OE High to Output Float (Note1)

CE=VIL

tOH

Address to Output hold

CE=OE=VIL

NOTE:
1.tDF is defined as the time at which the output achieves the
open circuit condition and data is no longer driven.

TEST CONDITIONS:

Input pulse levels: 0.45V/2.4V for 70ns max.

: 0V/3V for 55ns speed grade.

Input rise and fall times: < 10ns for 70ns max.

: < 5ns for 55ns speed grade.

Output load: 1 TTL gate + 100pF(Including scope and jig) for 70ns max.

: 1 TTL gate + 50pF(Including scope and jig) for 55ns speed grade.

Reference levels for measuring timing : 0.8V/2.0V or 70ns max.

:1.5V/1.5V for 55ns speed grade.

29F022T/B-90

29F022T/B-120

SYMBOL PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT CONDITIONS

tACC

Address to Output Delay

120

CE=OE=VIL

tCE

CE to Output Delay

120

OE=VIL

tOE

OE to Output Delay

CE=VIL

tDF

OE High to Output Float (Note1)

CE=VIL

tOH

Address to Output hold

CE=OE=VIL

P/N:PM0556

REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

DC CHARACTERISTICS TA = 0

C to 70

C, VCC = 5V

10%(VCC = 5V

5% for 29F022/022N-55)

SYMBOL

PARAMETER

MIN.

TYP MAX. UNIT CONDITIONS

ICC1 (Read)

Operating VCC Current

IOUT=0mA, f=5MHz

ICC2

IOUT=0mA, F=10MHz

ICC3 (Program)

In Programming

ICC4 (Erase)

In Erase

ICCES

VCC Erase Suspend Current

CE=VIH, Erase Suspended

NOTES:
1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.
2. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is

the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

P/N:PM0556

REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

AC CHARACTERISTICS TA = 0

C to 70

C, VCC = 5V

10%(VCC=5V

±±
±±
±

5% for 29F022T/B-55)

29F022T/B-55(Note2) 29F022T/B-70 29F022T/B-90

29F022T/B-12

SYMBOL

PARAMETER

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX. UNIT

tOES

OE setup time

tCWC

Command programming cycle

120

tCEP

WE programming pulse width

tCEPH1

WE programming pulse width High

tCEPH2

WE programming pulse width High

tAS

Address setup time

tAH

Address hold time

tDS

Data setup time

tDH

Data hold time

tCESC

CE setup time before command write

tDF

Output disable time (Note 1)

tAETC

Total erase time in auto chip erase

3(TYP.) 24

tAETB

Total erase time in auto sector erase

1(TYP.) 8

tAVT

Total programming time in auto verify

7(TYP.) 210

(Byte Program time)

tBAL

Sector address load time

100

tCH

CE Hold Time

tCS

CE setup to WE going low

tVLHT

Voltage Transition Time

tOESP

OE Setup Time to WE Active

tWPP1

Write pulse width for chip protect

tWPP2

Write pulse width for chip unprotect

NOTES:
1.tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
2.Under condition of VCC=5V

5%,CL=50pF, VIH/VIL=3.0V/0V, VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=-2mA.

P/N:PM0556

REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

AUTOMATIC PROGRAMMING TIMING WAVEFORM

polling and toggle bit checking after automatic
verification star ts. Device outputs DATA during
programming and DATA after programming on Q7.(Q6 is
for toggle bit; see toggle bit, DATA polling, timing
waveform)

One byte data is programmed. Verifying in fast
algorithm and additional programming by external
control are not required because these operations are
executed automatically by internal control circuit.
Programming completion can be verified by DATA

tCWC

tAS

tCEP

tDS

tDH

tDF

Vcc 5V

Q0~Q1

,Q4(Note 1)

A11~A17

tCEPH1

tAH

ADD Valid

tCESC

Command In

ADD Valid

A0~A10

Command In

Data In

DATA

Command In

Data In

DATA

tAVT

tOE

DATA polling

2AAH

555H

Command #AAH

Command #55H

Command #A0H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2:Toggle bit

P/N:PM0556

REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

AUTOMATIC CHIP ERASE TIMING WAVEFORM

automatic erase starts. Device outputs "0" during
erasure and 1 after erasure on Q7.(Q6 is for toggle bit;
see toggle bit, DATA polling, timing waveform)

AUTOMATIC CHIP ERASE TIMING WAVEFORM

All data in chip are erased. External erase verification is
not required because data is erased automatically by
internal control circuit. Erasure completion can be
verified by DATA polling and toggle bit checking after

tCWC

tAS

tCEP

tDS tDH

Vcc 5V

Q0,Q1,

Q4(Note 1)

A11~A17

tCEPH1

tAH

Command In

A0~A10

Command In

tAETC

DATA polling

2AAH

555H

Command #AAH

Command #55H

Command #80H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

555H

2AAH

555H

Command In

Command #AAH

Command In

Command #55H

Command In

Command #10H

P/N:PM0556

REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Sector data indicated by A13 to A17 are erased. Exter-
nal erase verification is not required because data are
erased automatically by internal control circuit. Erasure
completion can be verified by DATA polling and toggle bit

checking after automatic erase starts. Device outputs 0
during erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, DATA polling, timing waveform)

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

tAH

Sector

Address0

555H

2AAH

555H

Sector

Address1

Sector

Addressn

Vcc 5V

Q0,Q1,

Q4(Note 1)

A13~A17

A0~A10

Command

Command #30H

Command #55H

Command #AAH

Command #80H

Command #55H

Command #AAH

(Q0~Q7)

Command

tDH

tDS

tCEP

tCWC

tAETB

tBAL

DATA polling

tCEPH1

tAS

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0556

REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

TIMING WAVEFORM FOR CHIP PROTECTION/UNPROTECTION FOR SYSTEM WITHOUT 12V

Note1: Don't care except F0H.
Note2: Protection:7th command cycle A6 goes low.

Unprotection: 7th command cycle A6 goes high.

Note3: Protection verify:01H

Un-protection verify:00H

Note4: Must issue "unlock for chip protection/unprotection" command before chip protection/un-protection for a

system without 12V provided.

6th command
cycle : 555H

7th command
cycle

A6,A9 & sector address are don't care
during toggle bit polling period, or just
be kept valid value in read window.

Protected Verify

Reset to Read Mode

'0'

'1'

'0'

(Note 2)

'0'

'1'

tACC

tOE

tCE

tAS tAH

tCEP

X=Don't care

A6,A9 and Sector Addr. should be latched on the falling e
dge of WE or CE , ehich occurs last, for WSM reference

Toggle Bit Polling

X(2)

20H

Dout

F0H

(Q0-Q7)

P/N:PM0556

REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

PLASTIC PACKAGE

PART NO.

ACCESS TIME

OPERATING CURRENT

STANDBY CURRENT

PACKAGE

(ns)

MAX.(mA)

MAX.(uA)

MX29F022TPC-55

32 Pin PDIP

MX29F022TPC-70

32 Pin PDIP

MX29F022TPC-90

32 Pin PDIP

MX29F022TPC-12

120

32 Pin PDIP

MX29F022TTC-55

32 Pin TSOP

(Normal Type)

MX29F022TTC-70

32 Pin TSOP

(Normal Type)

MX29F022TTC-90

32 Pin TSOP

(Normal Type)

MX29F022TTC-12

120

32 Pin TSOP

(Normal Type)

MX29F022TQC-55

32 Pin PLCC

MX29F022TQC-70

32 Pin PLCC

MX29F022TQC-90

32 Pin PLCC

MX29F022TQC-12

120

32 Pin PLCC

MX29F022BPC-55

32 Pin PDIP

MX29F022BPC-70

32 Pin PDIP

MX29F022BPC-90

32 Pin PDIP

MX29F022BPC-12

120

32 Pin PDIP

MX29F022BTC-55

32 Pin TSOP

(Normal Type)

MX29F022BTC-70

32 Pin TSOP

(Normal Type)

MX29F022BTC-90

32 Pin TSOP

(Normal Type)

MX29F022BTC-12

120

32 Pin TSOP

(Normal Type)

MX29F022BQC-70

32 Pin PLCC

MX29F022BQC-90

32 Pin PLCC

MX29F022BQC-12

120

32 Pin PLCC

MX29F022NTPC-55

32 Pin PDIP

MX29F022NTPC-70

32 Pin PDIP

MX29F022NTPC-90

32 Pin PDIP

MX29F022NTPC-12

120

32 Pin PDIP

ORDERING INFORMATION

P/N:PM0556

REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

PART NO.

ACCESS TIME

OPERATING CURRENT

STANDBY CURRENT

PACKAGE

(ns)

MAX.(mA)

MAX.(uA)

MX29F022NTTC-55

32 Pin TSOP

(Normal Type)

MX29F022NTTC-70

32 Pin TSOP

(Normal Type)

MX29F022NTTC-90

32 Pin TSOP

(Normal Type)

MX29F022NTTC-12

120

32 Pin TSOP

(Normal Type)

MX29F022NTQC-55

32 Pin PLCC

MX29F022NTQC-70

32 Pin PLCC

MX29F022NTQC-90

32 Pin PLCC

MX29F022NTQC-12

120

32 Pin PLCC

MX29F022NBPC-55

32 Pin PDIP

MX29F022NBPC-70

32 Pin PDIP

MX29F022NBPC-90

32 Pin PDIP

MX29F022NBPC-12

120

32 Pin PDIP

MX29F022NBTC-55

32 Pin TSOP

(Normal Type)

MX29F022NBTC-70

32 Pin TSOP

(Normal Type)

MX29F022NBTC-90

32 Pin TSOP

(Normal Type)

MX29F022NBTC-12

120

32 Pin TSOP

(Normal Type)

MX29F022NBQC-70

32 Pin PLCC

MX29F022NBQC-90

32 Pin PLCC

MX29F022NBQC-12

120

32 Pin PLCC

P/N:PM0556

REV. 1.3, NOV. 11, 2002

MX29F022/022NT/B

MIN.

MAX.

Input Voltage with respect to GND on all pins except I/O pins

-1.0V

13.5V

Input Voltage with respect to GND on all I/O pins

-1.0V

Vcc + 1.0V

Current

-100mA

+100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

LIMITS

PARAMETER

MIN.

TYP.(2)

MAX.(3)

UNITS

Sector Erase Time

Chip Erase Time

Byte Programming Time

210

Chip Programming Time

3.5

10.5

sec

Erase/Program Cycles

100,000

Cycles

LATCH-UP CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE (1)

Note:

1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25

C,5V.

3.Maximum value measured at 25

C,4.5V.

PARAMETER

MIN.

UNIT

Data Retention Time

Years

DATA RETENTION

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 29F022T-90