1
P/N:PM0742
REV. 1.4, JUL. 04, 2003
MX29LV320T/B
32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES
4,194,304 x 8 / 2,097,152 x 16 switchable
Sector Structure
- 8K-Byte x 8 and 64K-Byte x 63
Extra 64K-Byte sector for security
- Features factory locked and identifiable, and cus-
tomer lockable
Twenty-Four Sector Groups
- Provides sector group protect function to prevent pro-
gram or erase operation in the protected sector group
- Provides chip unprotect function to allow code chang-
ing
- Provides temporary sector group unprotect function
for code changing in previously protected sector groups
Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program opera-
tions
Latch-up protected to 250mA from -1V to Vcc + 1V
Low Vcc write inhibit is equal to or less than 1.4V
Compatible with JEDEC standard
- Pinout and software compatible to single power sup-
ply Flash
PERFORMANCE
High Performance
- Fast access time: 70/90/120ns
- Fast program time: 7us/word typical utilizing acceler-
ate function
- Fast erase time: 1.6s/sector, 112s/chip (typical)
Low Power Consumption
- Low active read current: 10mA (typical) at 5MHz
- Low standby current: 200nA (typical)
Minimum 100,000 erase/program cycle
10-year data retention
SOFTWARE FEATURES
Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from
or program data to another sector which is not being
erased
Status Reply
- Data polling & Toggle bits provide detection of pro-
gram and erase operation completion
Support Common Flash Interface (CFI)
HARDWARE FEATURES
Ready/Busy (RY/BY) Output
- Provides a hardware method of detecting program
and erase operation completion
Hardware Reset (RESET) Input
- Provides a hardware method to reset the internal state
machine to read mode
WP/ACC input pin
- Provides accelerated program capability
PACKAGE
48-Pin TSOP
48-Ball CSP
GENERAL DESCRIPTION
The MX29LV320T/B is a 32-mega bit Flash memory or-
ganized as 4M bytes of 8 bits and 2M words of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29LV320T/B is packaged in 48-pin TSOP and
48-ball CSP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.
The standard MX29LV320T/B offers access time as fast
as 70ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29LV320T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV320T/B uses a command register to manage
this functionality.
MXIC Flash technology reliably stores memory
contents even after 100,000 erase and program
cycles. The MXIC cell is designed to optimize the
erase and program mechanisms. In addition, the
combination of advanced tunnel oxide processing
and low internal electric fields for erase and
programming operations produces reliable cycling.
2
P/N:PM0742
REV. 1.4, JUL. 04, 2003
MX29LV320T/B
AUTOMATIC PROGRAMMING
The MX29LV320T/B is byte/word programmable using
the Automatic Programming algorithm. The Automatic
Programming algorithm makes the external system do
not need to have time out sequence nor to verify the
data programmed. The typical chip programming time at
room temperature of the MX29LV320T/B is less than 36
seconds.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 un-
lock write cycle and A0H) and a program command (pro-
gram data and address). The device automatically times
the programming pulse width, provides the program veri-
fication, and counts the number of sequences. A status
bit similar to DATA polling and a status bit toggling be-
tween consecutive read cycles, provide feedback to the
user as to the status of the programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 50 seconds. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29LV320T/B is sector(s) erasable using
MXIC's Auto Sector Erase algorithm. Sector erase
modes allow sectors of the array to be erased in one
erase cycle. The Automatic Sector Erase algorithm
automatically programs the specified sector(s) prior to
electrical erase. The timing and verification of
electrical erase are controlled internally within the
device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand-
ard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia-
bility, and cost effectiveness. The MX29LV320T/B elec-
trically erases all bits simultaneously using Fowler-Nord-
heim tunneling. The bytes/words are programmed by
using the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
The MX29LV320T/B uses a 2.7V to 3.6V VCC
supply to perform the High Reliability Erase and
auto Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamperes on address and data pin from -1V to
VCC + 1V.
3
P/N:PM0742
REV. 1.4, JUL. 04, 2003
MX29LV320T/B
PIN CONFIGURATION
48 TSOP
SYMBOL
PIN NAME
A0~A20
Address Input
Q0~Q14
15 Data Inputs/Outputs
Q15/A-1
Q15(Data Input/Output, word mode)
A-1(LSB Address Input, byte mode)
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
BYTE
Word/Byte Selection Input
RESET
Hardware Reset Pin, Active Low
RY/BY
Read/Busy Output
VCC
3.0 volt-only single power supply
WP/ACC
Hardware Write Protect/Acceleration
Pin
GND
Device Ground
NC
Pin Not Connected Internally
PIN DESCRIPTION
LOGIC SYMBOL
48-Ball CSP 8mm x 9mm (Ball Pitch = 0.8 mm), Top View, Balls Facing Down
A
B
C
D
E
F
G
H
6
A13
A12
A14
A15
A16
BYTE
Q15/A-1 GND
5
A9
A8
A10
A11
Q7
Q14
Q13
Q6
4
WE
RESET
NC
A19
Q5
Q12
Vcc
Q4
3
RY/BY WP/ACC
A18
A20
Q2
Q10
Q11
Q3
2
A7
A17
A6
A5
Q0
Q8
Q9
Q1
1
A3
A4
A2
A1
A0
CE
OE
GND
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
NC
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29LV320T/B
16 or 8
Q0-Q15
(A-1)
RY/BY
A0-A20
WP/ACC
CE
OE
WE
RESET
BYTE
21
PDF 
ZIP
