P/N:PM1062

REV. 1.3, DEC. 20, 2004

MX29LV800BT/BB

8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE

3V ONLY FLASH MEMORY

and erase operation completion.

· Ready/Busy# pin (RY/BY#)

- Provides a hardware method of detecting program or
erase operation completion.

· Sector protection

- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotected allows code changes
in previously locked sectors.

· CFI (Common Flash Interface) compliant

- Flash device parameters stored on the device and
provide the host system to access

· 100,000 minimum erase/program cycles
· Latch-up protected to 100mA from -1V to VCC+1V
· Boot Sector Architecture

- T = Top Boot Sector
- B = Bottom Boot Sector

· Package type:

- 44-pin SOP
- 48-pin TSOP
- 48-pin CSP

· Compatibility with JEDEC standard

- Pinout and software compatible with single-power
supply Flash

· 10 years data retention

FEATURES

· Extended single - supply voltage range 2.7V to 3.6V
· 1,048,576 x 8/524,288 x 16 switchable
· Single power supply operation

- 3.0V only operation for read, erase and program
operation

· Fast access time: 70/90ns
· Low power consumption

- 20mA maximum active current
- 0.2uA typical standby current

· Command register architecture

- Byte/word Programming (9us/11us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)

· Fully compatible with MX29LV800T/B device
· Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address

· Erase suspend/Erase Resume

- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.

· Status Reply

- Data# polling & Toggle bit for detection of program

GENERAL DESCRIPTION

The MX29LV800BT/BB is a 8-mega bit Flash memory
organized as 1M bytes of 8 bits or 512K words of 16
bits. MXIC's Flash memories offer the most cost-effec-
tive and reliable read/write non-volatile random access
memory. The MX29LV800BT/BB is packaged in 44-pin
SOP, 48-pin TSOP, and 48-ball CSP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.

The standard MX29LV800BT/BB offers access time as
fast as 70ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29LV800BT/BB has separate chip enable
(CE#) and output enable (OE#) controls.

MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV800BT/BB uses a command register to man-
age this functionality. The command register allows for

100% TTL level control inputs and fixed power supply
levels during erase and programming, while maintaining
maximum EPROM compatibility.

MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV800BT/BB uses a 2.7V~3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.

The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

PIN CONFIGURATIONS

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A18

Address Input

Q0~Q14

Data Input/Output

Q15/A-1

Q15(Word mode)/LSB addr(Byte mode)

CE#

Chip Enable Input

WE#

Write Enable Input

BYTE#

Word/Byte Selection input

RESET#

Hardware Reset Pin

OE#

Output Enable Input

RY/BY#

Ready/Busy Output

VCC

Power Supply Pin (2.7V~3.6V)

GND

Ground Pin

48 TSOP (Standard Type) (12mm x 20mm)

48-Ball CSP Ball Pitch = 0.8 mm, Top View, Balls Facing Down

44 SOP(500 mil)

A13

A12

A14

A15

A16

BYTE#

Q15/A-1 GND

A10

A11

Q14

Q13

WE#

RESET# NC

Q12

Vcc

RY/BY# NC

A18

Q10

Q11

A17

CE#

OE#

GND

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RY/BY#

A18
A17

A7
A6
A5
A4
A3
A2
A1
A0

CE#

GND

OE#

Q0
Q8
Q1
Q9
Q2

Q10

Q11

RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC

MX29L

V800BT/BB

A15
A14
A13
A12
A11
A10

A9
A8

NC
NC

WE#

RESET#

NC
NC

RY/BY#

A18
A17

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

MX29LV800BT/BB

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

BLOCK STRUCTURE

TABLE 1: MX29LV800BT SECTOR ARCHITECTURE

Note: Byte mode:address range A18:A-1, word mode:address range A18:A0.

Sector Sector Size

Address range

Sector Address

Byte Mode Word Mode

Byte Mode (x8)

Word Mode (x16)

A18 A17 A16 A15 A14 A13 A12

SA0

64Kbytes

32Kwords

00000h-0FFFFh

00000h-07FFFh

SA1

64Kbytes

32Kwords

10000h-1FFFFh

08000h-0FFFFh

SA2

64Kbytes

32Kwords

20000h-2FFFFh

10000h-17FFFh

SA3

64Kbytes

32Kwords

30000h-3FFFFh

18000h-1FFFFh

SA4

64Kbytes

32Kwords

40000h-4FFFFh

20000h-27FFFh

SA5

64Kbytes

32Kwords

50000h-5FFFFh

28000h-2FFFFh

SA6

64Kbytes

32Kwords

60000h-6FFFFh

30000h-37FFFh

SA7

64Kbytes

32Kwords

70000h-7FFFFh

38000h-3FFFFh

SA8

64Kbytes

32Kwords

80000h-8FFFFh

40000h-47FFFh

SA9

64Kbytes

32Kwords

90000h-9FFFFh

48000h-4FFFFh

SA10

64Kbytes

32Kwords

A0000h-AFFFFh

50000h-57FFFh

SA11

64Kbytes

32Kwords

B0000h-BFFFFh

58000h-5FFFFh

SA12

64Kbytes

32Kwords

C0000h-CFFFFh

60000h-67FFFh

SA13

64Kbytes

32Kwords

D0000h-DFFFFh

68000h-6FFFFh

SA14

64Kbytes

32Kwords

E0000h-EFFFFh

70000h-77FFFh

SA15

32Kbytes

16Kwords

F0000h-F7FFFh

78000h-7BFFFh

SA16

8Kbytes

4Kwords

F8000h-F9FFFh

7C000h-7CFFFh

SA17

8Kbytes

4Kwords

FA000h-FBFFFh

7D000h-7DFFFh

SA18

16Kbytes

8Kwords

FC000h-FFFFFh

7E000h-7FFFFh

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

Sector Sector Size

Address range

Sector Address

Byte Mode Word Mode

Byte Mode (x8)

Word Mode (x16)

A18 A17 A16 A15 A14 A13 A12

SA0

16Kbytes

8Kwords

00000h-03FFFh

00000h-01FFFh

SA1

8Kbytes

4Kwords

04000h-05FFFh

02000h-02FFFh

SA2

8Kbytes

4Kwords

06000h-07FFFh

03000h-03FFFh

SA3

32Kbytes

16Kwords

08000h-0FFFFh

04000h-07FFFh

SA4

64Kbytes

32Kwords

10000h-1FFFFh

08000h-0FFFFh

SA5

64Kbytes

32Kwords

20000h-2FFFFh

10000h-17FFFh

SA6

64Kbytes

32Kwords

30000h-3FFFFh

18000h-1FFFFh

SA7

64Kbytes

32Kwords

40000h-4FFFFh

20000h-27FFFh

SA8

64Kbytes

32Kwords

50000h-5FFFFh

28000h-2FFFFh

SA9

64Kbytes

32Kwords

60000h-6FFFFh

30000h-37FFFh

SA10

64Kbytes

32Kwords

70000h-7FFFFh

38000h-3FFFFh

SA11

64Kbytes

32Kwords

80000h-8FFFFh

40000h-47FFFh

SA12

64Kbytes

32Kwords

90000h-9FFFFh

48000h-4FFFFh

SA13

64Kbytes

32Kwords

A0000h-AFFFFh

50000h-57FFFh

SA14

64Kbytes

32Kwords

B0000h-BFFFFh

58000h-5FFFFh

SA15

64Kbytes

32Kwords

C0000h-CFFFFh

60000h-67FFFh

SA16

64Kbytes

32Kwords

D0000h-DFFFFh

68000h-6FFFFh

SA17

64Kbytes

32Kwords

E0000h-EFFFFh

70000h-77FFFh

SA18

64Kbytes

32Kwords

F0000h-FFFFFh

78000h-7FFFFh

TABLE 2: MX29LV800BB SECTOR ARCHITECTURE

Note: Byte mode:address range A18:A-1, word mode:address range A18:A0.

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

AUTOMATIC PROGRAMMING

The MX29LV800BT/BB is byte programmable using the
Automatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature of the MX29LV800BT/BB is less than 10
seconds.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
The device provides an unlock bypass mode with faster
programming. Only two write cycles are needed to pro-
gram a word or byte, instead of four. A status bit similar
to DATA# polling and a status bit toggling between con-
secutive read cycles, provide feedback to the user as
to the status of the programming operation. Refer to write
operation status, table 8, for more information on these
status bits.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 25 second. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29LV800BT/BB is sector(s) erasable using
MXIC's Auto Sector Erase algorithm. The Automatic
Sector Erase algorithm automatically programs the
specified sector(s) prior to electrical erase. The timing
and verification of electrical erase are controlled inter-
nally within the device. An erase operation can erase
one sector, multiple sectors, or the entire device.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the erasing operation.

Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE# or CE#, whichever
happens first.

MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29LV800BT/BB
electrically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.

During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.

AUTOMATIC SELECT

The auto select mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on Q7~Q0. This mode is
mainly adapted for programming equipment on the de-
vice to be programmed with its programming algorithm.
When programming by high voltage method, automatic
select mode requires VID (11.5V to 12.5V) on address
pin A9 and other address pin A6, A1 and A0 as referring
to Table 3. In addition, to access the automatic select
codes in-system, the host can issue the automatic se-

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

lect command through the command register without
requiring VID, as shown in table 5.

To verify whether or not sector being protected, the sec-
tor address must appear on the appropriate highest or-
der address bit (see Table 1 and Table 2). The rest of
address bits, as shown in table 3, are don't care. Once
all necessary bits have been set as required, the pro-
gramming equipment may read the corresponding iden-
tifier code on Q7~Q0.

A18 A11

A5 A1 A0

Description

Mode CE# OE# WE#

Q15~Q0

A12 A10

Manufacturer Code

VID

C2H

Read

Device ID

Word

VID

22DAH

Silicon (Top Boot Block)

Byte

VID

XXDAH

Device ID

Word

VID

225BH

(Bottom Boot Block)

Byte

VID

XX5BH

XX01H

Sector Protection

VID

(protected)

Verification

XX00H

(unprotected)

TABLE 3. MX29LV800BT/BB AUTO SELECT MODE OPERATION

NOTE:SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

QUERY COMMAND AND COMMON FLASH

INTERFACE (CFI) MODE ( for MX29LV800BT/
BB)

MX29LV800BT/BB is capable of operating in the CFI
mode. This mode all the host system to determine the
manufacturer of the device such as operating param-
eters and configuration. Two commands are required in
CFI mode. Query command of CFI mode is placed first,
then the Reset command exits CFI mode. These are

described in Table 6.

The single cycle Query command is valid only when the
device is in the Read mode, including Erase Suspend,
Standby mode, and Read ID mode; however, it is ig-
nored otherwise.

The Reset command exits from the CFI mode to the
Read mode, or Erase Suspend mode, or read ID mode.
The command is valid only when the device is in the
CFI mode.

TABLE 4-1. CFI mode: Identification Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(Byte Mode)

(Word Mode)

Query-unique ASCII string "QRY"

0051

0052

0059

Primary vendor command set and control interface ID code

0002

0000

Address for primary algorithm extended query table

0040

0000

Alternate vendor command set and control interface ID code (none)

0000

Address for secondary algorithm extended query table (none)

0000

TABLE 4-2. CFI Mode: System Interface Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(Byte Mode)

(Word Mode)

VCC supply, minimum (2.7V)

0027

VCC supply, maximum (3.6V)

0036

VPP supply, minimum (none)

0000

VPP supply, maximum (none)

0000

Typical timeout for single word/byte write (2

us)

0004

Typical timeout for Minimum size buffer write (2

us)

0000

Typical timeout for individual block erase (2

ms)

000A

Typical timeout for full chip erase (2

ms)

0000

Maximum timeout for single word/byte write times (2

X Typ)

0005

Maximum timeout for buffer write times (2

X Typ)

0000

Maximum timeout for individual block erase times (2

X Typ)

0004

Maximum timeout for full chip erase times (not supported)

0000

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

TABLE 4-3. CFI Mode: Device Geometry Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(Byte Mode)

(Word Mode)

Device size (2

bytes)

0014

Flash device interface code (refer to the CFI publication 100)

0002

0000

Maximum number of bytes in multi-byte write (not supported)

0000

Number of erase block regions

0004

Erase block region 1 information (refer to the CFI publication 100)

0000

0040

0000

Erase block region 2 information

0001

0000

0020

0000

Erase block region 3 information

0000

0080

0000

Erase block region 4 information

000E

0000

0001

TABLE 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(Byte Mode)

(Word Mode)

Query-unique ASCII string "PRI"

0050

0052

0049

Major version number, ASCII

0031

Minor version number, ASCII

0030

Address sensitive unlock (0=required, 1= not required)

0000

Erase suspend (2= to read and write)

0002

Sector protect (N= # of sectors/group)

0001

Temporary sector unprotected (1=supported)

0001

Sector protect/unprotected scheme

0004

Simultaneous R/W operation (0=not supported)

0000

Burst mode type (0=not supported)

0000

Page mode type (0=not supported)

0000

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

First Bus

Second Bus

Third Bus

Fourth Bus

Fifth Bus

Sixth Bus

Command

Bus

Cycle

Cycle Addr

Data Addr

Data

Addr

Data Addr

Data

Addr

Data Addr

Data

Reset

XXXH F0H

Read

Read Silicon ID

Word

555H AAH 2AAH

55H

555H

90H ADI

DDI

Byte

AAAH AAH 555H

55H

AAAH

90H ADI

DDI

Sector Protect

Word

555H AAH 2AAH

55H

555H

90H (SA)

XX00H

Verify

x02H

XX01H

Byte

AAAH AAH 555H

55H

AAAH

90H (SA)

00H

x04H

01H

Program

Word

555H AAH 2AAH

55H

555H

A0H PA

Byte

AAAH AAH 555H

55H

AAAH

A0H PA

Chip Erase

Word

555H AAH 2AAH

55H

555H

80H 555H

AAH

2AAH 55H

555H 10H

Byte

AAAH AAH 555H

55H

AAAH

80H AAAH AAH

555H

55H

AAAH 10H

Sector Erase

Word

555H AAH 2AAH

55H

555H

80H 555H

AAH

2AAH 55H

30H

Byte

AAAH AAH 555H

55H

AAAH

80H AAAH AAH

555H

55H

30H

Sector Erase Suspend

XXXH B0H

Sector Erase Resume

XXXH 30H

CFI Query

Word

55H

Byte

AAH

TABLE 5. MX29LV800BT/BB COMMAND DEFINITIONS

Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A18=do not care.

(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, 22DA/DA(Top), and 225B/5B(Bottom) for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.
SA = Address of the sector.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or

555H to Address A10~A-1 in byte mode.
Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).
Write Sequence may be initiated with A11~A18 in either state.

4. For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,

it means the sector is still not being protected.

5. Any number of CFI data read cycle are permitted.

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

TABLE 6. MX29LV800BT/BB BUS OPERATION

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 5.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 5 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H/XX00H means unprotected.

Code=01H/XX01H means protected.

6. A18~A12=Sector address for sector protect.

7. The sector protect and chip unprotected functions may also be implemented via programming equipment.

sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them
in the improper sequence will reset the device to the
read mode. Table 5 defines the valid register command

ADDRESS

Q8~Q15

DESCRIPTION

CE# OE# WE# RESET# A18 A10 A9

A6 A5 A1 A0

Q0~Q7

BYTE

A12 A11

=VIH

=VIL

Read

AIN

Dout

Q8~Q14

=High Z

Q15=A-1

Write

AIN

DIN(3)

DIN

Reset

High Z

Temporary sector unlock

VID

AIN

DIN

High Z

Output Disable

High Z

Standby

Vcc

High Z

0.3V

Sector Protect

VID

DIN

Chip Unprotected

VID

DIN

Sector Protection Verify

VID

CODE(5)

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

REQUIREMENTS FOR READING ARRAY
DATA

To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should
remain at VIH.

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No command
is necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid address
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read
access until the command register contents are altered.

WRITE COMMANDS/COMMAND SEQUENCES

To program data to the device or erase sectors of memory
, the system must drive WE# and CE# to VIL, and OE#
to VIH.

The device features an Unlock Bypass mode to facilitate
faster programming. Once the device enters the Unlock
Bypass mode, only two write cycles are required to
program a byte, instead of four. The "byte Program
Command Sequence" section has details on
programming data to the device using both standard and
Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors
, or the entire device. Table indicates the address space
that each sector occupies. A "sector address" consists
of the address bits required to uniquely select a sector.
The "Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 1 defines the valid register command
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device
to reading array data. Section has details on erasing a
sector or the entire chip, or suspending/resuming the
erase operation.

After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal
register (which is separate from the memory array) on
Q7-Q0. Standard read cycle timings apply in this mode.

Refer to the Autoselect Mode and Autoselect Command
Sequence section for more information.

ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.

STANDBY MODE

When using both pins of CE# and RESET#, the device
enter CMOS Standby with both pins held at Vcc

0.3V.

If CE# and RESET# are held at VIH, but not within the
range of VCC ±

0.3V, the device will still be in the standby

mode, but the standby current will be larger. During Auto
Algorithm operation, Vcc active current (Icc2) is required
even CE# = "H" until the operation is completed. The
device can be read with standard access time (tCE) from
either of these standby modes, before it is ready to read
data.

OUTPUT DISABLE

With the OE# input at a logic high level (VIH), output
from the devices are disabled. This will cause the output
pins to be in a high impedance state.

RESET# OPERATION

The RESET# pin provides a hardware method of resetting
the device to reading array data. When the RESET# pin
is driven low for at least a period of tRP, the device
immediately terminates any operation in progress, tri-
states all output pins, and ignores all read/write
commands for the duration of the RESET# pulse. The
device also resets the internal state machine to reading
array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another
command sequence, to ensure data integrity

Current is reduced for the duration of the RESET# pulse.
When RESET# is held at VSS

0.3V, the device draws

CMOS standby current (ICC4). If RESET# is held at VIL
but not within VSS

0.3V, the standby current will be

greater.

The RESET# pin may be tied to system reset circuitry.
A system reset would that also reset the Flash memory,
enabling the system to read the boot-up firmware from

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.

If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.

SILICON-ID READ COMMAND

Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage (VID). However, multiplexing high volt-
age onto address lines is not generally desired system
design practice.

The MX29LV800BT/BB contains a Silicon-ID-Read op-
eration to supple traditional PROM programming meth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis-
ter. Following the command write, a read cycle with
A1=VIL, A0=VIL retrieves the manufacturer code of C2H/
00C2H. A read cycle with A1=VIL, A0=VIH returns the
device code of DAH/22DAH for MX29LV800BT, 5BH/
225BH for MX29LV800BB.

SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS

Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H
or sector erase command 30H.

The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required).

If the Erase operation was unsuccessful, the data on
Q5 is "1" (see Table 8), indicating the erase operation
exceed internal timing limit.

The automatic erase begins on the rising edge of the
last WE# or CE# pulse, whichever happens first in the
command sequence and terminates when the data on
Q7 is "1" at which time the device returns to the Read
mode, or the data on Q6 stops toggling for two consecu-
tive read cycles at which time the device returns to the
Read mode.

the Flash memory.

If RESET# is asserted during a program or erase
operation, the RY/BY# pin remains a "0" (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is completed within a
time of tREADY (not during Embedded Algorithms). The
system can read data tRH after the RESET# pin returns
to VIH.

Refer to the AC Characteristics tables for RESET#
parameters and to Figure 22 for the timing diagram.

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

READING ARRAY DATA

The device is automatically set to reading array data
after device power-up. No commands are required to re-
trieve data. The device is also ready to read array data
after completing an Automatic Program or Automatic
Erase algorithm.

After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. Af-
ter completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See Erase Suspend/Erase
Resume Commands" for more information on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if Q5 goes high, or
while in the autoselect mode. See the "Reset Command"
section, next.

RESET COMMAND

Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don't care
for this command.

The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.

The reset command may be written between the se-
quence cycles in a program command sequence before
programming begins. This resets the device to reading
array data (also applies to programming in Erase Sus-
pend mode). Once programming begins, however, the
device ignores reset commands until the operation is
complete.

The reset command may be written between the se-
quence cycles in an SILICON ID READ command se-
quence. Once in the SILICON ID READ mode, the reset
command must be written to return to reading array data
(also applies to SILICON ID READ during Erase Sus-
pend).

If Q5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).

Pins

Q15~Q8 Q7

Q2 Q1

Code (Hex)

Manufacture code

Word VIL

VIL

00H

00C2H

Byte

VIL

C2H

Device code

Word VIH

VIL

22H

22DAH

for MX29LV800BT

Byte

VIH

VIL

DAH

Device code

Word VIH

VIL

22H

225BH

for MX29LV800BB

Byte

VIH

VIL

5BH

Sector Protection

Word X

VIH X

01H (Protected)

Verification

Byte X

VIH X

00H (Unprotected)

TABLE 7. SILICON ID CODE

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the de-
vice to be entirely pre-programmed prior to executing
the Automatic Sector Erase Set-up command and Au-
tomatic Sector Erase command. Upon executing the
Automatic Sector Erase command, the device will auto-
matically program and verify the sector(s) memory for
an all-zero data pattern. The system is not required to
provide any control or timing during these operations.

When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when either the data on Q7 is "1" at which time the de-
vice returns to the Read mode, or the data on Q6 stops
toggling for two consecutive read cycles at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.

When using the Automatic sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two "un-
lock" write cycles. These are followed by writing the
set-up command 80H. Two more "unlock" write cycles
are then followed by the sector erase command 30H.
The sector address is latched on the falling edge of WE#
or CE#, whichever happens later, while the command
(data) is latched on the rising edge of WE# or CE#,
whichever happens first. Sector addresses selected are
loaded into internal register on the sixth falling edge of
WE# or CE#, whichever happens later. Each succes-
sive sector load cycle started by the falling edge of WE#
or CE#, whichever happens later must begin within 50us
from the rising edge of the preceding WE# or CE#, which-
ever happens first. Otherwise, the loading period ends
and internal auto sector erase cycle starts. (Monitor Q3
to determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command other
than Sector Erase (30H) or Erase Suspend (B0H) during
the time-out period resets the device to read mode.

ERASE SUSPEND

This command only has meaning while the state ma-
chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase operation. When the Erase Suspend Com-
mand is issued during the sector erase operation, the

device requires a maximum 20us to suspend the sector
erase operation. However, when the Erase Suspend com-
mand is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation. After this command has
been executed, the command register will initiate erase
suspend mode. The state machine will return to read
mode automatically after suspend is ready. At this time,
state machine only allows the command register to re-
spond to Erase Resume, program data to , or read data
from any sector not selected for erasure.

The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro-
gram operation is complete, the system can once again
read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing. However,
a delay time must be required after the erase resume
command (1.5ms for MX29LV800BT/BB), if the system
implements an endless erase suspend/resume loop, or
the number of erase suspend/resume is exceeded 1024
times. The erase times will be expended if the erase
behavior always be suspended. (Please refer to MXIC
Flash Application Note for details.)

WORD/BYTE PROGRAM COMMAND SEQUENCE

The device programs one byte of data for each program
operation. The command sequence requires four bus
cycles, and is initiated by writing two unlock write cycles,
followed by the program set-up command. The program
address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is

not

required to provide further controls or timings. The device
automatically generates the program pulses and verifies
the programmed cell margin. Table 1 shows the address
and data requirements for the byte program command
sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

WRITE OPERATION STATUS

The device provides several bits to determine the sta-
tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/
BY#. Table 10 and the following subsections describe
the functions of these bits. Q7, RY/BY#, and Q6 each
offer a method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.

Q7: Data# Polling

The DATA# polling bit, Q7, indicates to the host system
whether an Automatic Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend. DATA#
polling is valid after the rising edge of the final WE# pulse
in the program or erase command sequence.

During the Automatic Program algorithm, the device out-
puts on Q7 the complement of the datum programmed
to Q7. This Q7 status also applies to programming dur-
ing Erase Suspend. When the Automatic Program algo-
rithm is complete, the device outputs the datum pro-
grammed to Q7. The system must provide the program
address to read valid status information on Q7. If a pro-
gram address falls within a protected sector, DATA# poll-
ing on Q7 is active for approximately 1 us, then the de-
vice returns to reading array data.

During the Automatic Erase algorithm, DATA# polling pro-
duces a "0" on Q7. When the Automatic Erase algo-

determine the status of the program operation by using
Q7, Q6, or RY/BY#. See "Write Operation Status" for
information on these status bits.

Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming
operation. The Byte Program command sequence should
be reinitiated once the device has reset to reading array
data, to ensure data integrity.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may halt the
operation and set Q5 to "1" ," or cause the DATA# polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
still "0". Only erase operations can convert a "0" to a
"1".

rithm is complete, or if the device enters the Erase Sus-
pend mode, DATA# polling produces a "1" on Q7. This is
analogous to the complement/true datum out-put de-
scribed for the Automatic Program algorithm: the erase
function changes all the bits in a sector to "1" prior to
this, the device outputs the "complement," or "0"." The
system must provide an address within any of the sec-
tors selected for erasure to read valid status information
on Q7.

After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DATA# polling on
Q7 is active for approximately 100 us, then the device
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.

When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchronously with Q0-Q6 while Output En-
able (OE#) is asserted low.

RY/BY# : Ready/Busy

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY# status is valid
after the rising edge of the final WE# or CE#, whichever
happens first, in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be
tied together in parallel with a pull-up resistor to VCC.

If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the de-
vice is ready to read array data (including during the
Erase Suspend mode), or is in the standby mode.

Table 8 shows the outputs for RY/BY# during write op-
eration.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-
gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE# or CE#, whichever

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE# or CE# to
control the read cycles. When the operation is complete,
Q6 stops toggling.

After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.

The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus-
pended. When the device is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-sus-
pended. Alternatively, the system can use Q7.

If a program address falls within a protected sector, Q6
toggles for approximately 2 us after the program com-
mand sequence is written, then returns to reading array
data.

Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo-
rithm is complete.

Table 8 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether
that sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE# or CE#, whichever
happens first, in the command sequence.

Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE# or CE# to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-

parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sectors and mode information. Refer to
Table 8 to compare outputs for Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase op-
eration. If it is still toggling, the device did not complete
the operation successfully, and the system must write
the reset command to return to reading array data.

The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta-
tus as described in the previous paragraph. Alterna-
tively, it may choose to perform other system tasks. In
this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation.

Q5
Exceeded Timing Limits

Q5 will indicate if the program or erase time has ex-
ceeded the specified limits (internal pulse count). Under
these conditions Q5 will produce a "1". This time-out
condition indicates that the program or erase cycle was
not successfully completed. Data# Polling and Toggle
Bit are the only operating functions of the device under
this condition.

happens first, in the command sequence (prior to the
program or erase operation), and during the sector time-
out.

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

If this time-out condition occurs during sector erase op-
eration, it specifies that a particular sector is bad and it
may not be reused. However, other sectors are still func-
tional and may be used for the program or erase opera-
tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com-
bination of sectors are bad.

Status

RY/BY#

(Note1)

(Note2)

Byte Program in Auto Program Algorithm

Toggle

N/A

Toggle

Auto Erase Algorithm

Toggle

Erase Suspend Read

N/A Toggle

(Erase Suspended Sector)

Toggle

In Progress

Erase Suspended Mode

Erase Suspend Read

Data

(Non-Erase Suspended Sector)

Erase Suspend Program

Toggle

N/A

Byte Program in Auto Program Algorithm

Toggle

N/A

Toggle

Exceeded
Time Limits Auto Erase Algorithm

Toggle

Erase Suspend Program

Toggle

N/A

TABLE 8. WRITE OPERATION STATUS

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5:Exceeded Timing Limits " for more information.

If this time-out condition occurs during the byte program-
ming operation, it specifies that the entire sector con-
taining that byte is bad and this sector may not be re-
used, (other sectors are still functional and can be re-
used).

The time-out condition will not appear if a user tries to
program a non blank location without erasing. Please
note that this is not a device failure condition since the
device was incorrectly used.

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

POW

ER SUPPLY DECOUPLING

In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND.

POWER-UP SEQUENCE

The MX29LV800BT/BB powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.

TEMPORARY SECTOR UNPROTECTED

This feature allows temporary unprotected of previously
protected sector to change data in-system. The Tempo-
rary Sector Unprotected mode is activated by setting
the RESET# pin to VID(11.5V-12.5V). During this mode,
formerly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET# pin, all the previously protected sectors are
protected again.

SECTOR PROTECTION

The MX29LV800BT/BB features hardware sector pro-
tection. This feature will disable both program and erase
operations for these sectors protected. To activate this
mode, the programming equipment must force VID on
address pin A9 and OE# (suggest VID = 12V). Pro-
gramming of the protection circuitry begins on the falling
edge of the WE# pulse and is terminated on the rising
edge. Please refer to sector protect algorithm and wave-
form.

To verify programming of the protection circuitry, the pro-
gramming equipment must force VID on address pin A9
( with CE# and OE# at VIL and WE# at VIH). When
A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1"
code at device output Q0 for a protected sector. Other-
wise the device will produce 00H for the unprotected
sector. In this mode, the addresses, except for A1, are
don't care. Address locations with A1 = VIL are reserved
to read manufacturer and device codes. (Read Silicon
ID)

It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.

Q3
Sector Erase Timer

After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. DATA# polling
and Toggle Bit are valid after the initial sector erase com-
mand sequence.

If DATA# polling or the Toggle Bit indicates the device
has been written with a valid erase command, Q3 may
be used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by DATA# polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com-
mand has been accepted, the system software should
check the status of Q3 prior to and following each sub-
sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.

DATA PROTECTION

The MX29LV800BT/BB is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transition. During power up the device automatically re-
sets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down tran-
sition or system noise.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE# or WE#
will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# = VIL,
CE# = VIH or WE# = VIH. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.

CHIP UNPROTECTED

The MX29LV800BT/BB also features the chip unpro-
tected mode, so that all sectors are unprotected after
chip unprotected is completed to incorporate any changes
in the code. It is recommended to protect all sectors
before activating chip unprotected mode.

To activate this mode, the programming equipment must
force VID on control pin OE# and address pin A9. The
CE# pins must be set at VIL. Pins A6 must be set to
VIH. Refer to chip unprotected algorithm and waveform
for the chip unprotected algorithm. The unprotection
mechanism begins on the falling edge of the WE# pulse
and is terminated on the rising edge.

It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs (Q0-Q7) for an unprotected sector.

It is noted that all sectors are unprotected after the chip
unprotected algorithm is completed.

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . ..... -65

C to +150

Ambient Temperature

with Power Applied. . . . . . . . . . . . . .... -65

C to +125

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE#, and

RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-
shoot VSS to -2.0 V for periods of up to 20 ns. See
Figure 6. Maximum DC voltage on input or I/O pins is
VCC +0.5 V. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to
20 ns.

2. Minimum DC input voltage on pins A9, OE#, and

RESET# is -0.5 V. During voltage transitions, A9, OE#,
and RESET# may overshoot VSS to -2.0 V for peri-
ods of up to 20 ns. See Figure 6. Maximum DC input
voltage on pin A9 is +12.5 V which may overshoot to
14.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at

a time. Duration of the short circuit should not be
greater than one second.

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.

OPERATING RATINGS

Commercial (C) Devices

Ambient Temperature (T

). . . . . . . . . . . . 0

C to +70

Industrial (I) Devices

Ambient Temperature (T

). . . . . . . . . . -40

C to +85

Supply Voltages

for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

CAPACITANCE TA = 25

C, f = 1.0 MHz

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

CIN1

Input Capacitance

VIN = 0V

CIN2

Control Pin Capacitance

VIN = 0V

COUT

Output Capacitance

VOUT = 0V

NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.

3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.

TABLE 9. DC CHARACTERISTICS

TA = -40

C to 85

C, VCC = 2.7V~3.6V

Symbol

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

ILI

Input Leakage Current

VIN = VSS to VCC

ILIT

A9 Input Leakage Current

VCC=VCC max; A9=12.5V

ILO

Output Leakage Current

VOUT = VSS to VCC, VCC=VCC max

ICC1

VCC Active Read Current

CE#=VIL, OE#=VIH @5MHz

(Byte Mode)

@1MHz

CE#=VIL, OE#=VIH @5MHz

(Word Mode)

@1MHz

ICC2

VCC Active write Current

CE#=VIL, OE#=VIH

ICC3

VCC Standby Current

0.2

CE#; RESET#=VCC

0.3V

ICC4

VCC Standby Current

0.2

RESET#=VSS

0.3V

During Reset

ICC5

Automatic sleep mode

0.2

VIH=VCC

0.3V; VIL=VSS

0.3V

VIL

Input Low Voltage(Note 1)

-0.5

0.8

VIH

Input High Voltage

0.7xVCC

VCC+ 0.3

VID

Voltage for Automatic

Select and Temporary

11.5

12.5

VCC=3.3V

Sector Unprotected

VOL

Output Low Voltage

0.45

IOL = 4.0mA, VCC= VCC min

VOH1

Output High Voltage(TTL)

0.85xVCC

IOH = -2mA, VCC=VCC min

VOH2

Output High Voltage

VCC-0.4

IOH = -100uA, VCC min

(CMOS)

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

29LV800BT/BB-70

29LV800BT/BB-90

SYMBOLPARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT CONDITIONS

tRC

Read Cycle Time (Note 1)

tACC

Address to Output Delay

CE#=OE#=VIL

tCE

CE# to Output Delay

OE#=VIL

tOE

OE# to Output Delay

CE#=VIL

tDF

OE# High to Output Float (Note1)

CE#=VIL

tOEH

Output Enable Read

Hold Time

Toggle and Data# Polling 10

tOH

Address to Output hold

CE#=OE#=VIL

NOTE:

1. Not 100% tested.
2. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.

TEST CONDITIONS:

· Input pulse levels: 0V/3.0V.
· Input rise and fall times is equal to or less than 5ns.
· Output load: 1 TTL gate + 100pF (Including scope and

jig), for 29LV800T/B-90. 1 TTL gate + 30pF (Including
scope and jig) for 29LV800BT/BB-70

· Reference levels for measuring timing: 1.5V.

AC CHARACTERISTICS TA = -40

C to 85

C, VCC = 2.7V~3.6V

TABLE 10. READ OPERATIONS

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

AC CHARACTERISTICS TA = -40

C to 85

C, VCC = 2.7V~3.6V

TABLE 11. Erase/Program Operations

29LV800BT/BB-70

29LV800BT/BB-90

SYMBOL

PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT

tWC

Write Cycle Time (Note 1)

tAS

Address Setup Time

tAH

Address Hold Time

tDS

Data Setup Time

tDH

Data Hold Time

tOES

Output Enable Setup Time

tGHWL

Read Recovery Time Before Write

(OE# High to WE# Low)

tCS

CE# Setup Time

tCH

CE# Hold Time

tWP

Write Pulse Width

tWPH

Write Pulse Width High

tWHWH1

Programming Operation (Note 2)

9/11(TYP.)

(Byte/Word program time)

tWHWH2

Sector Erase Operation (Note 2)

0.7(TYP.)

sec

tVCS

VCC Setup Time (Note 1)

tRB

Recovery Time from RY/BY#

tBUSY

Program/Erase Valid to RY/BY# Delay

tWPP1

Write Pulse Width for Sector Protect

100ns

10us

100ns

10us

(A9, OE# Control)

(Typ.)

tWPP2

Write Pulse Width for Chip Unprotected

100ns

12ms

100ns

12ms

(A9, OE# Control)

(Typ.)

tBAL

Sector Address Load Time

NOTES:

1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

29LV800BT/BB-70

29LV800BT/BB-90

SYMBOL

PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT

tWC

Write Cycle Time (Note 1)

tAS

Address Setup Time

tAH

Address Hold Time

tDS

Data Setup Time

tDH

Data Hold Time

tOES

Output Enable Setup Time

tGHEL

Read Recovery Time Before Write

tWS

WE# Setup Time

tWH

WE# Hold Time

tCP

CE# Pulse Width

tCPH

CE# Pulse Width High

tWHWH1

Programming

Byte

9(Typ.)

Operation(note2)

Word

11(Typ.)

tWHWH2

Sector Erase Operation (note2)

0.7(Typ.)

sec

NOTE:

1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.

AC CHARACTERISTICS TA = -40

C to 85

C, VCC = 2.7V~3.6V

TABLE 12. Alternate CE# Controlled Erase/Program Operations

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

AUTOMATIC PROGRAMMING TIMING WAVEFORM

FIGURE 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM

One byte data is programmed. Verify in fast algorithm
and additional verification by external control are not re-
quired because these operations are executed automati-
cally by internal control circuit. Programming comple-
tion can be verified by DATA# polling and toggle bit check-

ing after automatic programming starts. Device outputs
DATA# during programming and DATA# after program-
ming on Q7. (Q6 is for toggle bit; see toggle bit, DATA#
polling, timing waveform)

tWC

Address

OE#

CE#

A0h

555h

Status

DOUT

NOTES:

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

tAS

tAH

tGHWL

tCH

tWP

tDS

tDH

tWHWH1

Read Status Data (last two cycle)

Program Command Sequence(last two cycle)

tBUSY

tRB

tCS

tWPH

tVCS

WE#

Data

RY/BY#

VCC

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

FIGURE 8. AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Sector indicated by A12 to A18 are erased. External
erase verify is not required because data are verified
automatically by internal control circuit. Erasure comple-
tion can be verified by DATA# polling and toggle bit check-

ing after automatic erase starts. Device outputs 0 dur-
ing erasure and 1 after erasure on Q7. (Q6 is for toggle
bit; see toggle bit, DATA# polling, timing waveform)

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

tWC

Address

OE#

CE#

55h

2AAh

Sector

Address 1

Sector

Address 0

30h

Progress Complete

30h

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

Sector

Address n

tAS

tAH

tBAL

tGHWL

tCH

tWP

tDS tDH

tWHWH2

Read Status Data

Erase Command Sequence(last two cycle)

tBUSY

tRB

tCS

tWPH

tVCS

WE#

Data

RY/BY#

VCC

30h

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

LIMITS

PARAMETER

MIN.

TYP.(2)

MAX.(3)

UNITS

Sector Erase Time

0.7

sec

Chip Erase Time

sec

Byte Programming Time

300

Word Programming Time

360

Chip Programming Time

Byte Mode

sec

Word Mode

5.8

sec

Erase/Program Cycles

100,000

Cycles

TABLE 16. ERASE AND PROGRAMMING PERFORMANCE (1)

Note:

1. Not 100% Tested, Excludes external system level over head.
2. Typical values measured at 25

C, 3V.

3. Maximum values measured at 25

C, 2.7V.

MIN.

MAX.

Input Voltage with respect to GND on ACC, OE#, RESET#, A9

-1.0V

12.5V

Input Voltage with respect to GND on all power pins, Address pins, CE# and WE#

-1.0V

VCC + 1.0V

Input Voltage with respect to GND on all I/O pins

-1.0V

VCC + 1.0V

Current

-100mA

+100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

TABLE 17. LATCH-UP CHARACTERISTICS

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

ORDERING INFORMATION

PLASTIC PACKAGE

PART NO.

ACCESS

OPERATING

STANDBY

PACKAGE

Remark

TIME (ns)

Current MAX. (mA)

Current MAX. (uA)

MX29LV800BTMC-70

44 Pin SOP

MX29LV800BBMC-70

44 Pin SOP

MX29LV800BTMC-90

44 Pin SOP

MX29LV800BBMC-90

44 Pin SOP

MX29LV800BTTC-70

48 Pin TSOP
(Normal Type)

MX29LV800BBTC-70

48 Pin TSOP
(Normal Type)

MX29LV800BTTC-90

48 Pin TSOP
(Normal Type)

MX29LV800BBTC-90

48 Pin TSOP
(Normal Type)

MX29LV800BTXBC-70

48 Ball CSP
(Ball Size:0.3mm)

MX29LV800BTXBC-90

48 Ball CSP
(Ball Size:0.3mm)

MX29LV800BBXBC-70

48 Ball CSP
(Ball Size:0.3mm)

MX29LV800BBXBC-90

48 Ball CSP
(Ball Size:0.3mm)

MX29LV800BTMI-70

44 Pin SOP

MX29LV800BBMI-70

44 Pin SOP

MX29LV800BTMI-90

44 Pin SOP

MX29LV800BBMI-90

44 Pin SOP

MX29LV800BTTI-70

48 Pin TSOP
(Normal Type)

MX29LV800BBTI-70

48 Pin TSOP
(Normal Type)

MX29LV800BTTI-90

48 Pin TSOP
(Normal Type)

MX29LV800BBTI-90

48 Pin TSOP
(Normal Type)

MX29LV800BTXBI-70

48 Ball CSP

(Ball Size:0.3mm)

MX29LV800BTXBI-90

48 Ball CSP

(Ball Size:0.3mm)

MX29LV800BBXBI-70

48 Ball CSP

(Ball Size:0.3mm)

MX29LV800BBXBI-90

48 Ball CSP

(Ball Size:0.3mm)

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

PART NO.

ACCESS

OPERATING

STANDBY

PACKAGE

Remark

TIME (ns)

Current MAX. (mA)

Current MAX. (uA)

MX29LV800BTXEC-70

48 Ball CSP

(Ball Size:0.4mm)

MX29LV800BTXEC-90

48 Ball CSP

(Ball Size:0.4mm)

MX29LV800BBXEC-70

48 Ball CSP

(Ball Size:0.4mm)

MX29LV800BBXEC-90

48 Ball CSP

(Ball Size:0.4mm)

MX29LV800BTXEI-70

48 Ball CSP

(Ball Size:0.4mm)

MX29LV800BTXEI-90

48 Ball CSP

(Ball Size:0.4mm)

MX29LV800BBXEI-70

48 Ball CSP

(Ball Size:0.4mm)

MX29LV800BBXEI-90

48 Ball CSP

(Ball Size:0.4mm)

MX29LV800BTTC-70G

48 Pin TSOP

PB free

(Normal Type)

MX29LV800BBTC-70G

48 Pin TSOP

PB free

(Normal Type)

MX29LV800BTTC-90G

48 Pin TSOP

PB free

(Normal Type)

MX29LV800BBTC-90G

48 Pin TSOP

PB free

(Normal Type)

MX29LV800BTXBC-70G

48 Ball CSP

PB free

(Ball Size:0.3mm)

MX29LV800BTXBC-90G

48 Ball CSP

PB free

(Ball Size:0.3mm)

MX29LV800BBXBC-70G

48 Ball CSP

PB free

(Ball Size:0.3mm)

MX29LV800BBXBC-90G

48 Ball CSP

PB free

(Ball Size:0.3mm)

MX29LV800BTTI-70G

48 Pin TSOP

PB free

(Normal Type)

MX29LV800BBTI-70G

48 Pin TSOP

PB free

(Normal Type)

MX29LV800BTTI-90G

48 Pin TSOP

PB free

(Normal Type)

MX29LV800BBTI-90G

48 Pin TSOP

PB free

(Normal Type)

P/N:PM1062

MX29LV800BT/BB

REV. 1.3, DEC. 20, 2004

PART NO.

ACCESS

OPERATING

STANDBY

PACKAGE

Remark

TIME (ns)

Current MAX. (mA)

Current MAX. (uA)

MX29LV800BTXBI-70G

48 Ball CSP

PB free

(Ball Size:0.3mm)

MX29LV800BTXBI-90G

48 Ball CSP

PB free

(Ball Size:0.3mm)

MX29LV800BBXBI-70G

48 Ball CSP

PB free

(Ball Size:0.3mm)

MX29LV800BBXBI-90G

48 Ball CSP

PB free

(Ball Size:0.3mm)

MX29LV800BTXEC-70G

48 Ball CSP

PB free

(Ball Size:0.4mm)

MX29LV800BTXEC-90G

48 Ball CSP

PB free

(Ball Size:0.4mm)

MX29LV800BBXEC-70G

48 Ball CSP

PB free

(Ball Size:0.4mm)

MX29LV800BBXEC-90G

48 Ball CSP

PB free

(Ball Size:0.4mm)

MX29LV800BTXEI-70G

48 Ball CSP

PB free

(Ball Size:0.4mm)

MX29LV800BTXEI-90G

48 Ball CSP

PB free

(Ball Size:0.4mm)

MX29LV800BBXEI-70G

48 Ball CSP

PB free

(Ball Size:0.4mm)

MX29LV800BBXEI-90G

48 Ball CSP

PB free

(Ball Size:0.4mm)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 29LV800BT-70

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 29LV800BT-70