P/N:PM0592

REV. 1.8, OCT. 15, 2001

FEATURES

· Bit organization

- 16M x 8 (byte mode)

- 8M x 16 (word mode)

· Fast access time

- Random access: 100ns (max.)

· Current

- Operating:30mA

- Standby:15uA(max.)

PIN CONFIGURATION

MX23L12810

NEW 128M-BIT (16M x 8 / 8M x 16) MASK ROM

FOR TSOP PACKAGE

· Supply voltage

- 2.7V~3.6V for 120ns

- 3.0V~3.6V for 100ns

· Package

- 48 pin TSOP (12mm x 20mm)

- 48 pin TSOP reverse type

· Temperature

- 0 ~ 70

48 TSOP (Top View)

BYTE

A16
A15
A14
A13
A12
A11
A10

A9
A8

A19
A21
A20
A18
A17

A7
A6
A5
A4
A3
A2
A1
A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

VSS
VSS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
VCC
VCC
A22
D11
D3
D10
D2
D9
D1
D8
D0
OE
VSS
VSS

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

MX23L12810

(Normal Type)

BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
A21
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

VSS
VSS

D15/A-1

D14

D13

D12

VCC
VCC

A22

D11

D10

D2
D9
D1
D8
D0

VSS
VSS

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

MX23L12810

(Reverse Type)

PRELIMINARY

P/N:PM0592

MX23L12810

REV. 1.8, OCT. 15, 2001

MODE SELECTION

Byte

D15/A-1

D0~D7

D8~D15

Mode

Power

High Z

Stand-by

High Z

Active

Output

D0~D7

D8~D15

Word

Active

Input

D0~D7

High Z

Byte

Active

BLOCK DIAGRAM

Address

Buffer

Memory

Array

Sense

Amplifier

Word/

Byte

Output

Buffer

D15/(D7)

A0/(A-1)

A22

BYTE

PIN DESCRIPTION

Symbol

Pin Function

A0~A22

Address Inputs

D0~D14

Data Outputs

D15/A-1

D15 (Word Mode)/ LSB Address

(Byte Mode)

Chip Enable Input

Symbol

Pin Function

Output Enable Input

Byte

Word/ Byte Mode Selection

VCC

Power Supply Pin

VSS

Ground Pin

No Connection

ORDER INFORMATION

Part No.

Access Time

Package

VCC

MX23L12810TC-10

100ns

48 pin TSOP

3.0V~3.6V

MX23L12810TC-12

120ns

48 pin TSOP

3.0V~3.6V

*MX23L12810TC-12

120ns

48 pin TSOP

2.7V~3.6V

(under development)

MX23L12810RC-10

100ns

48 pin TSOP (Reverse type)

3.0V~3.6V

MX23L12810RC-12

120ns

48 pin TSOP (Reverse type)

3.0V~3.6V

*MX23L12810RC-12

120ns

48 pin TSOP (Reverse type)

2.7V~3.6V

(under development)

P/N:PM0592

MX23L12810

REV. 1.8, OCT. 15, 2001

ABSOLUTE MAXIMUM RATINGS

Item

Symbol

Ratings

Voltage on any Pin Relative to VSS

VIN

-1.3V to VCC+2.0V (Note)

Ambient Operating Temperature

Topr

C to 70

Storage Temperature

Tstg

-65

C to 125

DC CHARACTERISTICS (Ta = 0

C ~ 70

C, VCC = 2.7V~3.6V)

Item

Symbol

MIN.

MAX.

Conditions

Output High Voltage

VOH

2.4V

IOH = -0.4mA

Output Low Voltage

VOL

0.4V

IOL = 1.6mA

Input High Voltage

VIH

2.2V

VCC+0.3V

Input Low Voltage

VIL

-0.3V

0.2 x VCC

Input Leakage Current

ILI

5uA

0V, VCC

Output Leakage Current

ILO

5uA

0V, VCC

Operating Current

ICC

30mA

f=5MHz, all outputs open,

CE=VIL(Chip Enable)

OE=VIH(Output Disabled)

Standby Current (TTL)

ISTB1

1mA

CE = VIH

Standby Current (CMOS)

ISTB2

15uA

CE>VCC-0.2V

Input Capacitance

CIN

10pF

Ta = 25

C, f = 1MHZ

Output Capacitance

COUT

10pF

Ta = 25

C, f = 1MHZ

Note: Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -1.3V for
periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC+0.5V. During voltage transitions, inputs may overshoot
VCC to VCC+2.0V for periods of up to 20ns.

AC CHARACTERISTICS (Ta = 0

C ~ 70

C, VCC = 2.7V~3.6V)

Item

Symbol

23L12810-10

23L12810-12

23L12810-15

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Read Cycle Time

tRC

100ns

120ns

150ns

Address Access Time

tAA

100ns

120ns

150ns

Chip Enable Access Time

tACE

100ns

120ns

150ns

Output Enable Time

tOE

30ns

50ns

70ns

Output Hold After Address

tOH

0ns

Output High Z Delay

tHZ

20ns

Note: Output high-impedance delay (tHZ) is measured
from OE or CE going high, and this parameter guaran-
teed by design over the full voltage and temperature
operating range - not tested.

P/N:PM0592

MX23L12810

REV. 1.8, OCT. 15, 2001

AC Test Conditions

Input Pulse Levels

0.4V~2.4V

Input Rise and Fall Times

10ns

Input Timing Level

1.4V

Output Timing Level

1.4V

Output Load

See Figure

TIMING DIAGRAM

RANDOM READ

Note:No output loading is present in tester load board.

Active loading is used and under software programming control.

Output loading capacitance includes load board's and all stray capacitance.

DOUT

C<100pF

IOL (load)=1.6mA

IOH (load)=-0.4mA

tACE

tAA

tOH

tHZ

ADD

DATA

Note:CE, OE are enable

VALID

tRC

tOE

P/N:PM0592

MX23L12810

REV. 1.8, OCT. 15, 2001

REVISION HISTORY

Revision #

Description

Page

Date

1.2

DC Characteristics ISTB2(CMOS Standby Current) 5uA-->15uA

DEC/15/1999

1.3

Del Package 44-pin SOP

P1,5

SEP/07/2000

1.4

Modify Current Operating:60mA-->40mA

DEC/12/2000

Modify ICC1:60mA-->40mA, f=5MHz, all outputs open

Del ICC2

1.5

Modify Current Operating:40mA-->50mA

DEC/14/2000

Modify ICC1:40mA-->50mA

1.6

1.Modify Fast access time:120ns-->90ns

JUL/10/2001

2.Modify Operating:50mA-->30mA

3.Added Temperature:0~70

4.Modify Supply Voltage : 3.3V

10%-->2.7V~3.6V

P1,3

5.Modify Package Information

P5,6

1.7

Delete Access Time:90ns

P1,2,3

AUG/28/2001

1.8

1.Add Supply Voltage: 2.7~3.6V for 120ns, 3.0~3.6V for 100ns

P1,2

OCT/15/2001

2.Modify Order Information

3.Add CE=VIL, OE=VIH in DC Characteristics

MX23L12810

ACRONIX

NTERNATIONAL

O.,

TD.

HEADQUARTERS:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

EUROPE OFFICE:

TEL:+32-2-456-8020

FAX:+32-2-456-8021

JAPAN OFFICE:

TEL:+81-44-246-9100

FAX:+81-44-246-9105

SINGAPORE OFFICE:

TEL:+65-348-8385

FAX:+65-348-8096

TAIPEI OFFICE:

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

ACRONIX

MERICA,

NC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

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