FEATURES
Bit organization
- 8M x 16 (byte mode)
- 4M x 32 (double word mode)
Fast access time
- Random access: 120ns (max.)
- Page access: 30ns (max.)
Page Size
- 8 double words per page
PIN CONFIGURATION
70 SSOP
1
P/N:PM0561
REV. 1.5, DEC. 26, 2000
MX23L12822
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
A0
A1
A2
A3
A4
A5
VCC
D0
D16
D1
D17
VSS
VCC
D2
D18
D3
D19
D4
D20
D5
D21
VSS
VCC
D6
D22
D7
D23
VSS
A6
A7
A8
A9
A10
A11
A12
NC
A21
A20
WORD
OE
CE
VSS
D31/A-1
D15
D30
D14
VSS
VCC
D29
D13
D28
D12
D27
D11
D26
D10
VSS
VCC
D25
D9
D24
D8
VCC
A19
A18
A17
A16
A15
A14
A13
MX23L12822
Current
- Operating: 75mA (max.)
- Standby: 15uA (max.)
Supply voltage
- 3.3V
10%
Package
- 70 pin SSOP (500 mil)
- 86 pin TSOP(2)
86 TSOP
128M-BIT (8M x 16 / 4M x 32) MASK ROM WITH PAGE MODE
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
36
37
38
39
40
41
42
43
51
50
49
48
47
46
45
44
NC
A0
A1
A2
A3
A4
A5
NC
NC
VCC
D0
D16
D1
D17
VSS
VCC
D2
D18
D3
D19
NC
NC
D4
D20
D5
D21
VSS
VCC
D6
D22
D7
D23
VSS
A6
A7
A8
A9
A10
A11
A12
A13
NC
NC
NC
NC
NC
A21
A20
WORD
OE
CE
NC
VSS
NC
D31/A-1
D15
D30
D14
VSS
VCC
D29
D13
D28
D12
NC
D27
D11
D26
D10
VSS
VCC
D25
D9
D24
D8
VCC
A19
A18
A17
A16
A15
A14
NC
NC
NC
NC
MX23L12822
2
P/N:PM0561
REV. 1.5, DEC. 26, 2000
MX23L12822
PIN DESCRIPTION
Symbol
Pin Function
A0~A21
Address Inputs
D0~D30
Data Outputs
D31/A-1
D31 (Double Word Mode)/ LSB Address (Word Mode)
CE
Chip Enable Input
OE
Output Enable Input
Word
Double Word/ Word Mode Selection
VCC
Power Supply Pin
VSS
Ground Pin
NC
No Connection
MODE SELECTION
CE
OE
Word
D31/A-1
D0~D15
D16~D31
Mode
Power
H
X
X
X
High Z
High Z
-
Stand-by
L
H
X
X
High Z
High Z
-
Active
L
L
H
Output
D0~D15
D16~D31
Double Word
Active
L
L
L
Input
D0~D15
High Z
Word
Active
ORDER INFORMATION
Part No.
Access Time
Page Access Time
Package
MX23L12822MC-12
120ns
30ns
70 pin SSOP
MX23L12822YC-12
120ns
30ns
86 pin TSOP
3
P/N:PM0561
REV. 1.5, DEC. 26, 2000
MX23L12822
BLOCK DIAGRAM
Address
Buffer
Memory
Array
Page
Buffer
Page
Decoder
Double
Word/
Word
Output
Buffer
D0
D31/(D15)
A3
A21
A0/(A-1)
A2
CE
WORD
OE
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
Voltage on any Pin Relative to VSS
VIN
-1.3V to 2.0V
Ambient Operating Temperature
Topr
0
C to 70
C
Storage Temperature
Tstg
-65
C to 125
C
Note: Minimum DC voltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot VSS
to -1.3V for periods of up to 20ns. Maximum DC voltage
on input or I/O pins is VCC+0.5V. During voltage transi-
tions, input may overshoot VCC to VCC+2.0V for peri-
ods of up to 20ns.
DC CHARACTERISTICS (Ta = 0
C ~ 70
C, VCC = 3.3V
10%)
Item
Symbol
MIN.
MAX.
Conditions
Output High Voltage
VOH
2.4V
-
IOH = -0.4mA
Output Low Voltage
VOL
-
0.4V
IOL = 1.6mA
Input High Voltage
VIH
2.2V
VCC+0.3V
Input Low Voltage
VIL
-0.3V
0.8V
Input Leakage Current
ILI
-
5uA
0V, VCC
Output Leakage Current
ILO
-
5uA
0V, VCC
Operating Current
ICC1
-
75mA
tRC = 120ns, all output open,
with normal sequential access
testing pattern
Standby Current (TTL)
ISTB1
-
1mA
CE = VIH
Standby Current (CMOS)
ISTB2
-
15uA
CE>VCC-0.2V
Input Capacitance
CIN
-
10pF
Ta = 25
C, f = 1MHZ
Output Capacitance
COUT
-
10pF
Ta = 25
C, f = 1MHZ
4
P/N:PM0561
REV. 1.5, DEC. 26, 2000
MX23L12822
AC CHARACTERISTICS (Ta = 0
C ~ 70
C, VCC = 3.3V
10%)
Item
Symbol
23L12822-12
MIN.
MAX.
Read Cycle Time
tRC
120ns
-
Address Access Time
tAA
-
120ns
Chip Enable Access Time
tACE
-
120ns
Page Mode Access Time
tPA
-
30ns
Output Enable Time
tOE
-
30ns
Output Hold After Address
tOH
0ns
-
Output High Z Delay
tHZ
-
20ns
Note:Output high-impedance delay (tHZ) is measured
from OE or CE going high, and this parameter guaran-
teed by design over the full voltage and temperature op-
erating range - not tested.
AC Test Conditions
Input Pulse Levels
0.4V~ 2.4V
Input Rise and Fall Times
10ns
Input Timing Level
1.4V
Output Timing Level
1.4V
Output Load
See Figure
Note:No output loading is present in tester load board.
Active loading is used and under software programming control.
Output loading capacitance includes load board's and all stray capacitance.
DOUT
C<100pF
IOL (load)=1.6mA
IOH (load)=-0.4mA
5
P/N:PM0561
REV. 1.5, DEC. 26, 2000
MX23L12822
TIMING DIAGRAM
RANDOM READ
PAGE READ
ADD
CE
tACE
tOE
tAA
tOH
tHZ
ADD
ADD
ADD
VALID
VALID
VALID
OE
DATA
tRC
A3-A21
(A-1),A0,A1,A2
DATA
Note: CE, OE are enable.
Page size is 8 double words in 32-bit mode, 16 words in 16-bit mode.
VALID ADD
VALID
1'st ADD
2'nd ADD
tPA
tAA
3'rd ADD
VALID
VALID
6
P/N:PM0561
REV. 1.5, DEC. 26, 2000
MX23L12822
Revision History
Revision #
Description
Page
Date
1.3
DC Characteristics ISTB2(CMOS Standby Current) 5uA-->15uA
P3
DEC/15/1999
1.4
Operating Current (ICC1) 60mA-->75mA
P1,3
JAN/14/2000
1.5
Modify Pin Configuration--86 TSOP D31-->D31/A-1
P1
DEC/26/2000
7
MX23L12822
M
ACRONIX
I
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C
O.,
L
TD.
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