PIN DESCRIPTION

REV. 0.8, NOV. 20, 2002

P/N: PM0765

FEATURES

256Kx 8 organization

Single +5V power supply

+12V programming voltage

Fast access time:90/100/120/150 ns

Totally static operation

Completely TTL compatible

Operating current:30mA

Standby current: 100uA

Chip erase time: 1 (typ.)

Chip program time: 12.5 (typ.)

50 minimum erase/program cycles

Typical fast programming cycle duration 10us/byte

Package type:

- 32 pin plastic DIP
- 32 pin PLCC
- 32 pin TSOP
- 32 pin SOP

PIN CONFIGURATIONS

32 PDIP/SOP

32 PLCC

SYMBOL

PIN NAME

A0~A17

Address Input

Q0~Q7

Data Input/Output

Chip Enable Input

Output Enable Input

Write Enable Input

VPP

Program Supply Voltage

No Internal Connection

VCC

Power Supply Pin (+5V)

GND

Ground Pin

MX26C2000B

2M-BIT [256K x 8] CMOS

MULTIPLE-TIME-PROGRAMMABLE-EPROM

ADVANCE INFORMATION

MX26C2000B

VPP

A16

A15

A12

GND

VCC

A17

A14

A13

A11

A10

A14

A13

A11

A10

GND

A12

A15

A16

VPP

VCC

A17

MX26C2000B

32 TSOP

A11

A9
A8

A13
A14
A17

VCC

VPP

A16
A15
A12

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

MX26C2000B

GENERAL DESCRIPTION

The MX26C2000B is a 5V only, 2M-bit, MTP EPROM

(Multiple Time Programmable Read Only Memory). It is
organized as 256K words by 8 bits per word, operates
from a single + 5 volt supply, has a static standby mode,
and features fast single address location programming.
All programming signals are TTL levels, requiring a single
pulse. It is design to be programmed and erased by an

EPROM programmer or on-board. The MX26C2000B
supports a intelligent fast programming algorithm which
can result in programming time of less than one minute.

This MTP EPROM

is packaged in industry standard 32

pin dual-in-line packages, 32 lead PLCC, 32 lead SOP
and 32 lead TSOP packages.

REV. 0.8, NOV. 20, 2002

P/N: PM0765

MX26C2000B

FUNCTIONAL DESCRIPTION

When the MX26C2000B is delivered, or it is erased, the
chip has all 2000K bits in the "ONE", or HIGH state.
"ZEROs" are loaded into the MX26C2000B through the
procedure of programming.

ERASE ALGORITHM

The MX26C2000B do not required preprogramming
before an erase operation. The erase algorithm is a close
loop flow to simultaneously erase all bits in the entire
array. Erase operation starts with the initial erase
operation. Erase verification begins at address 0000H
by reading data FFH from each byte. If any byte fails
to erase. the entire chip is reerased. to a maximum for
30 pulse counts of 100ms duration for each pulse. The
maximum cumulative erase time is 3s. However. the
device is usually erased in no more than 3 pulses. Erase
verification time can be reduced by storing the address
of the last byte that failed. Following the next erase
operation verification may start at the stored address
location. JEDEC standard erase algorithm can also be
used. But erase time will increase by performing the
unnecessary preprogramming.

PROGRAM ALGORITHM

The device is programmed byte by byte. A maximum
of 25 pulses. each of 10us duration is allowed for each
byte being programmed. The byte may be programmed
sequentially or by random. After each program pulse,
a program verify is done to determine if the byte has
been successfully programmed.

Programming then proceeds to the next desired byte
location. JEDEC standard program algorithms can be
used.

RESET

The Reset command initializes the

MTP EPROM

device to the Read mode. In addition, it also provides the
user with a safe method to abort any device operation
(including program or erase). The Reset command must
be written two consecutive times after the set-up Program
command (40H). This will safely abort any previous
operation and initialize the device to the Read mode.

The set-up Program command (40H) is the only command
that requires a two sequence reset cycle. The first Reset
command is interpreted as program data. How ever, FFH
data is considered null data during programming operations
(memory cells are only programmed from logica "1" to
"0". The second Reset command safely aborts the
programming operation and resets the device to the
Read mode.

This detailed information is for your reference. It may
prove esier to always issue the Reset command two
consecutive times. This eliminates the need to determine
if you are in the set-up Program state or not.

SET-UP PROGRAM/PROGRAM

A three-step sequence of commands is required to
perform a complete program operation: Set Up Program-
Program-Program Verify. The device is bulk erased and
byte by byte programming. The command 40H is written
to the command register to initiate Set Up Program
operation. Address and data to be programmed into the
byte are provided on the second WE pulse. Addresses
are latched on the falling edge of the WE pulse, data are
latched on the rising edge of the WE pulse. Program
operation begins on the rising edge of the second WE
pulse, and terminate of the next rising edge of the WE
pulse. Refer to AC Characteristics and Waveforms for
specific timing parameters.

COMMAND REGISTER

When high voltage is applied to V

the command

register is enabled. Read, write, standby, output disable
modes are available. The read, erase, erase verify,
program, program verify and Device ID are accessed via
the command register. Standard microprocessor write
timings are used to input a command to the register. This
register serves as the input to an internal state machine
which controls the operation mode of the device. An
internal latch is used for write cycles, addresses and
data for programming and erase operations.

NO INTEGRATED STOP TIMER FOR ERASE

Leading industry flash technology requires a stop timer
built into the flash chip to prevent the memory cells from
going into depletion due to over erase. The 2 Mbit MTP

REV. 0.8, NOV. 20, 2002

P/N: PM0765

MX26C2000B

EPROM

is built on an innovative cell concept in which

over erasing the memory cell is impossible.

DATA WRITE PROTECTION

The design of the device protects against accidental
erasure or programming. The internal state machine is
automatically reset to the read mode on power-up. Using
control register architecture, alteration of memory can
only occur after completion of proper command
sequences. The command register is only active when V

is at high voltage. when V

= V

PPL

, the device defaults

to the Read Mode. Robust design features prevent
inadvertent write cycles resulting from V

power-up and

power-down transitions or system noise. To avoid initiation
of write cycle during V

power-up, a write cycle is locked

out for V

less than 4V. The two- command program and

erase write sequence to the command register provide
additional software protection against spurious data
changes.

PROGRAM VERIFY MODE

Verification should be performed on the programmed bits
to determine that they were correctly programmed.
Verification should be performed with OE and CE, at
VIL, WE at VIH, and VPP at its programming voltage.

ERASE VERIFY MODE

Verification should be performed on the erased chip to
determine that the whole chip(all bits) was correctly
erased. Verification should be performed with OE and
CE at VIL, WE at VIH, and VCC = 5V, VPP = 12.5V

AUTO IDENTIFY MODE

The auto identify mode allows the reading out of a binary
code from MTP EPROM that will identify its
manufacturer and device type. This mode is intended
for use by programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25

C ambient temperature

range that is required when programming the
MX26C2000B.

To activate this mode, the programming equipment must

force 12.0

0.5 V on address line A9 of the device.

Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to
VIH. All other address lines must be held at VIL during
auto identify mode.

Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For
the MX26C2000B, these two identifier bytes are given
in the Mode Select Table. All identifiers for manufacturer
and device codes will possess odd parity, with the MSB
(DQ7) defined as the parity bit.

READ MODE

The MX26C2000B has two control functions, both of
which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE, assuming that CE has been LOW and addresses
have been stable for at least tACC - tOE.

STANDBY MODE

The MX26C2000B has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is
placed in CMOS standby when CE is at VCC

0.3 V.

The MX26C2000B also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is
placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.

SYSTEM CONSIDERATIONS

During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive

REV. 0.8, NOV. 20, 2002

P/N: PM0765

MX26C2000B

Table 1: BUS OPERATIONS

Mode

VPP(1)

Q0~Q7

Read

VPPL

VIL

VIH

Data Out

READ-ONLY

Output Disable

VPPL

VIL

VIH

Tri-State

MODE

Standby

VPPL

VIH

Tri-State

Manufacturer Identification

VPPL

VIL

VID(2) VIL

VIL

VIH

Data=C2H

Device Identification

VPPL

VIH

VID(2) VIL

VIL

VIH

Data=C3H

Read

VPPH

VIL

VIH

Data Out(3)

COMMAND

Output Disable

VPPH

VIL

VIH

Tri-State

MODE

Standby(4)

VPPH

X(5)

VIH

Tri-State

Program

VPPH

VIL

VIH

VIL

Data Inb

Note:
1. Refer to DC Characteristics. When VPP=VPPL memory contents can be read but not written or erased.
2. VID is the intelligent identifier high voltage. Refer to DC Characteristics.
3. Read operations with VPP=VPPH may access array data or the intelligent identifier codes.
4. With VPP at high voltage the standby current equals ICC+IPP(standby).
5. Refer to Table 2 for vaild data-in during a write operation.
6. X can be VIL or VIH.

effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be
used between VCC and GND for each of the eight
devices. The location of the capacitor should be close
to where the power supply is connected to the array.

OUTPUT DISABLE

Output is disabled when OE is at logre high. When in
output disabled all circuitry is enabled. Except the output
pins are in a high impedance state(TRI-ATATE).

REV. 0.8, NOV. 20, 2002

P/N: PM0765

MX26C2000B

COMMAND MODE

The 2 Mbit MTP EPROM

is in Command mode when

high voltage V

PPH

is applied to the V

pin. In this state the

available functions are Read, Program, Program Verify,
Eraseand Erase Verify. Reset are selected by writing
commands to the input register. Data from the register are
input to the state machine. The output from the state
machine determines the function of the device. The
command register serves as a latch to store data for
executing commands. It does not occupy address- able
memory location. Standard microprocessor write timing is
used. Table 2 defines the register commands. The
command register is written by bringing WE to a logic-low
Level (V

), while CE is low. Addresses are latched on the

falling edge of WE, while data is latched on the rising edge
of the WE pulse.

Standby and Output disable functions are the same as in
Read Mode, controlled by CE and OE. If the device is
deselected during erasure, programming, or erase/program
verification, the device draws active current until the
operations terminate.

READ COMMAND

To read memory content, write 00H into the command
register while high voltage is applied to
V

pin (V

= V

PPH

). Microprocessor read cycle retrieves

the data . The device remains enable for read until the data
in the command register are altered. The device is default
in read mode when power up. This is to ensure no
accidental alteration of the memory occurs during power
transition. Refer to AC Read Characteristics and Waveforms
for specific timing parameters.

SET UP ERASE/ERASE

Preprogram operation is not required prior to the erase
operation. A sequence of commands is required to perform
a complete erase operation: set up erase, erase, and
erase verify. High voltage is applied to the V

PPH

). The command 20H is written to the command

ERASE OPERATION

The same command, 20H, is again written to the
command register. This second command starts bulk

erase operation. The two-step command prevents
accidental alteration to memory array. Erase operation
starts with the rising edge of the WE pulse and
terminates with the rising edge of the next WE pulse,
which in this case is the erase verify command.

ERASE VERIFY

Each erase operation is followed by an erase verify. The
command A0H is written into the command register. The
address of the bytes to be verified is supplied with the
command. The address is latched on the falling edge of
the WE pulse. A reading FFH is returned to confirm all
bits in the byte are erased. This sequence of Set Up
Erase- Erase continues for each address until FFH is
returned. This indicates the entire memory array is
erased and completes the operation. Erase verify
operation starts at address 0000H and ends at the last
address. Maximum erase pulse duration for the 2Mbit
MTP EPROM

is 100ms with a maximum 30 pulses.

Refer to AC Characteristics and Waveforms for specific
timing parameters.

REV. 0.8, NOV. 20, 2002

P/N: PM0765

MX26C2000B

NOTICE:
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended period may
affect reliability.

NOTICE:
Specifications contained within the following tables are
subject to change.

ABSOLUTE MAXIMUM RATINGS

RATING

VALUE

Ambient Operating Temperature -40

C to 85

Storage Temperature

-65

C to 125

Applied Input Voltage

-0.5V to 7.0V

Applied Output Voltage

-0.5V to VCC + 0.5V

VCC to Ground Potential

-0.5V to 7.0V

A9 & VPP

-0.5V to 13.5V

CAPACITANCE

TA = 25

C, f = 1.0 MHz (Sampled only)

SYMBOL

PARAMETER

TYP.

MAX.

UNIT

CONDITIONS

CIN

Input Capacitance

VIN = 0V

COUT

Output Capacitance

VOUT = 0V

CVPP

VPP Capacitance

VPP = 0V

MX26C2000B

-90

-100

-120

-150

Operating Temperature Industrial

-40

C to 85

-40

C to 85

-40

C to 85

-40

C to 85

Vcc Power Supply

10%

DC/AC OPERATING CONDITION FOR READ OPERATION

DC CHARACTERISTICS

TA = -45

C ~ 85

C, VCC=5V

10%

SYMBOL

PARAMETER

MIN.

MAX.

UNIT CONDITIONS

VIL

Input Low Voltage

-0.3

0.8

VIH

Input High Voltage

2.0

VCC + 0.5

VOL

Output Low Voltage

0.4

IOL = 2.1mA, VCC=VCC MIN

VOH

Output High Voltage

2.4

IOH = -0.4mA

ICC1

VCC Active Current

CE = VIL, OE=VIH, f=5MHz

ISB

VCC Standby Current (CMOS)

100

CE=VCC+0.2V, VCC=VCC MAX

ISB

VCC Standby Current (TTL)

1.5

CE=VIH, VCC=VCC MAX

IPP

VPP Read Current

100

CE = OE = VIL, VPP = 5.5V

IPP2

VPP Supply Current

CE=WE=VIL, OE=VIH

(Program/Erase)

ILI

Input Leakage Current

-10

VIN = 0 to 5.5V

ILO

Output Leakage Current

-10

VOUT = 0 to 5.5V

VCC1

Fast Programming Supply Voltage

6.0

6.5

VPP1

Fast Programming Voltage

12.5

13.0

REV. 0.8, NOV. 20, 2002

P/N: PM0765

MX26C2000B

AC RAED CHARACTERISTICS OVER OPERATING RANGE WITH VPP=VCC

Symbol

Parameter

100

120

150

Unit

Jeded STD

MIN

MAX MIN

MAX MIN MAX

tAVAV TRC

Read Cycle Time

100

120

150

tELQV TCE

CE Access Time

100

120

150

tAVQV TACC

Address Access Time

100

120

150

tGLQV TOE

OE Access Time

tELQX TLZ

CE to Output in Low Z(Note 1)

tEHQZ TDF

Chip Disable to Output in High Z(Note 2) 0

tGLQX TOLZ

OE to Output in Low Z (Note 1)

tGHQZ TDF

Output Disable to Output in High Z

(Note 1)

tAXQX TOH

Output Hold from Address, CE or OE,

change

tWHGL TWHGL Write Recovery Time Before Read

tVCS

TVCS

VCC Setup Time to Valid Read (Note 2)

Note:
1. Sampled: not 100% tested.
2. Guaranteed by design. not tested.

REV. 0.8, NOV. 20, 2002

P/N: PM0765

MX26C2000B

AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS

Symbol

Parameter

100

120

150

Unit

JEDED

STD

MIN MAX MIN

MAX MIN MAX MIN MAX

tAVAV

TWC

Write Cycle Time (Note 3)

100

120

150

tAVWL

TAS

Address Setup Time

tWLAX

TAH

Address Hold Time

tDVWH

TDS

Data Setup Time

tWHDX

TDH

Data Hold Time

tWHGL

TWR

Write Recovery Time Before Read

tGHWL

TDES Read Recovery Time Before Write

tELWL

tCS

CE Setup Time Before Write

tWHEH

tCH

CE Hold Time

tWLWH

tWP

Write Pulse Width

tWHWL

tWPH Write Pulse Width High

tWHWH1

Duration of Programming Operation

(Note2)

tWHWH2

Duration of Erase Operation(Note2)

100

tVPEL

VPP Setup Time to Chip Enable Low

(Note 3)

tVCS

VCC Setup Time to Chip Enable Low

(Note 3)

tVPPR

VPP Rise Time (Note 3) 90% VPPH

500

tVPPF

VPP Fall Time (Note 3) 10% VPPH

500

Note:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to

AC Characteristics for Read Only Operations.

2. Maximum pulse widths not required because the on-chip program/erase circuitry will terminate the pulse widths

internally on the device.

3. Not 100% tested.

REV. 0.8, NOV. 20, 2002

P/N: PM0765

MX26C2000B

Table 2: Command Definitions

Command

Bus

First Bus Cycle

Second Bus Cycle

Cycles.

Req

Operation

Address

Data

Operation

Address

Data

Read Memory

Write

00H

Setup Erase/Erase

Write

20H

Write

20H

Erase Verify

Write

A0H

Read

EVD

Setup Program/Program

Write

40H

Write

Program Verify

Write

C0H

Read

PVD

Reset

Write

FFH

Write

FFH

1 EA=Erase Address: address of memory location to be read during erase verify.

PA=Program Address: address of memory location to be Programmed.
Address are latched on the falling edge of the WE pulse.

2 EVD=Erase Verify Data: data read from location EA during erase verify.

PD=Program Data: data to be programmed at location PA. Data is latched on the rising edge of WE.
PVD=Program Verify Data: data read from location PA during program verify. PA is latched on the Program
command.

REV. 0.8, NOV. 20, 2002

P/N: PM0765

MX26C2000B

ORDERING INFORMATION

PLASTIC PACKAGE

PART NO.

ACCESS TIME(ns)

OPERATING

STANDBY

OPERATING

PACKAGE

Current MAX.(mA)

Current MAX.(uA)

TEMPERATURE

MX26C2000BPC-90

100

C to 70

32 Pin DIP

MX26C2000BQC-90

100

C to 70

32 Pin PLCC

MX26C2000BMC-90

100

C to 70

32 Pin SOP

MX26C2000BTC-90

100

C to 70

32 Pin TSOP

MX26C2000BPC-10

100

C to 70

32 Pin DIP

MX26C2000BQC-10

100

C to 70

32 Pin PLCC

MX26C2000BMC-10

100

C to 70

32 Pin SOP

MX26C2000BTC-10

100

C to 70

32 Pin TSOP

MX26C2000BPC-12

120

100

C to 70

32 Pin DIP

MX26C2000BQC-12

120

100

C to 70

32 Pin PLCC

MX26C2000BMC-12

120

100

C to 70

32 Pin SOP

MX26C2000BTC-12

120

100

C to 70

32 Pin TSOP

MX26C2000BPC-15

150

100

C to 70

32 Pin DIP

MX26C2000BQC-15

150

100

C to 70

32 Pin PLCC

MX26C2000BMC-15

150

100

C to 70

32 Pin SOP

MX26C2000BTC-15

150

100

C to 70

32 Pin TSOP

MX26C2000BPI-90

100

-40

C to 85

32 Pin DIP

MX26C2000BQI-90

100

-40

C to 85

32 Pin PLCC

MX26C2000BMI-90

100

-40

C to 85

32 Pin SOP

MX26C2000BTI-90

100

-40

C to 85

32 Pin TSOP

MX26C2000BPI-10

100

-40

C to 85

32 Pin DIP

MX26C2000BQI-10

100

-40

C to 85

32 Pin PLCC

MX26C2000BMI-10

100

-40

C to 85

32 Pin SOP

MX26C2000BTI-10

100

-40

C to 85

32 Pin TSOP

MX26C2000BPI-12

120

100

-40

C to 85

32 Pin DIP

MX26C2000BQI-12

120

100

-40

C to 85

32 Pin PLCC

MX26C2000BMI-12

120

100

-40

C to 85

32 Pin SOP

MX26C2000BTI-12

120

100

-40

C to 85

32 Pin TSOP

MX26C2000BPI-15

150

100

-40

C to 85

32 Pin DIP

MX26C2000BQI-15

150

100

-40

C to 85

32 Pin PLCC

MX26C2000BMI-15

150

100

-40

C to 85

32 Pin SOP

MX26C2000BTI-15

150

100

-40

C to 85

32 Pin TSOP

REV. 0.8, NOV. 20, 2002

P/N: PM0765

MX26C2000B

Revision History

Revision No. Description

Page

Date

0.1

To Add speed 100ns to MX26C2000B

P1,10,11,12,18 NOV/28/2000

Modify the "DC CHARACTERISTICS" table

P10

0.2

To add erase/program cycle

DEC/18/2000

Changed title from MX26C2000A to MX26C2000B

All

0.3

Change Device ID code from 31H to CFH

DEC/28/2000

0.4

To added 32SOP/TSOP types package and access time 150ns

P1,11,12,17,18 MAR/27/2001

Modify device ID old CFH-->New C3H

Modify read ID method

P4,5,6,13

Modify erase/program cycle from 100 to 50

Modify VCC Standby Current(TTL) from 1mA to 1.5mA

P10

0.5

To added VCC1 & VPP1 to DC Characteristics Table

P10

APR/23/2001

Modify Package Information

P18~21

0.6

To added chip erase time / chip program time

JUL/04/2001

Modify Package Information

P18~21

0.7

Modify the Programming Operations Timing Waveforms

P15

OCT/04/2001

0.8

To modify Package Information

P18~21

NOV/20/2002

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