P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

64M-BIT [4M x 16] CMOS

MULTIPLE-TIME-PROGRAMMABLE EPROM

ADVANCED INFORMATION

FEATURES

4,194,304 x 16 byte structure

Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase andprogram

operation

Low Vcc write inhibit is equal to or less than 2.5V

Compatible with JEDEC standard

High Performance

- Fast access time: 90/120ns (typ.)

- Fast program time: 140s/chip (typ.)

- Fast erase time: 150s/chip (typ.)

Low Power Consumption

- Low active read current: 17mA (typ.) at 5MHz

- Low standby current: 30uA (typ.)

Minimum 100 erase/program cycle

Status Reply

- Data polling & Toggle bits provide detection of

program and erase operation completion

12V ACC input pin provides accelerated program

capability

Output voltages and input voltages on the device is

deterined by the voltage on the VI/O pin.

- VI/O voltage range:1.65V~3.6V

10 years data retention

Package

- 48-Pin TSOP

- 63-Ball CSP

GENERAL DESCRIPTION

The MX26L6413 is a 64M bit MTP EPROM

organized

as 4M bytes of 16 bits. MXIC's MTP EPROM

offer the

most cost-effective and reliable read/write non-volatile

random access memory. The MX26L6413 is packaged in

48-pin TSOP, 48-ball CSP amd 63-ball CSP. It is

designed to be reprogrammed and erased in system or in

standard EPROM programmers.

The standard MX26L6413 offers access time as fast as

90ns, allowing operation of high-speed microprocessors

without wait states. To eliminate bus contention, the

MX26L6413 has separate chip enable (CE) and output

enable OE controls. MXIC's MTP EPROM

augment

EPROM functionality with in-circuit electrical erasure and

programming. The MX26L6413 uses a command register

to manage this functionality.

MXIC's MTP EPROM

technology reliably stores

memory contents even after 100 erase and program

cycles. The MXIC cell is designed to optimize the erase

and program mechanisms. In addition, the combination of

advanced tunnel oxide processing and low internal

electric fields for erase and programming operations

produces reliable cycling.

The MX26L6413 uses a 2.7V to 3.6V VCC supply to

perform the High Reliability Erase and auto Program/

Erase algorithms.

The highest degree of latch-up protection is achieved with

MXIC's proprietary non-epiprocess. Latch-up protection

is proved for stresses up to 100 milliamps on address and

data pin from -1V to VCC +1V.

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

PIN CONFIGURATION

63 CSP Ball pitch=0.8mm for MX26L6413XB (TOP view, Ball down)

A13

* Ball are shorted together via the substrate but not connected to the die.

A12

RESET

ACC

A17

A14

A10

A21

A18

A15

A11

A19

A20

A16

VIO

Q14

Q12

Q10

Q15

Q13

VCC

Q11

GND

NC*

13.0 mm

8.0 mm

NC*

48 TSOP

A15
A14
A13
A12
A11
A10

A9
A8

A21
A20

RESET

ACC
VCC

A19
A18
A17

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

A16
V

I/O

GND
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
V

Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

MX26L6413

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

AUTOMATIC PROGRAMMING

The MX26L6413 is word programmable using the Auto-
matic Programming algorithm. The Automatic Program-
ming algorithm makes the external system do not need
to have time out sequence nor to verify the data pro-
grammed. The typical chip programming time at room
temperature of the MX26L6413 is around 140 seconds.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 un-
lock write cycle and A0H) and a program command (pro-
gram data and address). The device automatically times
the programming pulse width, provides the program veri-
fication, and counts the number of sequences. A status
bit similar to DATA polling and a status bit toggling be-
tween consecutive read cycles, provide feedback to the
user as to the status of the programming operation.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is around 150 sec-
onds. The Automatic Erase algorithm automatically pro-
grams the entire array prior to electrical erase. The tim-
ing and verification of electrical erase are controlled in-
ternally within the device.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand-
ard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.

Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-

ming and erase operations. All address are latched on
the falling edge of WE or CE, whichever happens later.
All data are latched on rising edge of WE or CE, which-
ever happens first.

MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia-
bility, and cost effectiveness. The MX26L6413 electri-
cally erases all bits simultaneously using Fowler-Nord-
heim tunneling. The bytes are programmed by using the
EPROM programming mechanism of hot electron injec-
tion.

During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

Operation

RESET

Address

Q15~Q0

Read

OUT

Write(Note 1)

Standby

VCC

0.3V

VCC

0.3V

High-Z

Output Disable

High-Z

Reset

High-Z

Legend:

L=Logic LOW=V

,H=Logic High=V

=12.0

0.5V,X=Don't Care, A

=Address IN, D

=Data IN, D

OUT

=Data OUT

Notes:
1. When the ACC pin is at V

, the device enters the accelerated program mode. See "Accelerated Program Operations"

for more information.

Table 1

BUS OPERATION(1)

A14

Operation

A15~A21

Q15~Q0

A10

Read Silicon ID

X00

C2H

Manufactures Code

Read Silicon ID

22FCH

Device Code

Secured Silscon

xx88h

Sector Indicator

(factory locked)

Bit (Q7)

xx08h

(non-factory locked)

Table 2. AUTOSELECT CODES (High Voltage Method)

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

REQUIREMENTS FOR READING ARRAY
DATA

To read array data from the outputs, the system must
drive the CE and OE pins to VIL. CE is the power control
and selects the device. OE is the output control and gates
array data to the output pins. WE should remain at VIH.

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content
occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid address on
the device address inputs produce valid data on the device
data outputs. The device remains enabled for read access
until the command register contents are altered.

WRITE COMMANDS/COMMAND
SEQUENCES

To program data to the device or erase memory , the
system must drive WE and CE to VIL, and OE to VIH.

An erase operation can erase the entire device. The
"Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 1 defines the valid register command
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device
to reading array data. Section has details on erasing the
entire chip.

After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal
register (which is separate from the memory array) on
Q15-Q0. Standard read cycle timings apply in this mode.
Refer to the Autoselect Mode and Autoselect Command
Sequence section for more information.

ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.

STANDBY MODE

MX26L6413 can be set into Standby mode with two dif-
ferent approaches. One is using both CE and RESET
pins and the other one is using RESET pin only.

When using both pins of CE and RESET, a CMOS
Standby mode is achieved with both pins held at Vcc ±
0.3V. Under this condition, the current consumed is less
than 50uA (typ.). If both of the CE and RESET are held
at VIH, but not within the range of VCC ±

0.3V, the device

will still be in the standby mode, but the standby current
will be larger. During Auto Algorithm operation, Vcc ac-
tive current (Icc2) is required even CE = "H" until the
operation is completed. The device can be read with stan-
dard access time (tCE) from either of these standby
modes.

When using only RESET, a CMOS standby mode is
achieved with RESET input held at Vss

0.3V, Under

this condition the current is consumed less than 50uA
(typ.). Once the RESET pin is taken high. The device is
back to active without recovery delay.

In the standby mode the outputs are in the high imped-
ance state, independent of the OE input.

MX26L6413 is capable to provide the Automatic Standby
Mode to restrain power consumption during read-out of
data. This mode can be used effectively with an applica-
tion requested low power consumption such as handy
terminals.

To active this mode, MX26L6413 automatically switch
themselves to low power mode when MX26L6413 ad-
dresses remain stable during access time of tACC+30ns.
It is not necessary to control CE, WE, and OE on the
mode. Under the mode, the current consumed is typi-
cally 50uA (CMOS level).

OUTPUT DISABLE

With the OE input at a logic high level (VIH), output from
the devices are disabled. This will cause the output pins
to be in a high impedance state.

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

RESET OPERATION

The RESET pin provides a hardware method of resetting
the device to reading array data. When the RESET pin is
driven low for at least a period of tRP, the device
immediately terminates any operation in progress, tri-
states all output pins, and ignores all read/write
commands for the duration of the RESET pulse. The
device also resets the internal state machine to reading
array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another
command sequence, to ensure data integrity

Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS

0.3V, the device draws

CMOS standby current (ICC4). If RESET is held at VIL
but not within VSS

0.3V, the standby current will be

greater.

The RESET pin may be tied to system reset circuitry. A
system reset would that also reset the MTP EPROM.

Refer to the AC Characteristics tables for RESET
parameters and to Figure 14 for the timing diagram.

SILICON ID READ OPERATION

MTP EPROM are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. EPROM program-
mers typically access signature codes by raising A9 to
a high voltage. However, multiplexing high voltage onto
address lines is not generally desired system design prac-
tice.

MX26L6413 provides hardware method to access the
silicon ID read operation. Which method requires VID on
A9 pin, VIL on CE, OE, A6, and A1 pins. Which apply
VIL on A0 pin, the device will output MXIC's manufac-
ture code of C2H. Which apply VIH on A0 pin, the device
will output MX26L6413 device code of 22FCH.

VI/O PIN OPERATION

MX26L6413 is capable to provide the I/O power supply
(VI/O) pin to control Input/Output voltage levels of the
device. The data outputs and voltage tolerated at its data
input is determined by the voltage on the VI/O pin. This
device is allows to operate in 1.8V or 3V system as re-
quired.

DATA PROTECTION

The MX26L6413 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with
its control register architecture, alteration of the memory
contents only occurs after successful completion of spe-
cific command sequences. The device also incorporates
several features to prevent inadvertent write cycles re-
sulting from VCC power-up and power-down transition or
system noise.

SECURED SILICON SECTOR

The MX26L6413 features a Flash memory region where
the system may access through a command sequence
to create a permanent part identification as so called
Electronic Serial Number (ESN) in the device. Once this
region is programmed, any further modification on the
region is impossible. The secured silicon sector is a 512
words in length, and uses a Secured Silicon Sector Indi-
cator Bit (Q7) to indicate whether or not the Secured
Silicon Sector is locked when shipped from the factory.
This bit is permanently set at the factory and cannot be
changed, which prevent duplication of a factory locked
part. This ensures the security of the ESN once the prod-
uct is shipped to the field.

The MX26L6413 offers the device with Secured Silicon
Sector either factory locked or customer lockable. The
factory-locked version is always protected when shipped
from the factory , and has the Secured Silicon Sector
Indicator Bit permanently set to a "1". The customer-
lockable version is shipped with the Secured Silicon
Sector unprotected, allowing customer to utilize that sec-
tor in any form they prefer. The customer-lockable ver-

VCC / VI/O Voltage Range

Part No.

VCC=2.7V to 3.6VVCC=2.7V to 3.6V

VI/O=2.7V to 3.6VVI/O=1.65V to 2.6V

MX26L6413-90

90ns

100ns

MX26L6413-12

120ns

130ns

Table 3

Notes: Typical values measured at VCC=2.7V to 3.6V,

VI/O=2.7V to 3.6V

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

sion has the secured sector Indicator Bit permanently
set to a "0". Therefore, the Secured Silicon Sector Indi-
cator Bit permanently set to a "0". Therefore, the Second
Silicon Sector Indicator Bit prevents customer, lockable
device from being used to replace devices that are fac-
tory locked.

The system access the Secured Silicon Sector through
a command sequence (refer to "Enter Secured Silicon/
Exit Secured Silicon Sector command Sequence). After
the system has written the Enter Secured Silicon Sector
command sequence, it may read the Secured Silicon
Sector by using the address normally occupied by the
address 000000h-0001FFh. This mode of operation con-
tinues until the system issues the Exit Secured Silicon
Sector command sequence, or until power is removed
from the device. On power-up, or following a hardware
reset, the device reverts to sending command to ad-
dress 000000h-0001FFFh.

LOW VCC WRITE INHIBIT

When VCC is less than VLKO the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional write
when VCC is greater than VLKO.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.

POWER-UP SEQUENCE

The MX26L6413 powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of the predefined command se-
quences.

FACTORY LOCKED:Secured Silicon Sector
Programmed and Protected At the Factory

In device with an ESN, the Secured Silicon Sector is
protected when the device is shipped from the factory.
The Secured Silicon Sector cannot be modified in any
way. A factory locked device has an 8-word random ESN
at address 000000h-000007h.

CUSTOMER LOCKABLE:Secured Silicon
Sector NOT Programmed or Protected At the
Factory

As an alternative to the factory-locked version, the device
may be ordered such that the customer may program
and protect the 512-word Secured Silicon Sector.
Programming and protecting the Secured Silicon Sector
must be used with caution since, once protected, there
is no procedure available for unprotecting the Secured
Silicon Sector area and none of the bits in the Secured
Silicon Sector memory space can be modified in any
way.

The Secured Silicon Sector area can be protected using
the following procedures:

Write the three-cycle Enter Secured Silicon Sector Region
command sequence. This allows in-system protection
of the Secured Silicon Sector without raising any device
pin to a high voltage. Note that method is only applicable
to the Secured Silicon Sector.

Once the Secured Silicon Sector is programmed, locked
and verified, the system must write the Exit Secured
Silicon Sector Region command sequence to return to
reading and writing the remainder of the array.

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

SOFTWARE COMMAND DEFINITIONS

Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them
in the improper sequence will reset the device to the
read mode. Table 4 defines the valid register command
sequences. Either of the two reset command sequences

Legend:
X=Don't care
RA=Address of the memory location to be read.
RD=Data read from location RA during read operation.
PA=Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE or
CE pulse.

PD=Data to be programmed at location PA. Data is
latched on the rising edge of WE or CE pulse.

will reset the device (when applicable).

All addresses are latched on the falling edge of WE or
CE, whichever happens later. All data are latched on ris-
ing edge of WE or CE, whichever happens first.

First Bus

Second Bus Third Bus

Fourth Bus

Fifth Bus

Sixth Bus

Command

Bus

Cycle

Addr

Data

Addr

Data Addr

Data

Addr

Data Addr Data

Read(Note 5)

Reset(Note 6)

XXX

Autoselect(Note 7)

Manufacturer ID

555

2AA

555

X00

Device ID

555

2AA

555

X01

22FC

Secured Sector

555

2AA

555

x03

see

Factory Protect

Note9

Enter Secured Silicon

555

2AA

555

Sector

Exit Secured Silicon

555

2AA

555

xxx

Sector

Porgram

555

2AA

555

Chip Erase

555

2AA

555

2AA

555

TABLE4. MX26L6413

COMMAND DEFINITIONS

Notes:
1. See Table 1 for descriptions of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits are don't care for unlock and command cycles, except when PA is required.
5. No unlock or command cycles required when device is in read mode.
6. The Reset command is required to return to the read mode when the device is in the autoselect mode or if Q5 goes

high.

7. The fourth cycle of the autoselect command sequence is a read cycle.
8. In the third and fourth cycles of the command sequence, set A21=0.
9. Command is valid when device is ready to read array data or when device is in autoselect mode.
10. The data is 88h for factory locked and 08h for non-factory locked.

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

READING ARRAY DATA

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array data
after completing an Automatic Program or Automatic
Erase algorithm.

The system

must

issue the reset command to re-en-

able the device for reading array data if Q5 goes high, or
while in the autoselect mode. See the "Reset Command"
section, next.

RESET COMMAND

Writing the reset command to the device resets the
device to reading array data. Address bits are don't care
for this command.

The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.

The reset command may be written between the se-
quence cycles in a program command sequence before
programming begins. This resets the device to reading
array data. Once programming begins, however, the
device ignores reset commands until the operation is
complete.

The reset command may be written between the se-
quence cycles in an SILICON ID READ command
sequence. Once in the SILICON ID READ mode, the
reset command

must

be written to return to reading array

data.

If Q5 goes high during a program or erase operation,
writing the reset command returns the device to reading
array data.

SILICON ID READ COMMAND SEQUENCE

The SILICON ID READ command sequence allows the
host system to access the manufacturer and devices
codes, and determine whether or not. Table 4 shows the
address and data requirements. This method is an
alternative to that shown in Table 1, which is intended for
EPROM programmers and requires V

on address bit

A9.

The SILICON ID READ command sequence is initiated
by writing two unlock cycles, followed by the SILICON
ID READ command. The device then enters the SILICON
ID READ mode, and the system may read at any address
any number of times, without initiating another command
sequence. A read cycle at address XX00h retrieves the
manufacturer code. A read cycle at address XX01h re-
turns the device code.

The system must write the reset command to exit the
autoselect mode and return to reading array data.

WORD PROGRAM COMMAND SEQUENCE

The command sequence requires four bus cycles, and
is initiated by writing two unlock write cycles, followed
by the program set-up command. The program address
and data are written next, which in turn initiate the
Embedded Program algorithm. The system is

not

required

to provide fur ther controls or timings. The device
automatically generates the program pulses and verifies
the programmed cell margin. Table 4 shows the address
and data requirements for the byte program command
sequence.

When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses
are no longer latched. The system can determine the
status of the program operation by using Q7, Q6. See
"Write Operation Status" for information on these status
bits.

Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming
operation. The Word Program command sequence should
be reinitiated once the device has reset to reading array
data, to ensure data integrity.

Programming is allowed in any sequence. A bit cannot
be programmed from a "0" back to a "1". Cause the Data
Polling algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
still "0". Only erase operations can convert a "0" to a
"1".

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

ACCELERATED PROGRAM OPERATIONS

The device offers accelerated program operations through
the ACC pin. When the system asserts V

on the ACC

pin, the device automatically bypass the two "Unlock"
write cycle. The device uses the higher voltage on the
ACC pin to accelerate the operation. Removing V

from

the ACC pin returns the device to normal operation. Under
normal operation ACC can be VCC or GND. Note that the
ACC pin must not be at V

any operation other than

accelerated programming, or device damage may result.

SETUP AUTOMATIC CHIP ERASE

Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.

The MX26L6413 contains a Silicon-ID-Read operation to
supplement traditional PROM programming methodology.
The operation is initiated by writing the read silicon ID
command sequence into the command register. Follow-
ing the command write, a read cycle with A6=VIL,
A1=VIL, A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A6=VIL, A1=VIL, A0=VIH returns the
device code of 22FCH for MX26L6413.

AUTOMATIC CHIP ERASE COMMAND

The device does not require the system to preprogram
prior to erase. The Automatic Erase algorithm automati-
cally preprogram and verifies the entire memory for an
all zero data pattern prior to electrical erase. The system
is not required to provide any controls or timings during
these operations. Table 4 shows the address and data
requirements for the chip erase command sequence.

Any commands written to the chip during the Automatic
Erase algorithm are ignored. Note that a hardware reset
during the chip erase operation immediately terminates
the operation. The Chip Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.

The system can determine the status of the erase op-
eration by using Q7, Q6. See "Write Operation Status"
for information on these status bits. When the Automatic
Erase algorithm is complete, the device returns to read-
ing array data and addresses are no longer latched.

Figure 5 illustrates the algorithm for the erase opera-tion.
See the Erase/Program Operations tables in "AC Char-
acteristics" for parameters, and to Figure 4 for timing
diagrams.

TABLE 5. SILICON ID CODE

Pins

Q15

Code(Hex)

Manufacture code

VIL

00H

00C2H

Device code for MX26L6413 VIH VIL

VIL

22H

22FCH

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

Q7: Data Polling

The Data Polling bit, Q7, indicates to the host system
whether an Automatic Algorithm is in progress or com-
pleted. Data Polling is valid after the rising edge of the
final WE pulse in the program or erase command se-
quence.

During the Automatic Program algorithm, the device out-
puts on Q7 the complement of the datum programmed
to Q7. This Q7 status also applies to programming dur-
ing Erase Suspend. When the Automatic Program algo-
rithm is complete, the device outputs the datum pro-
grammed to Q7. The system must provide the program
address to read valid status information on Q7.

During the Automatic Erase algorithm, Data Polling pro-
duces a "0" on Q7. When the Automatic Erase algo-
rithm is complete. Data Polling produces a "1" on Q7.
This is analogous to the complement/true datum output
described for the Automatic Program algorithm: the erase
function changes all the bits to "1" prior to this, the de-
vice outputs the "complement," or "0".

After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data Polling on
Q7 is active for approximately 100 us, then the device
returns to reading array data.

When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchronously with Q0-Q6 while Output Enable
(OE) is asserted low.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-
gram or Erase algorithm is in progress or complete. Toggle
Bit I may be read at any address, and is valid after the
rising edge of the final WE or CE, whichever happens
first pulse in the command sequence (prior to the pro-
gram or erase operation).

During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE or CE to con-
trol the read cycles. When the operation is complete, Q6
stops toggling.

Table 6 shows the outputs for Toggle Bit I on Q6.

Q5:Program/Erase Timing

Q5 will indicate if the program or erase time has exceeded
the specified limits (internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not suc-
cessfully completed. Data Polling and Toggle Bit are the
only operating functions of the device under this condi-
tion.

If this time-out condition occurs during chip erase opera-
tion, it specifies that device is bad and it may not be
reused. Write the Reset command sequence to the de-
vice, and then execute program or erase command se-
quence. This allows the system to continue to use the
other active sectors in the device.

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad.

If this time-out condition occurs during the word program-
ming operation, the word is bad and may not be reused,
(other word are still functional and can be reused).

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . ..... -65

C to +150

Ambient Temperature

with Power Applied. . . . . . . . . . . . . .... -65

C to +125

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE, and

RESET (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-
shoot VSS to -2.0 V for periods of up to 20 ns. See
Figure 6. Maximum DC voltage on input or I/O pins is
VCC +0.5 V. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to
20 ns. See Figure 7.

2. Minimum DC input voltage on pins A9, OE, and

RESET is -0.5 V. During voltage transitions, A9, OE,
and RESET may overshoot VSS to -2.0 V for periods
of up to 20 ns. See Figure 6. Maximum DC input volt-
age on pin A9 is +12.5 V which may overshoot to 14.0
V for periods up to 20 ns.

3. No more than one output may be shorted to ground at

a time. Duration of the short circuit should not be
greater than one second.

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.

OPERATING RATINGS

Commercial (C) Devices

Ambient Temperature (T

). . . . . . . . . . . . 0

C to +70

Industrial (I) Devices

Ambient Temperature (T

). . . . . . . . . . -40

C to +85

Supply Voltages

for full voltage range . . . . . . . . . . . . +2.7 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

Para-

VI/O=2.7V~3.6V

VI/O=1.65V~2.6V

meter Description

Test Conditions

Min

Typ

Max

Min

Typ

Max

Unit

I LI

Input Load Current (Note 1)

VIN = VSS to VCC ,

1.0

VCC = VCC max

I LIT

A9 Input Load Current

VCC=VCC max; A9 = 12.5V

I LO

Output Leakage Current

VOUT = VSS to VCC ,

1.0

VCC= VCC max

ICC1

VCC Active Read Current

CE= VIL, OE = VIH 5 MHz

(Notes1, 2)

1 MHz

ICC2

VCC Active Write Current

CE= V IL , OE = V IH

(Notes 1, 3, 4)

ICC3

VCC Standby Current (CMOS) CE,RESET,

100

(Note 1)

ACC=VCC

0.3V

ICC4

VCC Standby Current (TTL)

CE=VIH

0.5

(Note 1)

ICC5

VCC Reset Current (Note 1)

RESET = V SS

0.3 V,

0.2

ACC = VCC

0.3 V

IACC

ACC Accelerated Program

CE=VIL, OE=VIH

Acc pin

Current, Word

Vcc pin

VIL

Input Low Voltage

-0.5

0.8

0.4

VIH

Input High Voltage

0.7xVcc

Vcc+0.3 VI/O-0.4

VHH

Voltage for ACC

VCC = 3.0 V

10%

11.5

12.5

11.5

12.5

Program Acceleration

VID

Voltage for Autoselect

VCC = 3.0 V

10%

11.5

12.5

11.5

12.5

VOL

Output Low Voltage

IOL= 4.0mA,VCC=VCC min

0.45

VOH1 Output High Voltage

IOH=-2.0mA,VCC=VCC min 0.85VI/O

0.85VI/O

VOH2

IOH=-100uA,VCC=VCC min VI/O-0.4

VI/O-0.4

VLKO Low V CC Lock-Out Voltage

2.3

2.5

2.3

2.5

(Note 4)

Notes:
1. Maximum ICC specifications are tested with VCC = VCC max.
2. The ICC current listed is typically is less than 2 mA/MHz, with OE at V IH . Typical specifications are for VCC = 3.0 V.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.

DC CHARACTERISTICS TA=0

C to 70

C, VCC=2.7V~3.6V

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

SWITCHING TEST CIRCUITS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don't Care, Any Change Permitted

Changing, State Unknown

Does Not Apply

Center Line is High Impedance State (High Z)

KEY TO SWITCHING WAVEFORMS

SWITCHING TEST WAVEFORMS

TEST SPECIFICATIONS

Test Condition

90ns 120ns

Unit

Output Load

1 TTL gate

Output Load Capacitance,

30 100

CL (including jig capacitance)

Input Rise and Fall Times

Input Pulse Levels

0.0-3.0

Input timing measurement

1.5

reference levels

Output timing measurement

1.5

reference levels

DEVICE UNDER

TEST

DIODES=IN3064

OR EQUIVALENT

6.2K ohm

2.7K ohm

3.3V

1.5V

VIO/2

Measurement Level

3.0V

0.0V

OUTPUT

INPUT

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

Symbol

DESCRIPTION

CONDITION

90ns

120ns

Unit

tACC

Address to output delay

CE=VIL MAX

120

OE=VIL

tCE

Chip enable to output delay

OE=VIL MAX

120

tOE

Output enable to output delay

MAX

tDF

OE High to output float(Note1)

MAX

tOH

Output hold time of from the rising edge of

MIN

Address, CE, or OE, whichever happens first

tRC

Read cycle time (Note 1)

MIN

120

tWC

Write cycle time (Note 1)

MIN

120

tCWC

Command write cycle time(Note 1)

MIN

120

tAS

Address setup time

MIN

tAH

Address hold time

MIN

tDS

Data setup time

MIN

tDH

Data hold time

MIN

tVCS

Vcc setup time(Note 1)

MIN

tCS

Chip enable setup time

MIN

tCH

Chip enable hold time

MIN

tOES

Output enable setup time (Note 1)

MIN

tOEH

Output enable hold time (Note 1)

Read

MIN

Toggle &

MIN

Data Polling

tWES

WE setup time

MIN

tWEH

WE hold time

MIN

tCEP

CE pulse width

MIN

tCEPH

CE pulse width high

MIN

tWP

WE pulse width

MIN

tWPH

WE pulse width high

MIN

tOLZ

Output enable to output low Z

MAX

tWHGL

WE high to OE going low

MIN

tWHWH1 Word Programming Operation (Note 3)

TYP

tWHWH1 Accelerated Word Programming Operation(Note3)

TYP

tWHWH2 Chip Erase Operation (Note3)

TYP

150

sec

Note:

1.Not 100% Tested
2.t

= t

= 5ns

3. See the " Erase and Program Performance" section for more information.

AC CHARACTERISTICS TA=0

C to 70

C, VCC=2.7V~3.6V

P/N:PM0914

REV. 0.1, NOV. 20, 2002

MX26L6413

MIN.

MAX.

Input Voltage with respect to GND on all pins except I/O pins

-1.0V

13.5V

Input Voltage with respect to GND on all I/O pins

-1.0V

Vcc + 1.0V

Current

-100mA

+100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

LIMITS

PARAMETER

MIN.

TYP.(2)

MAX.

UNITS

Chip Erase Time

150

300

sec

Word Programming Time

350

Chip Programming Time

140

250

sec

Accelerated Chip Erase Time

150

sec

Accelerated Word Program Time

210

Accelerated Chip Program Time

125

sec

Erase/Program Cycles

100

Cycles

LATCH-UP CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE(1)

Note:

1. Not 100% Tested, Excludes external system level over head.
2. Typical values measured at 25

C,3.3V. Additionally programming typically assume checkerboard pattern.

Parameter Symbol

Parameter Description

Test Set

TYP

MAX

UNIT

CIN

Input Capacitance

VIN=0

7.5

COUT

Output Capacitance

VOUT=0

8.5

CIN2

Control Pin Capacitance

VIN=0

7.5

CAPACITANCE TA=0

C to 70

C, VCC=2.7V~3.6V

Notes:
1. Sampled, not 100% tested.
2. Test conditions TA=25

C, f=1.0MHz

Parameter

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150

Years

125

Years

DATA RETENTION

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MX26L6413TC-12

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MX26L6413TC-12