Operating current: 30mA

Standby current: 100uA

Package type:

- 28 pin plastic DIP
- 32 pin PLCC
- 28 pin 8 x 13.4 mm TSOP(I)

PIN CONFIGURATIONS

PDIP

GENERAL DESCRIPTION

The MX27C512 is a 5V only, 512K-bit, One-Time
Programmable Read Only Memory. It is organized as
64K words by 8 bits per word, operates from a single
+5volt supply, has a static standby mode, and features
fast single address location programming. All program-
ming signals are TTL levels, requiring a single pulse. For
programming outside from the system, existing EPROM

programmers may be used. The MX27C512 supports
intelligent fast programming algorithm which can result
in programming time of less than fifteen seconds.

This EPROM is packaged in industry standard 28 pin
dual-in-line packages 32 lead PLCC, and 28 lead
TSOP(I) packages.

FEATURES

64K x 8 organization

Single +5V power supply

+12.5V programming voltage

Fast access time: 45/55/70/90/100/120/150ns

Totally static operation

Completely TTL compatible

P/N: PM0235

REV. 4.7, NOV. 19, 2002

BLOCK DIAGRAM

PIN DESCRIPTION

PLCC

8 x 13.4mm 28TSOP(I)

SYMBOL

PIN NAME

A0~A15

Address Input

Q0~Q7

Data Input/Output

Chip Enable Input

OE/VPP

Output Enable Input/Program Supply

Voltage

No Internal Connection

VCC

Power Supply Pin (+5V)

GND

Ground Pin

MX27C512

512K-BIT [64Kx8] CMOS EPROM

A15

A12

GND

VCC

A14

A13

A11

OE/VPP

A10

MX27C512

A11

OE/VPP

A10

GND

A12

A15

VCC

A14

A13

MX27C512

OE/VPP

A11

A9
A8

A13
A14

VCC

A15
A12

A7
A6
A5
A4
A3

22
23
24
25
26
27
28
1
2
3
4
5
6
7

A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2

21
20
19
18
17
16
15
14
13
12
11
10

9
8

MX27C512

CONTROL

LOGIC

OUTPUT

BUFFERS

Q0~Q7

OE/VPP

A0~A15

ADDRESS

INPUTS

Y-DECODER

X-DECODER

Y-SELECT

512K BIT

CELL

MAXTRIX

VCC

GND

P/N:PM0235

REV. 4.7, NOV. 19, 2002

MX27C512

AUTO IDENTIFY MODE

The auto identify mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and device type. This mode is intended for use by
programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25

C ambient

temperature range that is required when programming
the MX27C512.

To activate this mode, the programming equipment
must force 12.0

0.5(VH) on address line A9 of the

device. Two identifier bytes may then be sequenced
from the device outputs by toggling address line A0 from
VIL to VIH. All other address lines must be held at VIL
during auto identify mode.

Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For the
MX27C512, these two identifier bytes are given in the
Mode Select Table. All identifiers for manufacturer and
device codes will possess odd parity, with the MSB (Q7)
defined as the parity bit.

READ MODE

The MX27C512 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE, assuming that CE has been LOW and addresses
have been stable for at least tACC - tOE.

STANDBY MODE

The MX27C512 has a CMOS standby mode which
reduces the maximum VCC current to 100uA . It is
placed in CMOS standby when CE is at VCC

0.3 V.

The MX27C512 also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is
placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.

FUNCTIONAL DESCRIPTION

THE PROGRAMMING OF THE MX27C512

When the MX27C512 is delivered, or it is erased, the
chip has all 512K bits in the "ONE" or HIGH state.
"ZEROs" are loaded into the MX27C512 through the
procedure of programming.

For programming, the data to be programmed is applied
with 8 bits in parallel to the data pins.

Vcc must be applied simultaneously or before Vpp, and
removed simultaneously or after Vpp. When
programming an MXIC EPROM, a 0.1uF capacitor is
required across Vpp and ground to suppress spurious
voltage transients which may damage the device.

FAST PROGRAMMING

The device is set up in the fast programming mode when
the programming voltage OE/VPP = 12.75V is applied,
with VCC = 6.25 V, (Algorithm is shown in Figure 1). The
programming is achieved by applying a single TTL low
level 100us pulse to the CE input after addresses and
data line are stable. If the data is not verified, an
additional pulse is applied for a maximum of 25 pulses.
This process is repeated while sequencing through
each address of the device. When the programming
mode is completed, the data in all address is verified at
VCC = 5V

10%.

PROGRAM INHIBIT MODE

Programming of multiple MX27C512s in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX27C512 may be common. A
TTL low-level program pulse applied to an MX27C512
CE input with OE/VPP = 12.5

0.5V will program that

MX27C512. A high-level CE input inhibits the other
MX27C512s from being programmed.

PROGRAM VERIFY MODE

Verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verification should be performed with OE/VPP and
CE, at VIL. Data should be verified tDV after the falling
edge of CE.

P/N:PM0235

REV. 4.7, NOV. 19, 2002

MX27C512

NOTES: 1. VH = 12.0 V

0.5 V

2. X = Either VIH or VIL

3. A1 - A8 = A10 - A15 = VIL(For auto select)
4. See DC Programming Characteristics for VPP voltage during

programming.

MODE SELECT TABLE

PINS

MODE

OE/VPP

OUTPUTS

Read

VIL

DOUT

Output Disable

VIL

VIH

High Z

Standby (TTL)

VIH

High Z

Standby (CMOS)

VCC

0.3V

High Z

Program

VIL

VPP

DIN

Program Verify

VIL

DOUT

Program Inhibit

VIH

VPP

High Z

Manufacturer Code(3)

VIL

C2H

Device Code(3)

VIL

VIH

91H

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a two-
line control function is provided to allow for:

1. Low memory power dissipation,
2. Assurance that output bus contention will not
occur.

It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.

SYSTEM CONSIDERATIONS

During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be
used between VCC and GND for each eight devices.
The location of the capacitor should be close to where
the power supply is connected to the array.

P/N:PM0235

REV. 4.7, NOV. 19, 2002

MX27C512

ABSOLUTE MAXIMUM RATINGS

RATING

VALUE

Ambient Operating Temperature

-40

C to 125

Storage Temperature

-65

C to 125

Applied Input Voltage

-0.5V to 7.0V

Applied Output Voltage

-0.5V to VCC + 0.5V

VCC to Ground Potential

-0.5V to 7.0V

A9 & Vpp

-0.5V to 13.5V

NOTICE:
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended period may affect reliability.

NOTICE:
Specifications contained within the following tables are sub-
ject to change.

DC/AC Operating Conditions for Read Operation

MX27C512

-45

-55

-70

-90

-10

-12

-15

Operating

Commercial 0

C to 55

C to 70

Temperature Industrial

-40

C to 85

C -40

C to 85

C -40

C to 85

C -40

C to 85

C -40

C to 85

C -40

C to 85

C -40

C to 85

Automotive

-40

C to 125

C -40

C to 125

C -40

C to 125

C -40

C to 125

Vcc Power Supply

10%

DC CHARACTERISTICS

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

CONDITIONS

VOH

Output High Voltage

2.4

IOH = -0.4mA

VOL

Output Low Voltage

0.4

IOL = 2.1mA

VIH

Input High Voltage

2.0

VCC + 0.5

VIL

Input Low Voltage

-0.2

0.8

ILI

Input Leakage Current

-10

VIN = 0 to 5.5V

ILO

Output Leakage Current

-10

VOUT = 0 to 5.5V

ICC3

VCC Power-Down Current

100

CE = VCC

0.3V

ICC2

VCC Standby Current

1.5

CE = VIH

ICC1

VCC Active Current

CE = VIL, f=5MHz, Iout =0mA

IPP

VPP Supply Current Read

CE = VIL, VPP = 5.5V

CAPACITANCE

TA = 25

C, f = 1.0 MHz (Sampled only)

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

CONDITIONS

CIN

Input Capacitance

VIN = 0V

COUT

Output Capacitance

VOUT = 0V

Vpp

VPP Capacitance

VPP = 0V

P/N:PM0235

REV. 4.7, NOV. 19, 2002

MX27C512

DC PROGRAMMING CHARACTERISTICS

TA = 25

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

CONDITIONS

VOH

Output High Voltage

2.4

IOH = -0.40mA

VOL

Output Low Voltage

0.4

IOL = 2.1mA

VIH

Input High Voltage

2.0

VCC + 0.5

VIL

Input Low Voltage

-0.2

0.8

ILI

Input Leakage Current

-10

VIN = 0 to 5.5V

A9 Auto Select Voltage

11.5

12.5

ICC3

VCC Supply Current(Program & Verify)

IPP2

VPP Supply Current(Program)

CE = VIL

VCC1

Fast Programming Supply Voltage

6.00

6.50

VPP1

Fast Programming Voltage

12.5

13.0

27C512-10

27C512-12

27C512-15

SYMBOL

PARAMETER

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

UNIT

CONDITIONS

tACC

Address to Output Delay

100

120

150

CE = OE = VIL

tCE

Chip Enable to Output Delay

100

120

150

OE = VIL

tOE

Output Enable to Output

CE = VIL

Delay

tDF

OE High to Output Float,

or CE High to Output Float

tOH

Output Hold from Address,

CE or OE which ever occurred

first

AC CHARACTERISTICS

27C512-45

27C512-55

27C512-70

27C512-90

SYMBOL PARAMETER

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

UNIT CONDITIONS

tACC

Address to Output Delay

CE = OE = VIL

tCE

Chip Enable to Output Delay

OE = VIL

tOE

Output Enable to Output

CE = VIL

Delay

tDF

OE High to Output Float,

or CE High to Output Float

tOH

Output Hold from Address,

CE or OE which ever occurred

first

P/N:PM0235

REV. 4.7, NOV. 19, 2002

MX27C512

ORDERING INFORMATION

PLASTIC PACKAGE

PART NO.

ACCESS TIME

OPERATING

STANDBY

OPERATING

PACKAGE

(ns)

CURRENT MAX.(mA)

CURRENT MAX.(uA)

TEMPERATURE

MX27C512PC-45

100

C to 70

28 Pin DIP

MX27C512QC-45

100

C to 70

32 Pin PLCC

MX27C512TC-45

100

C to 70

28 PinTSOP(I)

MX27C512PC-55

100

C to 70

28 Pin DIP

MX27C512QC-55

100

C to 70

32 Pin PLCC

MX27C512TC-55

100

C to 70

28 Pin TSOP(I)

MX27C512PC-70

100

C to 70

28 Pin DIP

MX27C512QC-70

100

C to 70

32 Pin PLCC

MX27C512TC-70

100

C to 70

28 Pin TSOP(I)

MX27C512PC-90

100

C to 70

28 Pin DIP

MX27C512QC-90

100

C to 70

32 Pin PLCC

MX27C512TC-90

100

C to 70

28 Pin TSOP(I)

MX27C512PC-12

120

100

C to 70

28 Pin DIP

MX27C512QC-12

120

100

C to 70

32 Pin PLCC

MX27C512TC-12

120

100

C to 70

28 Pin TSOP(I)

MX27C512PC-15

150

100

C to 70

28 Pin DIP

MX27C512QC-15

150

100

C to 70

32 Pin PLCC

MX27C512TC-15

150

100

C to 70

28 Pin TSOP(I)

MX27C512PI-45

100

-40

C to 85

28 Pin DIP

MX27C512QI-45

100

-40

C to 85

32 Pin PLCC

MX27C512TI-45

100

-40

C to 85

28 PinTSOP(I)

MX27C512PI-55

100

-40

C to 85

28 Pin DIP

MX27C512QI-55

100

-40

C to 85

32 Pin PLCC

MX27C512TI-55

100

-40

C to 85

28 Pin TSOP(I)

MX27C512PI-70

100

-40

C to 85

28 Pin DIP

MX27C512QI-70

100

-40

C to 85

32 Pin PLCC

MX27C512TI-70

100

-40

C to 85

28 Pin TSOP(I)

MX27C512PI-90

100

-40

C to 85

28 Pin DIP

MX27C512QI-90

100

-40

C to 85

32 Pin PLCC

MX27C512TI-90

100

-40

C to 85

28 Pin TSOP(I)

MX27C512PI-12

120

100

-40

C to 85

28 Pin DIP

MX27C512QI-12

120

100

-40

C to 85

32 Pin PLCC

MX27C512TI-12

120

100

-40

C to 85

28 Pin TSOP(I)

MX27C512PI-15

150

100

-40

C to 85

28 Pin DIP

MX27C512QI-15

150

100

-40

C to 85

32 Pin PLCC

MX27C512TI-15

150

100

-40

C to 85

28 Pin TSOP(I)

MX27C512TA-90

100

-40

C to 125

28 Pin TSOP(I)

MX27C512TA-120

120

100

-40

C to 125

28 Pin TSOP(I)

P/N:PM0235

REV. 4.7, NOV. 19, 2002

MX27C512

REVISION HISTORY

Revision #

Description

Page

Date

3.3

Programming Flow Chart corrected, programming verify after whole
array programmed with 1 pulse.

4.0

1) Reduce operating current change from 40mA to 30mA.
2) Add 28-TSOP(I) and 28-SOP packages offering.
3) Eliminate Interactive Programming Mode.

4.1

IPP 100uA --> 10uA

08/07/1997

4.2

CDIP 70/90/100/120/150ns speed grades deleted from ordering

05/07/1998

information.

4.3

Cancel ceramic DIP package type

P1,2,10,12

MAR/02/2000

4.4

Remove 28-pin SOP Package

P1,10

SEP/19/2001

Package Information format changed

P11~13

4.5

Add automotive grade

P6,10

NOV/09/2001

4.6

Remove "ultraviolet erasable" wording

APR/24/2002

4.7

To modify Package Information

P11~13

NOV/19/2002

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