MDT10P55
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P. 1
2003/5 Ver. 1.2
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully
static CMOS technology process to achieve higher
speed and smaller size with the low power
consump-tion and high noise immunity. On chip
memory inclu-des 1K words of ROM, and 72 bytes of
static RAM.
2. Features
The followings are some of the features on the
hardware and software :
u
Fully COMS static design
u
8-bit data bus
u
On chip EPROM size : 1K words
u
Internal RAM size : 72 bytes
u
36 single word instructions
u
14-bit instructions
u
2-level stacks
u
Operating voltage : 2.5 V ~ 6.0 V
u
Operating frequency : 0 ~ 20 MHz
u
The most fast execution time is 200 ns under
20 MHz in all single cycle instructions except
the branch instruction
u
Addressing modes include direct, indirect and
relative addressing modes
u
Power-on Reset
u
Sleep Mode for power saving
u
5 types of oscillator can be selected by
programming option:
INTRC
Internal 4 MHz RC oscillator
RC
Low cost RC oscillator
LFXT
Low frequency crystal oscillator
XTAL
Standard crystal oscillator
HFXT
High frequency crystal oscillator
u
3 oscillator start-up time can be selected by
programming option:
20 ms, 40 ms, 80 ms
u
8-bit real time clock/counter(RTCC) with 8-bit
programmable prescaler
u
On-chip RC oscillator based Watchdog
Timer(WDT)
u
Wake-up from sleep on pin change
3. Applications
The application areas of this MDT10P55 range from
appliance motor control and high speed automotive
to low power remote transmitters/receivers, small
instruments, chargers, toy, automobile and PC
pe-ripheral ... etc.
MDT10P55
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P. 2
2003/5 Ver. 1.2
MDT10P55A3P/MDT10P55A3S
VDD 1
14 VSS
PB5 2
13 PB0
PB4 3
12 PB1
/MCLR 4
11 PB2
PC5/RTCC 5
10 PC0
PC4 6
9 PC1
PC3 7
8 PC2
MDT10P55A4P/MDT10P55A4S
VDD 1
14 VSS
OSC1 2
13 PB0
OSC2/PB4 3
12 PB1
/MCLR 4
11 PB2
PC5/RTCC 5
10 PC0
PC4 6
9 PC1
PC3 7
8 PC2
4. Pin Assignment
MDT10P55A1P/MDT10P55A1S
VDD 1
14 VSS
PB5 2
13 PB0
PB4 3
12 PB1
PB3 4
11 PB2
PC5/RTCC 5
10 PC0
PC4 6
9 PC1
PC3 7
8 PC2
MDT10P55A2P/MDT10P55A2S
VDD 1
14 VSS
OSC1 2
12 PB0
OSC2/PB4 3
12 PB1
PB3 4
11 PB2
PC5/RTCC 5
10 PC0
PC4 6
9 PC1
PC3 7
8 PC2
5. Pin Function Description
Pin Name
I/O
Function Description
PB5~0
I/O
Port B, TTL input level
PB3 input only.
PC4~0
I/O
Port C, TTL input level
PC5/RTCC
I/O
Real Time Clock/Counter, Schmitt Trigger input levels
/MCLR
I
Master Clear, Schmitt Trigger input levels
OSC1
I
Oscillator Input
OSC2
O
Oscillator Output
V
dd
Power supply
V
ss
Ground
MDT10P55
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P. 3
2003/5 Ver. 1.2
6. Memory Map
(A) Register Map
Address
Description
00
Indirect Addressing Register
01
RTCC
02
PC
03
STATUS
04
MSR
06
Port B
07
Port C
08~1F
30~3F
50~5F
70~7F
General purpose registers
(1)IAR ( Indirect Address Register) : R0
(2) RTCC (Real Time Counter/Counter Register) : R1
(3) PC (Program Counter) : R2
Write PC, CALL --- always 0
JUMP --- from instruction word
RTIW, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b5
RTIW, RET --- from STACK
Write PC --- from ALU
JUMP, CALL --- from instruction word
RTIW, RET --- from STACK
MDT10P55
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P. 4
2003/5 Ver. 1.2
(4) STATUS (Status register) : R3
Bit
Symbol
Function
0
1
2
3
4
5
6
7
C
HC
Z
PF
TF
PAGE
----
PCWUF
Carry bit
Half Carry bit
Zero bit
Power down bit
WDT Timer overflow Flag bit
ROM page select bit
Unimplemented
Pin change wake up from sleep
(5) MSR (Memory Bank Select Register) : R4
b7
b6
b5
b4
b3
b2
b1
b0
Read only "1" BANK Select
Indirect Addressing Mode
(6) PORT B : R6
PB5~PB0, I/O Register
PB3 input only.
(7) PORT C: R7
PC5~PC0, I/O Register
(8) TMR (Time Mode Register)
Bit
Symbol
Function
Prescaler Value
RTCC rate
WDT rate
2
--
0
PS2
--
0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
3
PSC
Prescaler assignment bit :
0
--
RTCC
1
--
Watchdog Timer
MDT10P55
This specification are subject to be changed without notice. Any latest information please preview
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P. 5
2003/5 Ver. 1.2
Bit
Symbol
Function
4
TCE
RTCC signal Edge :
0
--
Increment on low-to-high transition on RTCC pin
1
--
Increment on high-to-low transition on RTCC pin
5
TCS
RTCC signal set :
0
--
Internal instruction cycle clock
1
--
Transition on RTCC pin
6
PBPHB
PortB pull-high :
0
--
Enable
1
--
Disable
7
PBWUB
PortB wake-up :
0
--
Enable
1
--
Disable
(9) CPIO B
CPIO C (Control Port I/O Mode Register)
The CPIO register is "write-only"
"0", I/O pin in output mode;
"1", I/O pin in input mode.
(10) Configurable options for EPROM (Set by writer) :
Oscillator Type
Oscillator Start-up Time
INTRC Oscillator
20ms,40ms,80ms
RC Oscillator
20ms,40ms,80ms
HFXT Oscillator
20 ms,40ms,80ms
XTAL Oscillator
20ms,40 ms,80ms
LFXT Oscillator
20ms,40 ms,80 ms
Watchdog Timer control
Watchdog timer disable all the time
Watchdog timer enable all the time
Security state
Security weak Disable
Security Disable
Security Enable
The default security state of EPROM is weak disable. Once the IC was set to
enable or disable, it's forbidden to change.
MDT10P55
This specification are subject to be changed without notice. Any latest information please preview
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P. 6
2003/5 Ver. 1.2
(B) Program Memory
Address
Description
000-3FF
Program memory
000
The starting address of power on, external reset or WDT time-out reset.
8. Reset Condition for all Registers
Register
Address
Power-On Reset
/MCLR Reset
WDT Reset
IAR
00h
xxxx xxxx
uuuu uuuu
uuuu uuuu
RTCC
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PC
02h
0000 0000
0000 0000
0000 0000
STATUS
03h
0001 1xxx
#00# #uuu
#00# #uuu
MSR
04h
110x xxxx
110u uuuu
11uu uuuu
PORT B
06h
--xx xxxx
--uu uuuu
--uu uuuu
PORT C
07h
--xx xxxx
--uu uuuu
--uu uuuu
Note : u
unchanged, x
unknown, -
unimplemented, read as "0"
#
value depends on the condition of the following table
Condition
Status: bit 7
Status: bit 4
Status: bit 3
/MCLR reset (not during SLEEP)
0
u
u
/MCLR reset during SLEEP
0
1
0
WDT reset (not during SLEEP)
0
0
1
WDT reset during SLEEP
0
0
0
Wake-up from SLEEP on pin change
1
1
0
9. Instruction Set :
Instruction Code
Mnemonic
Operands
Function
Operating
Status
010000 00000000
NOP
No operation
None
010000 00000001
CLRWT
Clear Watchdog timer
0
WT
TF, PF
010000 00000010
SLEEP
Sleep mode
0
WT, stop OSC
TF, PF
010000 00000011
TMODE
Load W to TMODE register
W
TMODE
None
010000 00000100
RET
Return
Stack
PC
None
010000 00000rrr
CPIO R
Control I/O port register
W
CPIO r
None
MDT10P55
This specification are subject to be changed without notice. Any latest information please preview
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P. 7
2003/5 Ver. 1.2
Instruction Code
Mnemonic
Operands
Function
Operating
Status
010001 1rrrrrrr
STWR R
Store W to register
W
R
None
011000 trrrrrrr
LDR R, t
Load register
R
t
Z
111010 iiiiiiii
LDWI I
Load immediate to W
I
W
None
010111 trrrrrrr
SWAPR R, t
Swap halves register
[R(0~3)
R(4~7)]
t
None
011001 trrrrrrr
INCR R, t
Increment register
R + 1
t
Z
011010 trrrrrrr
INCRSZ R, t
Increment register, skip if zero
R + 1
t
None
011011 trrrrrrr
ADDWR R, t
Add W and register
W + R
t
C, HC, Z
011100 trrrrrrr
SUBWR R, t
Subtract W from register
R
W
t or
(R+/W+1
t)
C, HC, Z
011101 trrrrrrr
DECR R, t
Decrement register
R
1
t
Z
011110 trrrrrrr
DECRSZ R, t
Decrement register, skip if zero
R
1
t
None
010010 trrrrrrr
ANDWR R, t
AND W and register
R
W
t
Z
110100 iiiiiiii
ANDWI i
AND W and immediate
i
W
W
Z
010011 trrrrrrr
IORWR R, t
Inclu. OR W and register
R
W
t
Z
110101 iiiiiiii
IORWI i
Inclu. OR W and immediate
i
W
W
Z
010100 trrrrrrr
XORWR R, t
Exclu. OR W and register
R
W
t
Z
110110 iiiiiiii
XORWI i
Exclu. OR W and immediate
i
W
W
Z
011111 trrrrrrr
COMR R, t
Complement register
/R
t
Z
010110 trrrrrrr
RRR R, t
Rotate right register
R(n)
R(n-1),
C
R(7), R(0)
C
C
010101 trrrrrrr
RLR R, t
Rotate left register
R(n)
r(n+1),
C
R(0), R(7)
C
C
010000 1xxxxxxx
CLRW
Clear working register
0
W
Z
010001 0rrrrrrr
CLRR R
Clear register
0
R
Z
0000bb brrrrrrr
BCR R, b
Bit clear
0
R(b)
None
0010bb brrrrrrr
BSR R, b
Bit set
1
R(b)
None
0001bb brrrrrrr
BTSC R, b
Bit Test, skip if clear
Skip if R(b)=0
None
0011bb brrrrrrr
BTSS R, b
Bit Test, skip if set
Skip if R(b)=1
None
1000nn nnnnnnnn
LCALL n
Long CALL subroutine
n
PC,
PC+1
Stack
None
1010nn nnnnnnnn
LJUMP n
Long JUMP to address
n
PC
None
110000 nnnnnnnn
CALL n
Call subroutine
n
PC,
PC+1
Stack
None
110001 iiiiiiii
RTIW i
Return, place immediate to W
Stack
PC,i
W
None
11001n nnnnnnnn
JUMP n
JUMP to address
n
PC
None
MDT10P55
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 8
2003/5 Ver. 1.2
Note :
W
:
Working register
b
:
Bit position
WT
:
Watchdog timer
t
:
Target
TMODE
:
TMODE mode register
0
:
Working register
CPIO
:
Control I/O port register
1
:
General register
TF
:
Timer overflow flag
R
:
General register address
PF
:
Power loss flag
C
:
Carry flag
PC
:
Program Counter
HC :
Half carry
OSC
:
Oscillator
Z
:
Zero flag
Inclu.
:
Inclusive `
'
/
:
Complement
Exclu.
:
Exclusive `
'
x
:
Don't care
AND
:
Logic AND `
'
i
:
Immediate data ( 8 bits )
n
:
Immediate address
10. Oscillator start up timer condition :
Oscillator Type
Porwer-on reset
Subsequest resets
INTRC,RC
20ms,40ms,80ms
300us
HF,XT,LF
20ms,40ms,80ms
20ms,40ms,80ms
11. Electrical Characteristics
*Note: Temperature=25C
1.Operation Current :
(1) HF (C=10p) , WDT - enable
4M
10M
20M
Sleep
2.5V
400uA
800uA
1.2mA
1.0uA
3.0V
800uA
1.3mA
2.3mA
10uA
4.0V
1.2mA
2.1mA
3.4mA
15uA
5.0V
1.8mA
3.3mA
4.9mA
30uA
6.4V
2.8mA
5.1mA
7.5mA
60uA
These parameters are for reference only.
(2) XT (C=10p) , WDT - enable
1M
4M
10M
Sleep
2.5V
100uA
250uA
500uA
1.0uA
3.0V
350uA
700uA
1.1mA
10uA
4.0V
500uA
1.1mA
2.0mA
15uA
5.0V
800uA
1.6mA
3.0mA
30uA
6.4V
1.3mA
2.6mA
5.0mA
60uA
These parameters are for reference only.
MDT10P55
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 9
2003/5 Ver. 1.2
(3) RC , WDT Enable , @Vdd = 5.0V
C
R
Freq.
Current
4.7k
7.4M
2.3mA
10k
2.9M
950uA
47k
884K
350uA
100k
452K
200uA
300k
148K
120uA
3p
470k
92K
120uA
4.7k
4.2M
1.3mA
10k
2.2M
750uA
47k
484K
230uA
100k
240K
150uA
300k
80K
120uA
20p
470k
52K
120uA
4.7k
1.4M
550uA
10k
736K
300uA
47k
160K
150uA
100k
80K
120uA
300k
27K
120uA
100p
470k
17K
120uA
4.7k
632K
300uA
10k
312K
200uA
47k
68K
120uA
100k
34K
120uA
300k
11K
120uA
300p
470k
7K
120uA
These parameters are for reference only.
(4) LF (C=10p) , WDT - disable
32K
455K
1M
Sleep
2.5V
30uA
X
X
1.0uA
3.0V
60uA
@3.2V,300uA
@3.2V,300uA
1.0uA
4.0V
150uA
450uA
450uA
1.0uA
5.0V
300uA
750uA
750uA
1.0uA
6.4V
750uA
1.2mA
1.2mA
1.0uA
These parameters are for reference only.
MDT10P55
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 10
2003/5 Ver. 1.2
2. Input Voltage (Vdd = 5V) :
Port
Min
Max
TTL
Vss
1.5V
Vil
Schmitt trigger
Vss
0.8V
TTL
2.5V
Vdd
Vih
Schmitt trigger
3.8V
Vdd
These parameters are for reference only.
3. Output Voltage (Vdd = 5V) :
PA,PB
Condition
Voh
3.4V
Ioh =-20mA
Vol
0.8V
Iol =+20mA
Voh
4.3V
Ioh = -5mA
Vol
0.6V
Iol = +5mA
These parameters are for reference only.
4. Output Current (Max.) (Vdd = 5V) :
Port A:
Current
Source current
25mA
Sink current
25mA
These parameters are for reference only.
Port B:
Current
Source current
25mA
sink current
25mA
These parameters are for reference only.
5. The basic WDT time-out cycle time :
Time
2.5V
25ms
3.0V
23ms
4.0V
20ms
5.0V
19ms
6.3V
18ms
These parameters are for reference only.
MDT10P55
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 11
2003/5 Ver. 1.2
6.
(1)INT_RC,WDT disable
IC1:
4M
Sleep
3.0V
900uA
1.0uA
4.0V
1.5mA
1.0uA
5.0V
2.1mA
1.0uA
These parameters are for reference only.
(2)INT_RC,WDT enable
IC1:
4M
Sleep
3.0V
900uA
5uA
4.0V
1.5mA
15uA
5.0V
2.1mA
30uA
These parameters are for reference only.
7. Min Operation Voltage :
C =>
10p
20p
30p
XT, 20M
2.4V
2.4V
2.6V
HF, 20M
2.5V
2.6V
3.0V
These parameters are for reference only.
RC, 1k, no cap.
2.2V
These parameters are for reference only.
C =>
0p
10p
20p
LF, 1M
2.8V
3.2V
3.4V
These parameters are for reference only.
8. MCLR filter time :
Vdd=5V
time
2us
These parameters are for reference only.
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