MDT10P64

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P.1 2005/6 Ver1.4

1. General Description

This EPROM-Based 8-bit micro-controller uses a fully static

CMOS technology process to achieve higher speed and

smaller size with the low power consumption and high noise

immunity. On chip memory includes 2K words of ROM, and

128 bytes of static RAM.

2. Features

The followings are some of the features on the hardware

and software :

Fully CMOS static design

8-bit data bus

On chip EPROM size : 2.0 K words

Internal RAM size : 161 bytes

(128 general purpose registers, 33 special

registers)

37 single word instructions

14-bit instructions

8-level stacks

Operating voltage : 2.5 V ~ 5.5 V (PRD Disable)

4.5 V ~ 5.5 V (PRD Enable)

Operating frequency : DC ~ 20 MHz

The most fast execution time is 200 ns under 20

MHz in all single cycle instructions except the

branch instruction

Addressing modes include direct, indirect and

relative addressing modes

Power-on Reset

Power edge-detector Reset

Power range-detector Reset

Sleep Mode for power saving

8 interrupt sources:

-External INT pin

-TMR0 timer,TMR1 timer,TMR2 timer

-PortB<7:4> interrupt on change

-CCP,SCM,PCM

Capture,Compare,PWM module

Synchronous serial port with SCM

Parallel communication mode(PCM)

TMR0 : 8-bit real time clock/counter

TMR1 : 16-bit real time clock/count

TMR2 : 8-bit clock/counter(internal)

4 types of oscillator can be selected by

programming option:

Low cost RC oscillator

LFXT

Low frequency crystal oscillator

XTAL

Standard crystal oscillator

HFXT

High frequency crystal oscillator

On-chip RC oscillator based Watchdog Timer(WDT)

33 I/O pins with their own independent direction

control

3. Applications

The application areas of this MDT10P64 range from

appliance motor control and high speed auto-motive to low

power remote transmitters/receivers, pointing devices, and

telecommunications processors, such as Remote

controller, small instruments, toy, automobile and PC

peripheral ... etc.

MDT10P64

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P.3 2005/6 V1.4

5. Pin Function Description

Pin Name

I/O

Function Description

PA0~PA3,PA5

I/O

Port A, TTL input level

RTCC/PA4

I/O

Real Time Clock/Counter, Schmitt Trigger input levels

Open drain output

PB0~PB7

I/O

Port B, TTL input level / PB0:External interrupt input ,

PB4~PB7:Interrupt on pin change

PC0~PC7

I/O

Port C, Schmitt Trigger input levels

PD0~PD7

I/O

Port D, Schmitt Trigger input levels / TTL input level

PE0~PE2

I/O

Port E, Schmitt Trigger input levels / TTL input level

/MCLR

Master Clear, Schmitt Trigger input levels

OSC1/CLKIN

Oscillator Input/external clock input

OSC2/CLKOUT

Oscillator Output/in RC mode

the CLKOUT pin has 1/4 frequency

of CLKIN

Power supply

Ground

6. Memory Map

(A) Register Map

Address

Description

BANK0

Indirect Addressing Register

RTCC

PCL

STATUS

MSR

Port A

Port B

Port C

Port D

Port E

PCHLAT

MDT10P64

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P.4 2005/6 V1.4

Address

Description

INTS

PIFB1

TMR1L

TMR1H

T1STA

TMR2

T2STA

SCMBUF

SCMCTL

CCPL

CCPH

CCPCTL

20~7F

General purpose register

BANK1

TMR

CPIO A

CPIO B

CPIO C

CPIO D

CPIO E

PIEB1

PSTA

T2PER

SCMSTA

A0~BF

General purpose register

(1) IAR ( Indirect Address Register) : R00

(2) RTCC (Real Time Counter/Counter Register) : R01

MDT10P64

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P.5 2005/6 V1.4

(3) PC (Program Counter) : R02,R0A

Write PC --- from PCHLAT

LJUMP, LCALL --- from instruction word

RTWI, RET --- from STACK

A11

A10~A8

A7~A0

Write PC --- from ALU
LJUMP, LCALL --- from instruction word

RTWI, RET, RTFI --- from STACK

(4) STATUS (Status register) : R03

Bit

Symbol

Function

6-7

/PF

/TF

RBS0

----

Carry bit

Half Carry bit

Zero bit

Power down Flag bit

WDT Timer overflow Flag bit

0 : 00H --- 7FH ( Bank0 )

1 : 80H --- FFH ( Bank1 )

General purpose bit

(5) MSR (Memory Bank Select Register) : R04

Memory Bank Select Register :

0 : 00~7F (Bank 0)
1 : 80~FF (Bank1)

Indirect Addressing Mode

(6) PORT A : R05

PA5~PA0, I/O Register

(7) PORT B : R06

PB7~PB0, I/O Register

MDT10P64

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P.6 2005/6 V1.4

(8) PORT C : R07

PC7~PC0, I/O Register

(9) PORT D : R08

PD7~PD0, I/O Register

(10) PORT E : R09

PE2~PE0, I/O Register

(11) PCHLAT : R0A

(12) INTS ( Interrupt Status Register ) : R0B

Bit

Symbol

Function

RBIF

PORT B change interrupt flag. Set when PB <7:4> inputs change

INTF

Set when INT interrupt occurs. INT interrupt flag.

TIF

Set when TMR0 overflows.

RBIE

0 : disable PB change interrupt

1 : enable PB change interrupt

INTS

0 : disable INT interrupt

1 : enable INT interrupt

TIS

0 : disable TMR0 interrupt

1 : enable TMR0 interrupt

PEIE

0 : disable all peripheral interrupt

1 : enable all peripheral interrupt

GIS

0 : disable global interrupt

1 : enable global interrupt

(13) PIFB1 (Peripheral Interrupt Flag Bit) : R0C

Bit

Symbol

Function

TMR1IF

TMR1 interrupt flag

0 : TMR1 did not overflow

1 : TMR1 overflowed

TMR2IF

TMR2 interrupt flag

0 : No TMR2 to T2PER match occurred

1 : TMR2 to T2PER match occurred

CCPIF

CCP interrupt flag

0 : No TMR1 capture/compare occurred

1 : A TMR1 capture/compare occurred

MDT10P64

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P.7 2005/6 V1.4

Bit

Symbol

Function

SCMIF

SCM interrupt flag

No read or write has occurred

A read or a write has occurred

6~4

Unimplemented

PCMIF

PCM interrupt flag

0 : No R/W operation has taken place

1 : A R/W operation has taken place

(14) TMR1L : R0E

The LSB of the 16-bit TMR1

(15) TMR1H : R0F

The MSB of the 16-bit TMR1

(16) T1STA : R10

Bit

Symbol

Function

TMR1ON 0 : Stop TMR1

1 : Enable TMR1

TMR1CLK 0 : Internal clock (Fosc/4)

1 : External clock from pin PC0

/T1SYNC TMR1CLK = 1

0 : Synchronize external clock

1 : Do not synchronize external clock

TMR1CLK = 0

This bit is ignored

T1OSCEN 0 : TMR1 Oscillator is shut off

1 : TMR1 Oscillator is enable

5~4

T1CKPS1

T1CKPS0

1 1 = 1:8 Prescale value

1 0 = 1:4 Prescale value

0 1 = 1:2 Prescale value

0 0 = 1:1 Prescale value

7~6

Unimplemented

(17) TMR2 : R11

TMR2 register

MDT10P64

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P.8 2005/6 V1.4

(18) T2STA : R12

Bit

Symbol

Function

1~0

T2CKPS1

T2CKPS0

0 0 = Prescaler is 1

0 1 = Prescaler is 4

1 x = Prescaler is 16

TMR2ON 0 : TMR2 is off

1 : TMR2 is on

7~3

Unimplemented

(19) SCMBUF : R13

Serial communication port buffer

(20) SCMCTL : R14

Bit

Symbol

Function

3~0

SCM3

SCM0

0 0 0 0 : SCM master mode , clock = Fosc/4

0 0 0 1 : SCM master mode , clock = Fosc/16

0 0 1 0 : SCM master mode , clock = Fosc/64

0 0 1 1 : SCM master mode , clock = TMR2 output/2

0 1 0 0 : SCM slave mode , clock = SCK pin , /SS control enable

0 1 0 1 : SCM slave mode , clock = SCK pin , /SS control disable

CKS

0 : Transmit happens on rising edge , receive on falling edge, Idle state for

clock is low level.

1 : Transmit happens on falling edge , receive on rising edge, Idle state for

clock is high level

SCMEN

0 : Disable SCM, then pc3, pc4, pc5 is I/O prot

1 : Enable SCM

SCMROI

0 : No overflow

1 : Overflow

WCOL

0 : No collision

1 : The SCMBUF is written while it is still transmitting the previous word

(21) CCPL : R15

Capture/Compare/PWM LSB

(22) CCPH : R16

Capture/Compare/PWM MSB

MDT10P64

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P.9 2005/6 V1.4

(23) CCPCTL : R17

Bit

Symbol

Function

3~0

CCPM3

CCPM0

0 0 0 0 : CCP off

0 1 0 0 : Capture mode , every falling edge

0 1 0 1 : Capture mode , every rising edge

0 1 1 0 : Capture mode , every 4

rising edge

0 1 1 1 : Capture mode , every 16

rising edge

1 0 0 0 : Compare mode , set output on match

1 0 0 1 : Compare mode , clear output on match

1 0 1 0 : Compare mode , generate software interrupt on match

1 0 1 1 : Compare mode , trigger special event

1 1 x x : PWM mode

5~4

PWMLSB These bits are the two LSBs of the PWM duty cycle

7~6

Unimplemented

(24) TMR (Time Mode Register) : R81

Bit

Symbol

Function

Prescaler Value

RTCC rate

WDT rate

2~0

PS2~0

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

PSC

Prescaler assignment bit :
0 : RTCC
1 : Watchdog Timer

TCE

RTCC signal Edge :
0 : Increment on low-to-high transition on RTCC pin
1 : Increment on high-to-low transition on RTCC pin

TCS

RTCC signal set :
0 : Internal instruction cycle clock
1 : Transition on RTCC pin

IES

Interrupt edge select
0 : Interrupt on falling edge on PB0
1 : Interrupt on rising edge on PB0

PBPH

PORTB3~0 pull-hi
0 : PORTB3~0 pull-hi are enable
1 : PORTB3~0 pull-hi are disable

(25) CPIO A (Control Port I/O Mode Register) : R85

"0", I/O pin in output mode.

"1", I/O pin in input mode.

MDT10P64

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P.10 2005/6 V1.4

(26) CPIO B (Control Port I/O Mode Register) : R86

"0", I/O pin in output mode.

"1", I/O pin in input mode.

(27) CPIO C (Control Port I/O Mode Register) : R87

"0", I/O pin in output mode.

"1", I/O pin in input mode.

(28) CPIO D (Control Port I/O Mode Register) : R88

"0", I/O pin in output mode.

"1", I/O pin in input mode.

(29) CPIO E (Control Port I/O Mode Register) : R89

Bit

Symbol

Function

2~0

BIT2~BIT0 Port E control port I/O mode bits

0 : I/O pin in output mode

1 : I/O pin in input mode

Unimplemented

PCMSB

0 : General I/O mode

1 : PCM mode

IBOB

0 : No overflow occurred

1 : A write occurred when a previously input word has not been read

OBF

0 : The output buffer has been read

1 : The output buffer still holds

IBF

0 : No data has been received

1 : A data has been received and is waiting to be read

(30) PIEB1 : R8C

Bit

Symbol

Function

TMR1IE

TMR1 interrupt enable bit

0 : Disable TMR1 interrupt

1 : Enable TMR1 interrupt

TMR2IE

TMR2 interrupt enable bit

0 : Disable TMR2 interrupt

1 : Enable TMR2 interrupt

CCP1IE

CCP1 interrupt enable bit

disable CCP1 interrupt

enable CCP1 interrupt

SCMIE

SCM interrupt enable bit

0 : Disable SCM interrupt

1 : Enable SCM interrupt

MDT10P64

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P.11 2005/6 V1.4

Bit

Symbol

Function

6~4

Unimplemented

PCMIE

PCM interrupt enable bit

0 : Disable PCM interrupt

1 : Enable PCM interrupt

(31) PSTA : R8E

Bit Symbol

Function

PRDB

0 : Power range-detector Reset occurred
1 : No Power range-detector Reset Occurred

PORB

0 : Power on Reset occurred
1 : No Power on Reset occurred

(32) T2PER : R92

Timer2 period

(33) SCMSTA : R94

Bit

Symbol

Function

0 : Receive not complete

1 : Receive complete

7~1

Unimplemented

(34) Configurable options for EPROM (Set by writer) :

Oscillator Type

RC Oscillator

HFXT Oscillator

XTAL Oscillator

LFXT Oscillator

Watchdog Timer control

Watchdog timer disable all the time

Watchdog timer enable all the time

Power-range control

Power-range disable

Power-range enable

MDT10P64

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P.12 2005/6 V1.4

Oscillator-start Timer control

0ms

75ms

Power-edge Detect

Security state

PED Disable

Security Disable

PED Enable

Security Enable

(B) Program Memory

Address

Description

000-7FF

Program memory

000

The starting address of power on, external reset or WDT time-out reset.

004

Interrupt vector

7. Reset Condition for all Registers

Register

Address

Power-On Reset,

Power range detector

Reset

/MCLR or WDT Reset

Wake-up from SLEEP

IAR

00h

N/A

RTCC

01h

xxxx xxxx

uuuu uuuu

0Ah,02h

0000 0000 0000

PC+1

STATUS

03h

0001 1xxx

000# #uuu

MSR

04h

xxxx xxxx

uuuu uuuu

PORT A

05h

--xx xxxx

--uu uuuu

PORT B

06h

xxxx xxxx

uuuu uuuu

PORT C

07h

xxxx xxxx

uuuu uuuu

PORT D

08h

xxxx xxxx

uuuu uuuu

PORT E

09h

---- -xxx

---- -uuu

PCHLAT

0Ah

---0 0000

---u uuuu

INTS

0Bh

0000 000x

0000 000u

uuuu uuuu

PIFB1

0Ch

---- 0000

---- uuuu

TMR1H

0Fh

xxxx xxxx

uuuu uuuu

T1STA

10h

--00 0000

--uu uuuu

MDT10P64

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P.13 2005/6 V1.4

Register

Address

Power-On Reset,

Power range detector

Reset

/MCLR or WDT Reset

Wake-up from SLEEP

TMR1L

0Eh

xxxx xxxx

uuuu uuuu

TMR2

11h

0000 0000

uuuu uuuu

T2STA

12h

---- -000

---- -uuu

SCMBUF

13h

xxxx xxxx

uuuu uuuu

SCMCTL

14h

0000 0000

uuuu uuuu

CCPL

15h

xxxx xxxx

uuuu uuuu

CCPH

16h

xxxx xxxx

uuuu uuuu

CCPCTL

17h

--00 0000

--uu uuuu

TMR

81h

1111 1111

uuuu uuuu

CPIOA

85h

--11 1111

--uu uuuu

CPIOB

86h

1111 1111

uuuu uuuu

CPIOC

87h

1111 1111

uuuu uuuu

CPIOD

88h

1111 1111

uuuu uuuu

CPIOE

89h

0000 -111

uuuu -uuu

PIEB1

8Ch

0--- 0000

u--- uuuu

PSTA

8Eh

---- --0u

---- --uu

T2PER

92h

1111 1111

SCMSTA

94h

---- ---0

---- ---u

Note : u

unchanged, x

unknown, -

unimplemented, read as "0"

value depends on the condition of the following table

Condition

Status: bit 4

Status: bit 3

PSTA: bit 1

PSTA: bit 0

/MCLR reset (not during SLEEP)

/MCLR reset during SLEEP

WDT reset (not during SLEEP)

WDT reset during SLEEP

Power-on reset

Power-range reset

Note : u

unchanged, x

unknown, -

unimplemented, read as "0"

MDT10P64

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P.14 2005/6 V1.4

8. Instruction Set :

Instruction Code

Mnemonic

Operands

Function

Operating

Status

010000 00000000

NOP

No operation

None

010000 00000001

CLRWT

Clear Watchdog timer

TF, PF

010000 00000010

SLEEP

Sleep mode

WT, stop OSC

TF, PF

010000 00000011

TMODE

Load W to TMODE register

TMODE

None

010000 00000100

RET

Return from subroutine

Stack

None

010000 00000rrr

CPIO R

Control I/O port register

CPIO r

None

010001 1rrrrrrr

STWR R

Store W to register

None

011000 trrrrrrr

LDR R, t

Load register

111010 iiiiiiii

LDWI I

Load immediate to W

None

010111 trrrrrrr

SWAPR R, t

Swap halves register

[R(0~3)

R(4~7)]

None

011001 trrrrrrr

INCR R, t

Increment register

R + 1

011010 trrrrrrr

INCRSZ R, t

Increment register, skip if zero

R + 1

None

011011 trrrrrrr

ADDWR R, t

Add W and register

W + R

C, HC, Z

011100 trrrrrrr

SUBWR R, t

Subtract W from register

t or

(R+/W+1

C, HC, Z

011101 trrrrrrr

DECR R, t

Decrement register

011110 trrrrrrr

DECRSZ R, t

Decrement register, skip if zero

None

010010 trrrrrrr

ANDWR R, t

AND W and register

110100 iiiiiiii

ANDWI i

AND W and immediate

010011 trrrrrrr

IORWR R, t

Inclu. OR W and register

110101 iiiiiiii

IORWI i

Inclu. OR W and immediate

010100 trrrrrrr

XORWR R, t

Exclu. OR W and register

110110 iiiiiiii

XORWI i

Exclu. OR W and immediate

011111 trrrrrrr

COMR R, t

Complement register

010110 trrrrrrr

RRR R, t

Rotate right register

R(n)

R(n-1),

R(7), R(0)

010101 trrrrrrr

RLR R, t

Rotate left register

R(n)

r(n+1),

R(0), R(7)

010000 1xxxxxxx

CLRW

Clear working register

010001 0rrrrrrr

CLRR R

Clear register

0000bb brrrrrrr

BCR R, b

Bit clear

R(b)

None

0010bb brrrrrrr

BSR R, b

Bit set

R(b)

None

0001bb brrrrrrr

BTSC R, b

Bit Test, skip if clear

Skip if R(b)=0

None

0011bb brrrrrrr

BTSS R, b

Bit Test, skip if set

Skip if R(b)=1

None

MDT10P64

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P.15 2005/6 V1.4

Instruction Code

Mnemonic

Operands

Function

Operating

Status

100nnn nnnnnnnn

LCALL n

Long CALL subroutine

PC,

PC+1

Stack

None

101nnn nnnnnnnn

LJUMP n

Long JUMP to address

None

110111 iiiiiiii

ADDWI i

Add immediate to W

W+i

C,HC,Z

110001 iiiiiiii

RTWI i

Return, place immediate to W

Stack

PC,i

None

111000 iiiiiiii

SUBWI i

Subtract W from immediate

i-W

C,HC,Z

010000 00001001

RTFI

Reture from interrupt

Stack

PC,1

GIS

None

Note :

Working register

Bit position

Watchdog timer

Target

TMODE

TMODE mode register

Working register

CPIO

Control I/O port register

General register

Timer overflow flag

General register address

Power loss flag

Carry flag

Program Counter

HC :

Half carry

OSC

Oscillator

Zero flag

Inclu.

Inclusive `

Complement

Exclu.

Exclusive `

Don't care

AND

Logic AND `

' I :

Immediate data ( 8 bits )

9. Electrical Characteristics

*Note: Temperature=25�C
1.Operation Current :

(1) HF (C=10p) , WDT - disable, PRD � disable

10M

20M

Sleep

2.5V

330u

710u

1.3m

<1u

3.0V

480u

910u

1.7m

<1u

4.0V

720u

1.4m

2.8m

<1u

5.0V

1.4m

2.6m

4.3m

<1u

5.5V

1.8m

3.5m

5.7m

<1u

These parameters are for reference only.

(2) XT (C=10p) , WDT - disable, PRD � disable

10M

Sleep

2.5V

100u

310u

600u

<1u

3.0V

220u

450u

860u

<1u

4.0V

310u

660u

1.3m

<1u

5.0V

560u

1.0m

1.9m

<1u

5.5V

780u

1.5m

2.9m

<1u

These parameters are for reference only.

MDT10P64

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P.16 2005/6 V1.4

(3) LF (C=10p) , WDT - disable, PRD - disable,

32K

455K

Sleep

2.5V

10u

@2.7V 50u

80u

<1u

3.0V

15u

60u

90u

<1u

4.0V

25u

80u

150u

<1u

5.0V

40u

140u

230u

<1u

5.5V

80u

250u

390u

<1u

These parameters are for reference only.

(4) RC, WDT - disable; PRD - disable; @Vdd = 5.0V

Freq.

Current

4.7k

8.4M

1.7m

10k

4.5M

1.1m

47k

1.1M

430u

100k

520K

330u

300k

180K

165u

470k

110K

155u

4.7k

3.2M

1.3m

10k

2.2M

640u

47k

500K

230u

100k

240K

180u

300k

81.2K

150u

20p

470k

51.6K

145u

4.7k

1.4M

500u

10k

688K

370u

47k

152K

165u

100k

72.8K

150u

300k

24.4K

140u

100p

470k

15.6K

138u

4.7k

592K

350u

10k

292K

190u

47k

64K

147u

100k

30.8K

141u

300k

10.4K

137u

300p

470k

6.4K

136u

These parameters are for reference only.

MDT10P64

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P.17 2005/6 V1.4

2. Input Voltage (Vdd = 5V) :

Port

Min

Max

TTL

Vss

0.8V

Vil

Schmitt trigger

Vss

0.6V

TTL

3.0V

Vdd

Vih

Schmitt trigger

3.8V

Vdd

These parameters are for reference only.

Input Voltage (Vdd = 3V) :

Port

Min

Max

TTL

Vss

0.4V

Vil

Schmitt trigger

Vss

0.2V

TTL

2.0V

Vdd

Vih

Schmitt trigger

2.6V

Vdd

These parameters are for reference only.

3. Output Voltage (Vdd = 5V) :

PA,PB

Condition

Voh

3.5V

Ioh = -20mA

Vol

0.9V

Iol = 20mA

Voh

4.2V

Ioh = -5mA

Vol

0.7V

Iol = 5mA

These parameters are for reference only.

4. Output Current (Max.) (Vdd = 5V) :

I/O Port

Current

source current

25mA

sink current

40mA

These parameters are for reference only.

MDT10P64

This specification are subject to be changed without notice. Any latest information please preview

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P.18 2005/6 V1.4

5. The basic WDT time-out cycle time :

Time

2.5V

3.0V

4.0V

5.0V

5.5V

Unit = ms

These parameters are for reference only.

6.PRD :

(1)PRD reset voltage :

Voltage

Vih

4.0

�

10%

Vil

3.6

�

10%

Unit = V

These parameters are for reference only.

(2) PRD reset current :

Current

5.0V

120

4.0V

100

Unit = uA

These parameters are for reference only.

7.Pull high resistor :

Vdd

PB3~0 Pull high

Unit = K Ohm

These parameters are for reference only.

8.MCLR filter time :

Vdd=5V

time

640

Unit = ns

These parameters are for reference only.

Электронный компонент: MDT10P64