AH-27
Micrel
3-202
1997
Application Hint 27
Slowing Voltage Regulator Turn-On
by Jerry Kmetz
Slow Turn-On Circuits
The turn-on time interval of a voltage regulator is essentially
determined by the bandwidth of the regulator, its maximum
output current, and the load capacitance. To some extent the
rise time of the applied input voltage (which is normally quite
short, tens of milliseconds, or less) also affects the turn-on
time. However, the regulator output voltage typically steps
abruptly at turn-on. Increasing the turn-on interval via some
form of slew-limiting decreases the surge current seen by
both the regulator and the system. This application hint
addresses designing circuitry to change the step-function to
a smoother RC charge waveform.
Various performance features exist between the three cir-
cuits that are presented. These are (1) whether stability is
impacted, (2) whether start-up output is 0V, and (3) whether
the circuit quickly recovers from momentarily interrupted
input voltage or shorted output. The following table summa-
rizes the features of each circuit:
Circuit
Stability
Start-Up
V
IN
Interrupt
V
OUT
Short
Number Impacted? Pedestal?
Recovery?
Recovery?
1
yes
1.2V
no
no
2
no
1.8V
no
yes
3
no
0V
yes
no
Slow Turn-On Circuit Performance Features
1. The Simplest Approach
Figure 1 illustrates a typical LDO voltage regulator, the
MIC29153, with an additional capacitor (C
T
) in parallel with
the series leg (R1) of the feedback voltage divider. Since the
voltage (V
ADJ
) will be maintained at V
REF
by the regulator
loop, the output of this circuit will still rapidly step to V
REF
and
then rise slowly. Since V
REF
is usually only about 1.2V, this
eliminates a large part of the surge current.
As C
T
charges, the regulator output (V
OUT
) asymptotically
approaches the desired value. If a turn-on time of 300
milliseconds is desired then about three time constants
should be allowed for charge time:
then 3
= 0.3s, or
= 0.1s = R1
C
T
= 300k
0.33
F.
Figure 2 shows the waveforms of the circuit of Figure 1. This
circuit has three shortcomings: (1) the approximately 1.2V
step at turn-on, (2) the addition of capacitor C
T
places a zero
in the closed-loop transfer function (which affects frequency
and transient responses and can potentially cause stability
problems) and (3) the recovery time associated with a mo-
mentarily short-circuited output may be unacceptably long.
This is because if the output is shorted C
T
is discharged only
by R2; if the short is removed before C
T
is fully discharged the
regulator output will not exhibit the desired turn-on behavior.
Typical LDO Regulator
V
REF
V
OUT
C
T
0.33F
R1
300k
R2
100k
V
ADJ
OUT
IN
GND
C
IN
22F
ADJ
MIC29153
V
IN
C
OUT
22F
Figure 1. Simplest Slow Turn-On Circuit
Figure 2. Turn-On Behavior for Circuit of Figure 1
0
0
2
0.2
4
0.4
0.6
0.8
10
5
1.0
0
OUTPUT VOLTAGE (V) INPUT VOLTAGE (V)
TIME (s)
1997
3-203
AH-27
Micrel
3
Typical LDO Regulator
V
REF
V
OUT
C
T
0.33F
R1
300k
R2
100k
V
ADJ
OUT
IN
GND
C
IN
22F
ADJ
MIC29153
V
IN
C
OUT
22F
D1, D2 = 1N4148
D2
D1
Figure 3. Improved Slow Turn-On Circuit
2. Improved Simple Approach
Figure 3 is an improvement on the circuit of Figure 1 in that
it addresses the problems of potential instability and recov-
ery time. Diode D1 is added to the circuit to decouple the
(charged) capacitor from the feedback network, thereby
eliminating the effect of C
T
on the closed-loop transfer
function. Because of the non-linear effect of D1 being in
series with C
T
, there is a slightly longer "tail" associated with
approaching the final output voltage at turn-on. In the event
of a momentarily shorted output, diode D2 provides a low-
impedance discharge path for C
T
and thus assures the
desired turn-on behavior upon recovery.
Figure 4 shows the waveforms of the circuit of Figure 3. Note
that the initial step-function output is now 0.6V higher than
with the circuit of Figure 1. This approximately 1.8V turn-on
pedestal may be objectionable, especially in applications
where the output voltage is relatively low by design.
0
0
2
0.2
4
0.4
0.6
0.8
10
5
1.0
0
OUTPUT VOLTAGE (V) INPUT VOLTAGE (V)
TIME (s)
Figure 4. Turn-On Behavior of Figure 3
3. Eliminating Initial Start-Up Pedestal
The circuits of Figures 1 and 3 depend upon the existence of
an output voltage (to create V
ADJ
) and, therefore, produce the
initial step-function voltage pedestals of about 1.2V and 1.8V,
as can be seen in Figures 2 and 4, respectively. The approach
of Figure 5 facilitates placing the output voltage origin at zero
volts because V
CONTROL
is derived from the input voltage. No
reactive component is added to the feedback circuit. The
value of R
T
should be considerably smaller than R3 to assure
that the junction of R
T
and C
T
acts like a voltage source
driving R3 and so R
T
is the primary timing control. If sufficient
current is introduced into the loop summing junction (via R3)
to generate V
ADJ
V
REF
, then V
OUT
will be zero volts. As R
T
charges C
T
the voltage V
CONTROL
decays, which would
eventually result in V
ADJ
< V
REF
. However, since in normal
operation V
ADJ
= V
REF
, V
OUT
will become greater than zero
volts. The process continues until V
CONTROL
decays to
V
REF
+0.6V and V
OUT
reaches the desired value. This circuit
requires a regulator with an enable function, (e.g., the
MIC29152) because a small (< 2V) spike is generated coin-
cident with application of a step-function input voltage. Ca-
pacitor C1 and resistor R4 provide a short hold-off timing
function that eliminates this spike.
Figure 6 illustrates the timing of this operation. The small
initial delay (about 40 milliseconds) is the time interval during
which V
ADJ
> V
REF
. Since V
IN
is usually fairly consistent in
value R3 may be chosen to minimize this delay. Note that if
R3 is calculated based on the minimum foreseen V
IN
(as
described below), then higher values of V
IN
will produce
additional delay before the turn-on ramp begins. Conversely,
if V
IN (max)
is used for the calculation of R3, then lower values
of V
IN
will not produce the desired turn-on characteristic;
instead, there will be a small initial step-function prior to the
desired turn-on ramp. Recovery from a momentarily shorted
output is not addressed by this circuit, but interrupted input
voltage is handled properly. Notice that the build-up of
regulator output voltage differs from the waveforms of Fig-
ures 2 and 4 in that it is more ramp-like . This is because only
an initial portion of the RC charge waveform is used; i.e., while
V
CONTROL
> V
REF
+0.6V. The actual time constant used for
Figure 5 is 0.33 second, so 3
is one second. As shown by
Figure 6, this provides about 600 milliseconds of ramp time,
AH-27
Micrel
3-204
1997
Typical LDO Regulator
V
REF
V
OUT
R1
300k
R2
100k
V
ADJ
OUT
IN
GND
C
IN
22F
ADJ
MIC29152
V
IN
C
OUT
22F
D1
C1
0.1F
R
T
33k
C
T
10F
R4
240k
EN
D2
1N4001
R3
240k
V
CONTROL
1N4148
Figure 5. Slow Turn-On Without Pedestal Voltage
0
0
2
0.2
4
0.4
0.6
0.8
10
5
1.0
0
OUTPUT VOLTAGE (V) INPUT VOLTAGE (V)
TIME (s)
Figure 6. Turn-On Behavior of Figure 5
which corresponds to the first 60% of the capacitor RC charge
curve. R3 is calculated as follows:
at turn-on time force
V
ADJ
= 1.5V
(just slightly higher than V
REF
)
then
I
=
V
R1
R2
R1
R2
CONTROL
1 5
.
+
and
R3 =
V
0.6V
I
IN min
CONTROL
-
Since the MIC29152 is a low-dropout regulator, 6V was
chosen for V
IN
(min). This corresponds to the small (approxi-
mately 40 msec) delay before the output begins to rise. With
7V input the initial delay is considerably more noticeable.
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