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March 2005

M9999-033105

MIC2592B

Dual-Slot PCI Express Hot-Plug Controller

General Description

The MIC2592B is a dual-slot power controller supporting the

power distribution requirements for Peripheral Component

Interconnect Express (PCI Express) Hot-Plug compliant

systems. The MIC2592B provides complete power control

support for two PCI Express slots, including the 3.3VAUX

defi ned by the PCI Express standards. Support for 12V, 3.3V,

and 3.3VAUX supplies is provided including programmable

constant-current inrush limiting, voltage supervision, pro-

grammable current limit, and circuit breaker functions. These

features provide comprehensive system protection and fault

isolation. The MIC2592B also incorporates an SMBus interface

via which complete status of each slot is provided.
All support documentation can be found on Micrel's web site

at www.micrel.com.

Micrel, Inc. · 1849 Fortune Drive · San Jose, CA 95131 · USA · tel + 1 (408) 944-0800 · fax + 1 (408) 474-1000 · http://www.micrel.com

Features

· Supports two independent PCI Express slots

· SMBus interface for slot power control and status

· Voltage-tolerant I/O for compatibility with SMBus 2.0

systems

· 12V, 3.3V, and 3.3VAUX supplies supported per PCI

Express Specifi cation v1.0a

- Intergrated power MOSFETs for 3.3VAUX

- Intergrated power MOSFETs for 3.3V

rails

- Standby operation for Wake-on-LAN applications with

low backfeed on Main +12V and +3.3V rails.

· Programmable inrush current limiting

· Active current regulation controls inrush current

· Electronic circuit breaker for each supply to each slot

· High accuracies for both circuit breaker trip points and

nuisance trip prevention timers

· Dual level fault detection for quick fault response without

nuisance tripping

· Thermal isolation between circuitry for Slot A and Slot B

· Two General Purpose Input pins suitable for interface to

logic and switches.

Ordering Information

Part Number

12V and 3V

3.3VAUX

Package

Standard

Pb-Free

Fast-Trip Thresholds Current Limit

MIC2592B 2BTQ MIC2592B 2YTQ

100mV

0.375A

48 Pin TQFP

MIC2592B 3BTQ* MIC2592B 3YTQ*

150mV

0.375A

48 Pin TQFP

MIC2592B 5BTQ* MIC2592B 5YTQ*

Disabled

0.375A

48 Pin TQFP

* Contact factory for availability

Standard

Pb-Free

Fast-Trip Thresholds Current Limit

MIC2592B 2BTQ MIC2592B 2YTQ

100mV

0.375A

48 Pin TQFP

MIC2592B 3BTQ* MIC2592B 3YTQ*

150mV

0.375A

48 Pin TQFP

MIC2592B 5BTQ* MIC2592B 5YTQ*

Disabled

0.375A

48 Pin TQFP

Part Number

12V and 3V

3.3VAUX

Package

Standard

Pb-Free

Fast-Trip Thresholds Current Limit

MIC2592B 2BTQ MIC2592B 2YTQ

100mV

0.375A

48 Pin TQFP

MIC2592B 3BTQ* MIC2592B 3YTQ*

150mV

0.375A

48 Pin TQFP

MIC2592B 5BTQ* MIC2592B 5YTQ*

Disabled

0.375A

48 Pin TQFP

Part Number

12V and 3V

3.3VAUX

Package

MIC2592B 2BTQ MIC2592B 2YTQ

100mV

0.375A

48 Pin TQFP

MIC2592B 3BTQ* MIC2592B 3YTQ*

150mV

0.375A

48 Pin TQFP

MIC2592B 5BTQ* MIC2592B 5YTQ*

Disabled

0.375A

48 Pin TQFP

Part Number

12V and 3V

3.3VAUX

Package

Standard

Pb-Free

Fast-Trip Thresholds Current Limit

MIC2592B 2BTQ MIC2592B 2YTQ

100mV

0.375A

48 Pin TQFP

MIC2592B 3BTQ* MIC2592B 3YTQ*

150mV

0.375A

48 Pin TQFP

MIC2592B 5BTQ* MIC2592B 5YTQ*

Disabled

0.375A

48 Pin TQFP

Part Number

12V and 3V

3.3VAUX

Package

Part Number

12V and 3V

3.3VAUX

Package

MIC2592B

Micrel

March 2005

M9999-033105

Pin Description

Pin Number

Pin Name

Pin Function

12VINA

12V Supply Power and Sense Inputs [A/B]: Two pins are provided for Kelvin.

12VINB

connection (one for each slot). Pin 5 is the (+) Kelvin-sense connection to

the supply side of the sense resistor for 12V Slot A. Pin 32 is the (+) Kelvin

sense connection to the supply side of the sense resistor for 12V Slot B.

These two pins must ultimately connect to each other as close as possible at

the MIC2592B controller in order to eliminate any IR drop between these

pins. An undervoltage lockout circuit (UVLO) prevents the switches from

turning on while this input is less than its lockout threshold.

3VINA

3.3V Supply Power and Sense Inputs [A/B]: Two pins are provided for

3VINB

connection (one for each slot). Pin 12 is the (+) Kelvin-sense connection to

the supply side of the sense resistor for 3V Slot A. Pin 25 is the (+) Kelvin

sense connection to the supply side of the sense resistor for 3V Slot B.

These two pins must ultimately connect to each other as close as possible at

the MIC2592B controller in order to eliminate any IR drop between these

pins. An undervoltage lockout circuit (UVLO) prevents the switches from

turning on while this input is less than its lockout threshold.

3VOUTA

3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs. Used to

3VOUTB

monitor the 3.3V output voltages for Power-is-Good status.

12VOUTA

12V Power-Good Sense Inputs: Connect to 12V[A/B] outputs. Used to

12VOUTB

monitor the 12V output voltages for Power-is-Good status.

12VSENSEA

12V Circuit Breaker Sense Inputs: The current limit thresholds are set

12VSENSEB

by connecting sense resistors between these pins and 12VIN[A/B]. When

the current limit threshold of IR = 50mV is reached, the 12VGATE[A/B] pin

is modulated to maintain a constant voltage across the sense resistor and

therefore a constant current into the load. If the 50mV threshold is exceeded

for t

FLT

, the circuit breaker is tripped and the GATE pin for the affected 12V

FLT

supply's external MOSFET is immediately pulled high.

3VSENSEA

3V Circuit Breaker Sense Inputs: The current limit thresholds are set by

3VSENSEB

connecting sense resistors between these pins and 3VIN[A/B]. When the

current limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is

modulated to maintain a constant voltage across the sense resistor and

therefore a constant current into the load. If the 50mV threshold is exceeded

for t

FLT

, the circuit breaker is tripped and the GATE pin for the affected 3V

FLT

supply's external MOSFET is immediately pulled low.

12VGATEA

12V Gate Drive Outputs: Each pin connects to the gate of an external

12VGATEB

P-Channel MOSFET. During power-up, the C

GATE

and the C

of the

MOSFETs are connected to a 25µA current sink. This controls the value of

dv/dt seen at the source of the MOSFETs.

During current limit events, the voltage at this pin is adjusted to maintain

constant current through the switch for a period of t

FLT

. Whenever an

FLT

overcurrent, thermal shutdown, or input undervoltage fault condition occurs,

the GATE pin for the affected slot is immediately brought high. These pins

are charged by an internal current source during power-down. Also, the 3V

supply for the affected slot is shut-down.

3VGATEA

3V Gate Drive Outputs: Each pin connects to the gate of an external

3VGATEB

N-Channel MOSFET. During power-up, the C

GATE

and the C

of the

MOSFETs are connected to a 25µA current source. This controls the value

of dv/dt seen at the source of the MOSFETs, and hence the current fl owing

into the load capacitance.

During current limit events, the voltage at this pin is adjusted to maintain

constant current through the switch for a period of t

FLT

. Whenever an

FLT

overcurrent, thermal shutdown, or input undervoltage fault condition occurs,

the GATE pin for the affected slot is immediately brought low. During power-

down, these pins are discharged by an internal current source. Also, the 12V

supply for the affected slot is shut down.

Pin Number

Pin Name

Pin Function

12VINB

connection (one for each slot). Pin 5 is the (+) Kelvin-sense connection to

the supply side of the sense resistor for 12V Slot A. Pin 32 is the (+) Kelvin

sense connection to the supply side of the sense resistor for 12V Slot B.

These two pins must ultimately connect to each other as close as possible at

the MIC2592B controller in order to eliminate any IR drop between these

pins. An undervoltage lockout circuit (UVLO) prevents the switches from

turning on while this input is less than its lockout threshold.

3VINA

3.3V Supply Power and Sense Inputs [A/B]: Two pins are provided for

3VINB

connection (one for each slot). Pin 12 is the (+) Kelvin-sense connection to

the supply side of the sense resistor for 3V Slot A. Pin 25 is the (+) Kelvin

sense connection to the supply side of the sense resistor for 3V Slot B.

These two pins must ultimately connect to each other as close as possible at

the MIC2592B controller in order to eliminate any IR drop between these

pins. An undervoltage lockout circuit (UVLO) prevents the switches from

turning on while this input is less than its lockout threshold.

3VOUTA

3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs. Used to

3VOUTB

monitor the 3.3V output voltages for Power-is-Good status.

12VOUTA

12V Power-Good Sense Inputs: Connect to 12V[A/B] outputs. Used to

12VOUTB

monitor the 12V output voltages for Power-is-Good status.

12VSENSEA

12V Circuit Breaker Sense Inputs: The current limit thresholds are set

12VSENSEB

by connecting sense resistors between these pins and 12VIN[A/B]. When

the current limit threshold of IR = 50mV is reached, the 12VGATE[A/B] pin

is modulated to maintain a constant voltage across the sense resistor and

therefore a constant current into the load. If the 50mV threshold is exceeded

for t

supply's external MOSFET is immediately pulled high.

3VSENSEA

3V Circuit Breaker Sense Inputs: The current limit thresholds are set by

3VSENSEB

connecting sense resistors between these pins and 3VIN[A/B]. When the

current limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is

modulated to maintain a constant voltage across the sense resistor and

therefore a constant current into the load. If the 50mV threshold is exceeded

for t

supply's external MOSFET is immediately pulled low.

12VGATEA

12V Gate Drive Outputs: Each pin connects to the gate of an external

12VGATEB

P-Channel MOSFET. During power-up, the C

MOSFETs are connected to a 25µA current sink. This controls the value of

dv/dt seen at the source of the MOSFETs.

During current limit events, the voltage at this pin is adjusted to maintain

constant current through the switch for a period of t

overcurrent, thermal shutdown, or input undervoltage fault condition occurs,

the GATE pin for the affected slot is immediately brought high. These pins

are charged by an internal current source during power-down. Also, the 3V

supply for the affected slot is shut-down.

3VGATEA

3V Gate Drive Outputs: Each pin connects to the gate of an external

3VGATEB

N-Channel MOSFET. During power-up, the C

MOSFETs are connected to a 25µA current source. This controls the value

of dv/dt seen at the source of the MOSFETs, and hence the current fl owing

into the load capacitance.

During current limit events, the voltage at this pin is adjusted to maintain

constant current through the switch for a period of t

overcurrent, thermal shutdown, or input undervoltage fault condition occurs,

the GATE pin for the affected slot is immediately brought low. During power-

down, these pins are discharged by an internal current source. Also, the 12V

supply for the affected slot is shut down.

Pin Number

Pin Name

Pin Function

12VINA

12V Supply Power and Sense Inputs [A/B]: Two pins are provided for Kelvin.

12VINB

connection (one for each slot). Pin 5 is the (+) Kelvin-sense connection to

the supply side of the sense resistor for 12V Slot A. Pin 32 is the (+) Kelvin

sense connection to the supply side of the sense resistor for 12V Slot B.

These two pins must ultimately connect to each other as close as possible at

the MIC2592B controller in order to eliminate any IR drop between these

pins. An undervoltage lockout circuit (UVLO) prevents the switches from

turning on while this input is less than its lockout threshold.

3VINA

3.3V Supply Power and Sense Inputs [A/B]: Two pins are provided for

3VINB

connection (one for each slot). Pin 12 is the (+) Kelvin-sense connection to

the supply side of the sense resistor for 3V Slot A. Pin 25 is the (+) Kelvin

sense connection to the supply side of the sense resistor for 3V Slot B.

These two pins must ultimately connect to each other as close as possible at

the MIC2592B controller in order to eliminate any IR drop between these

pins. An undervoltage lockout circuit (UVLO) prevents the switches from

turning on while this input is less than its lockout threshold.

3VOUTA

3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs. Used to

3VOUTB

monitor the 3.3V output voltages for Power-is-Good status.

12VOUTA

12V Power-Good Sense Inputs: Connect to 12V[A/B] outputs. Used to

12VOUTB

monitor the 12V output voltages for Power-is-Good status.

12VSENSEA

12V Circuit Breaker Sense Inputs: The current limit thresholds are set

12VSENSEB

by connecting sense resistors between these pins and 12VIN[A/B]. When

the current limit threshold of IR = 50mV is reached, the 12VGATE[A/B] pin

is modulated to maintain a constant voltage across the sense resistor and

therefore a constant current into the load. If the 50mV threshold is exceeded

for t

supply's external MOSFET is immediately pulled high.

3VSENSEA

3V Circuit Breaker Sense Inputs: The current limit thresholds are set by

3VSENSEB

connecting sense resistors between these pins and 3VIN[A/B]. When the

current limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is

modulated to maintain a constant voltage across the sense resistor and

therefore a constant current into the load. If the 50mV threshold is exceeded

for t

supply's external MOSFET is immediately pulled low.

12VGATEA

12V Gate Drive Outputs: Each pin connects to the gate of an external

12VGATEB

P-Channel MOSFET. During power-up, the C

MOSFETs are connected to a 25µA current sink. This controls the value of

dv/dt seen at the source of the MOSFETs.

During current limit events, the voltage at this pin is adjusted to maintain

constant current through the switch for a period of t

overcurrent, thermal shutdown, or input undervoltage fault condition occurs,

the GATE pin for the affected slot is immediately brought high. These pins

are charged by an internal current source during power-down. Also, the 3V

supply for the affected slot is shut-down.

3VGATEA

3V Gate Drive Outputs: Each pin connects to the gate of an external

3VGATEB

N-Channel MOSFET. During power-up, the C

MOSFETs are connected to a 25µA current source. This controls the value

of dv/dt seen at the source of the MOSFETs, and hence the current fl owing

into the load capacitance.

During current limit events, the voltage at this pin is adjusted to maintain

constant current through the switch for a period of t

overcurrent, thermal shutdown, or input undervoltage fault condition occurs,

the GATE pin for the affected slot is immediately brought low. During power-

down, these pins are discharged by an internal current source. Also, the 12V

supply for the affected slot is shut down.

Pin Number

Pin Name

Pin Function

12VINA

12V Supply Power and Sense Inputs [A/B]: Two pins are provided for Kelvin.

12VINB

connection (one for each slot). Pin 5 is the (+) Kelvin-sense connection to

the supply side of the sense resistor for 12V Slot A. Pin 32 is the (+) Kelvin

sense connection to the supply side of the sense resistor for 12V Slot B.

These two pins must ultimately connect to each other as close as possible at

the MIC2592B controller in order to eliminate any IR drop between these

pins. An undervoltage lockout circuit (UVLO) prevents the switches from

turning on while this input is less than its lockout threshold.

3VINA

3.3V Supply Power and Sense Inputs [A/B]: Two pins are provided for

3VINB

connection (one for each slot). Pin 12 is the (+) Kelvin-sense connection to

the supply side of the sense resistor for 3V Slot A. Pin 25 is the (+) Kelvin

sense connection to the supply side of the sense resistor for 3V Slot B.

These two pins must ultimately connect to each other as close as possible at

the MIC2592B controller in order to eliminate any IR drop between these

pins. An undervoltage lockout circuit (UVLO) prevents the switches from

turning on while this input is less than its lockout threshold.

3VOUTA

3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs. Used to

3VOUTB

monitor the 3.3V output voltages for Power-is-Good status.

12VOUTA

12V Power-Good Sense Inputs: Connect to 12V[A/B] outputs. Used to

12VOUTB

monitor the 12V output voltages for Power-is-Good status.

12VSENSEA

12V Circuit Breaker Sense Inputs: The current limit thresholds are set

12VSENSEB

by connecting sense resistors between these pins and 12VIN[A/B]. When

the current limit threshold of IR = 50mV is reached, the 12VGATE[A/B] pin

is modulated to maintain a constant voltage across the sense resistor and

therefore a constant current into the load. If the 50mV threshold is exceeded

for t

supply's external MOSFET is immediately pulled high.

3VSENSEA

3V Circuit Breaker Sense Inputs: The current limit thresholds are set by

3VSENSEB

connecting sense resistors between these pins and 3VIN[A/B]. When the

current limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is

modulated to maintain a constant voltage across the sense resistor and

therefore a constant current into the load. If the 50mV threshold is exceeded

for t

supply's external MOSFET is immediately pulled low.

12VGATEA

12V Gate Drive Outputs: Each pin connects to the gate of an external

12VGATEB

P-Channel MOSFET. During power-up, the C

MOSFETs are connected to a 25µA current sink. This controls the value of

dv/dt seen at the source of the MOSFETs.

During current limit events, the voltage at this pin is adjusted to maintain

constant current through the switch for a period of t

overcurrent, thermal shutdown, or input undervoltage fault condition occurs,

the GATE pin for the affected slot is immediately brought high. These pins

are charged by an internal current source during power-down. Also, the 3V

supply for the affected slot is shut-down.

3VGATEA

3V Gate Drive Outputs: Each pin connects to the gate of an external

3VGATEB

N-Channel MOSFET. During power-up, the C

MOSFETs are connected to a 25µA current source. This controls the value

of dv/dt seen at the source of the MOSFETs, and hence the current fl owing

into the load capacitance.

During current limit events, the voltage at this pin is adjusted to maintain

constant current through the switch for a period of t

overcurrent, thermal shutdown, or input undervoltage fault condition occurs,

the GATE pin for the affected slot is immediately brought low. During power-

down, these pins are discharged by an internal current source. Also, the 12V

supply for the affected slot is shut down.

March 2005

M9999-033105

MIC2592B

Micrel

Pin Description (continued)

Pin Number

Pin Name

Pin Function

VSTBYA

3.3V Standby Input Voltage: Required to support PCI Express VAUX output.

VSTBYB

Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]

to ensure that the chip is accessible during standby modes. A UVLO circuit

prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO

threshold. Both pins must be externally connected together at the MIC2592B

controller.

VAUXA

3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect

VAUXB

the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal

400m MOSFETs. These outputs are current limited and protected against

short-circuit faults.

ONA

Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA

ONB

and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by

these controls only after the V

STBY

input supply is valid and stabe (i.e., t

STBY

POR

elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after

a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie

these pins to GND if using SMI power control. Also, see pin description for

/FAULTA and /FAULTB.

AUXENA

Enable Inputs: Rising-edge triggered. Used to enable or disable the

AUXENB

VAUX[A/B] outputs. The outputs can be switched on by these controls only

after the V

STBY

input supply is valid and stabe (i.e., t

STBY

POR

elapses - See the

Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets

the respective slot's Aux Output Fault Latch. Tie these pins to GND if using

SMI power control. Also, see pin description for /FAULTA and /FAULTB.

CFILTERA

Overcurrent Timers: Capacitors connected between these

CFILTERB

pins and GND set the duration of t

FLT

for each slot. The overcurrent fi lter

delay (t

FLT

) is the amount of time for which a slot remains in current limit

before its circuit breaker is tripped.

/PWRGDA

/PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has

/PWRGDB

been commanded to turn on and has successfully begun delivering power to

its respective +12V, +3.3V, and VAUX outputs. Each pin requires an external

pull-up resistor to V

STBY

/FAULTA

/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the

/FAULTB

circuit breaker trips due to a fault condition (overcurrent, input undervoltage,

overtemperature). Each pin requires an external pull-up resistor to V

STBY

Bringing the slot's ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]

was asserted in response to a fault condition on one of the slot's MAIN out-

puts (+12V or +3.3V).

/FAULT[A/B] is reset by bringing the slot's AUXEN[A/B] pin low if

/FAULT[A/B] was asserted in response to a fault condition on the slot's

VAUX output. If a fault condition occurred on both the MAIN and VAUX

outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be

brought low to deassert the /FAULT[A/B] output.

/FORCE_ONA

Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]

/FORCE_ONB

input will turn on all three of the respective slot's outputs (+12V, +3.3V, and

VAUX), while specifi cally defeating all protections on those supplies. This

explcitly includes all overcurrent and short circuit protections, and on-chip

thermal protection for the VAUX[A/B] supplies. Additionally included are the

UVLO protections for the +3.3V and +12V main supplies. The

/FORCE_ON[A/B] pins do not disable UVLO protection for the VAUX[A/B]

supplies. These input pins are intended for diagnostic purposes only.

Asserting /FORCE_ON[A/B] will cause the respective slot's /PWRGD[A/B]

and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus

There is a pair of register bits, accessible via the SMBus, which can be set

to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]

pins -- See CNTRL[A/B] Register Bit D[2].

GPI_A0

General Purpose Inputs: The states of these two inputs are available by

GPI_B0

reading the Common Status Register, Bits [4:5]. If not used, connect each

pin to GND.

Pin Number

Pin Name

Pin Function

VSTBYB

Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]

to ensure that the chip is accessible during standby modes. A UVLO circuit

prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO

threshold. Both pins must be externally connected together at the MIC2592B

controller.

VAUXA

3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect

VAUXB

the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal

400m MOSFETs. These outputs are current limited and protected against

short-circuit faults.

ONA

Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA

ONB

and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by

these controls only after the V

elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after

a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie

these pins to GND if using SMI power control. Also, see pin description for

/FAULTA and /FAULTB.

AUXENA

Enable Inputs: Rising-edge triggered. Used to enable or disable the

AUXENB

VAUX[A/B] outputs. The outputs can be switched on by these controls only

after the V

Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets

the respective slot's Aux Output Fault Latch. Tie these pins to GND if using

SMI power

CFILTERA

Overcurrent Timers: Capacitors connected between these

CFILTERB

pins and GND set the duration of t

delay (t

before its circuit breaker is tripped.

/PWRGDB

been commanded to turn on and has successfully begun delivering power to

its respective +12V, +3.3V, and VAUX outputs. Each pin requires an extern

pull-up resistor to V

/FAULTA

/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the

/FAULTB

circuit breaker trips due to a fault condition (overcurrent, input undervoltage,

overtemperature). Each pin requires an external pull-up resistor to V

Bringing the slot's ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]

was asserted in response to a fault condition on one of the slot's MAIN out-

puts (+12V or +3.3V).

/FAULT[A/B] is reset by bringing the slot's AUXEN[A/B] pin low if

/FAULT[A/B] was asserted in response to a fault condition on the slot's

VAUX output. If a fault condition occurred on both the MAIN and VAUX

outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be

brought low to deassert the /FAULT[A/B] output.

/FORCE_ONA

Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]

/FORCE_ONB

input will turn on all three of the respective slot's outputs (+12V, +3.3V, and

VAUX), while specifi cally defeating all protections on those supplies. This

explcitly includes all overcurrent and short circuit protections, and on-chip

UVLO protections for the +3.3V and +12V main supplies. The

/FORCE_ON[A/B] pins do

supplies. These input pins are intended for diagnostic purposes only.

Asserting /FORCE_ON[A/B] will cause the respective slot's /PWRGD[A/B]

and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus

There is a pair of register bits, accessible via the SMBus, which can be set

to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]

pins -- See CNTRL[A/B] Register Bit D[2].

GPI_A0

General Purpose Inputs: The states of these two inputs are available by

pin to GND.

Pin Number

Pin Name

Pin Function

VSTBYA

3.3V Standby Input Voltage: Required to support PCI Express VAUX output.

VSTBYB

Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]

to ensure that the chip is accessible during standby modes. A UVLO circuit

prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO

threshold. Both pins must be externally connected together at the MIC2592B

controller.

VAUXA

3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect

VAUXB

the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal

400m MOSFETs. These outputs are current limited and protected against

short-circuit faults.

ONA

Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA

ONB

and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by

these controls only after the V

elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after

a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie

these pins to GND if using SMI power control. Also, see pin description for

/FAULTA and /FAULTB.

AUXENA

Enable Inputs: Rising-edge triggered. Used to enable or disable the

AUXENB

VAUX[A/B] outputs. The outputs can be switched on by these controls only

after the V

Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets

the respective slot's Aux Output Fault Latch. Tie these pins to GND if using

SMI power

CFILTERA

Overcurrent Timers: Capacitors connected between these

CFILTERB

pins and GND set the duration of t

delay (t

before its circuit breaker is tripped.

/PWRGDA

/PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has

/PWRGDB

been commanded to turn on and has successfully begun delivering power to

its respective +12V, +3.3V, and VAUX outputs. Each pin requires an extern

pull-up resistor to V

/FAULTA

/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the

/FAULTB

circuit breaker trips due to a fault condition (overcurrent, input undervoltage,

overtemperature). Each pin requires an external pull-up resistor to V

Bringing the slot's ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]

was asserted in response to a fault condition on one of the slot's MAIN out-

puts (+12V or +3.3V).

/FAULT[A/B] is reset by bringing the slot's AUXEN[A/B] pin low if

/FAULT[A/B] was asserted in response to a fault condition on the slot's

VAUX output. If a fault condition occurred on both the MAIN and VAUX

outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be

brought low to deassert the /FAULT[A/B] output.

/FORCE_ONA

Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]

/FORCE_ONB

input will turn on all three of the respective slot's outputs (+12V, +3.3V, and

VAUX), while specifi cally defeating all protections on those supplies. This

explcitly includes all overcurrent and short circuit protections, and on-chip

UVLO protections for the +3.3V and +12V main supplies. The

/FORCE_ON[A/B] pins do

supplies. These input pins are intended for diagnostic purposes only.

Asserting /FORCE_ON[A/B] will cause the respective slot's /PWRGD[A/B]

and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus

There is a pair of register bits, accessible via the SMBus, which can be set

to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]

pins -- See CNTRL[A/B] Register Bit D[2].

GPI_A0

General Purpose Inputs: The states of these two inputs are available by

GPI_B0

reading the Common Status Register, Bits [4:5]. If not used, connect each

pin to GND.

Pin Number

Pin Name

Pin Function

VSTBYA

3.3V Standby Input Voltage: Required to support PCI Express VAUX output.

VSTBYB

Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]

to ensure that the chip is accessible during standby modes. A UVLO circuit

prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO

threshold. Both pins must be externally connected together at the MIC2592B

controller.

VAUXA

3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect

VAUXB

the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal

400m MOSFETs. These outputs are current limited and protected against

short-circuit faults.

ONA

Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA

ONB

and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by

these controls only after the V

elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after

a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie

these pins to GND if using SMI power control. Also, see pin description for

/FAULTA and /FAULTB.

AUXENA

Enable Inputs: Rising-edge triggered. Used to enable or disable the

AUXENB

VAUX[A/B] outputs. The outputs can be switched on by these controls only

after the V

Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets

the respective slot's Aux Output Fault Latch. Tie these pins to GND if using

SMI power

CFILTERA

Overcurrent Timers: Capacitors connected between these

CFILTERB

pins and GND set the duration of t

delay (t

before its circuit breaker is tripped.

/PWRGDA

/PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has

/PWRGDB

been commanded to turn on and has successfully begun delivering power to

its respective +12V, +3.3V, and VAUX outputs. Each pin requires an extern

pull-up resistor to V

/FAULTA

/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the

/FAULTB

circuit breaker trips due to a fault condition (overcurrent, input undervoltage,

overtemperature). Each pin requires an external pull-up resistor to V

Bringing the slot's ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]

was asserted in response to a fault condition on one of the slot's MAIN out-

puts (+12V or +3.3V).

/FAULT[A/B] is reset by bringing the slot's AUXEN[A/B] pin low if

/FAULT[A/B] was asserted in response to a fault condition on the slot's

VAUX output. If a fault condition occurred on both the MAIN and VAUX

outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be

brought low to deassert the /FAULT[A/B] output.

/FORCE_ONA

Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]

/FORCE_ONB

input will turn on all three of the respective slot's outputs (+12V, +3.3V, and

VAUX), while specifi cally defeating all protections on those supplies. This

explcitly includes all overcurrent and short circuit protections, and on-chip

UVLO protections for the +3.3V and +12V main supplies. The

/FORCE_ON[A/B] pins do

supplies. These input pins are intended for diagnostic purposes only.

Asserting /FORCE_ON[A/B] will cause the respective slot's /PWRGD[A/B]

and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus

There is a pair of register bits, accessible via the SMBus, which can be set

to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]

pins -- See CNTRL[A/B] Register Bit D[2].

GPI_A0

General Purpose Inputs: The states of these two inputs are available by

GPI_B0

reading the Common Status Register, Bits [4:5]. If not used, connect each

pin to GND.

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