February 2005

M9999-092004

MIC5162

Micrel, Inc.

MIC5162

Dual Regulator Controller For High-Speed Bus Termination

General Description

The MIC5162 is a dual regulator controller designed for high-
speed bus termination. It offers a simple, low-cost JEDEC
compliant solution for terminating high-speed, low-voltage
digital buses (i.e. DDR, SCSI, GTL, SSTL, HSTL, LV-TTL,
Rambus, LV-PECL, LV-ECL, etc).

The MIC5162 controls two external N-Channel MOSFETs to
form two separate regulators. It operates by switching be-
tween either the high-side MOSFET or the low-side MOSFET
depending on whether the current is being sourced to the load
or sinked by the regulator.

Designed to provide a universal solution for bus termination
regardless of input voltage, output voltage, or load current,
the desired MIC5162 output voltage can be programmed by
externally forcing the reference voltage.

The MIC5162 operates from an input of 1.35V to 6V, with a
second bias supply input required for operation. It is available
in the tiny MSOP-10 package with operating junction tem-
perature range of 40°C to +125°C.

Typical Application

Features

· JEDEC Compliant Bus Termination for SCSI, GTL,

SSTL, HSTL, LV-TTL, Rambus, LV-PECL, LV-ECL, etc.

· DDR memory termination
· Tracking programmable output
· Requires minimal external components
· Wide bandwidth
· Input voltage range: 1.35V to 6V
· Logic controlled enable input
· Tiny MSOP-10 package
· Available 40°C < T

< +125°C

Applications

· Desktop computers
· Notebook computers
· Communication systems
· Video cards

Micrel, Inc. · 2180 Fortune Drive · San Jose, CA 95131 · USA · tel + 1 (408) 944-0800 · fax + 1 (408) 474-1000 · http://www.micrel.com

Load Transient

TIME (200µs/div)

REF

(50mV/div)

SOURCE

(2A/div)

Source 3A

Sink 3A

Typical SSTL-2 Application

OUT

= 330µF

220pF

= 5.0V

DDQ

= 1.35V

to 6.0V

DDQ

SUD50N02-06

MIC5162BMM

VDDQ

VCC

VREF

COMP

GND

120pF

=2.5V to 1.5V

Ordering Information

Part Number

Junction

Standard

Pb-Free

Temp Range

Package

MIC5162BMM

MIC5162YMM

40°C to +125°C

10-Pin MSOP

February 2005

M9999-092004

MIC5162

Micrel, Inc.

Electrical Characteristics

= 25°C with V

DDQ

= 2.5V; V

= 5V; V

= V

; bold values indicate 40ºC<T

<+125ºC; unless otherwise specified. See test

circuit 1 for test circuit configuration.

Parameter

Condition

Min

Typ

Max

Units

REF

Voltage

0.5V

DDQ

Voltage Accuracy (Note 2)

Sourcing; 100mA to 3A

0.4

10

Sinking; 100mA to 3A

0.6

10

Supply Current (I

DDQ

)

= 1.2V (controller ON)

120

140

µA

No Load

200

Supply Current (I

)

No Load

Shutdown Current (Note 3)

= 0.2V (controller OFF)

µA

Startup Time (Note 4)

, = 5V external bias; V

= V

µs

Enable Input

Enable Input Threshold

Regulator enable

1.2

Regulator shutdown

0.3

Enable Hysteresis

Enable Pin Input Current

< 0.2V (controller shutdown)

0.01

µA

> 1.2V (controller enabled)

5.5

µA

Drive

High Side Gate Drive Voltage

High Side MOSFET Fully ON

4.8

4.97

High Side Gate Drive Voltage

High Side MOSFET Fully OFF

0.03

0.2

Low Side Gate Drive Voltage

Low Side MOSFET Fully ON

4.8

4.97

Low Side Gate Drive Voltage

Low Side MOSFET Fully OFF

0.03

0.2

Note 1.

Exceeding the absolute maximum ratings may damage the device.

Note 2.

The V

voltage accuracy is measured as a delta voltage from the reference output (V

REF

Note 3.

Shutdown current is measured only on the V

pin. The V

DDQ

pin will always draw a minimum amount of current when voltage is applied.

Note 4.

Start-up time is defined as the amount of time from V

= V

to HSD = 90% of V

Absolute Maximum Ratings

(Note 1)

Supply Voltage (V

) ...................................................... 7V

Supply Voltage (V

DDQ

) .................................................... 7V

Enable Input Voltage (V

) ............................................. 7V

Junction Temperature Range ............ 40°C < T

< +125°C

Operating Ratings

(Note 2)

Supply Voltage (V

) ............................................ 3V to 6V

Supply Voltage (V

DDQ

) ....................................... 1.35V - 6V

Enable Input Voltage (V

) .................................. 0V to VIN

February 2005

M9999-092004

MIC5162

Micrel, Inc.

Typical Characteristics

-5

-4

-3

-2

-1

-3

-2

-1

REF

] (mV)

OUTPUT CURRENT (A)

REF

]

vs. Output Current

-10

-8

-6

-4

-2

-40 -20 0

20 40 60 80 100 120

REF

] (mV)

TEMPERATURE (°C)

REF

]

vs. Temperature

SINK 3A

-10

-8

-6

-4

-2

-40 -20 0

20 40 60 80 100 120

REF

] (mV)

TEMPERATURE (°C)

REF

]

vs. Temperature

SOURCE 3A

1.2375

1.2400

1.2425

1.2450

1.2475

1.2500

1.2525

1.2550

1.2575

1.2600

1.2625

-40 -20 0

20 40 60 80 100 120

REF

(V)

TEMPERATURE (°C)

REF

vs. Temperature

DDQ

= 2.5V

SOURCE CURRENT (mA)

INPUT VOLTAGE (V)

Current

vs. Input Voltage

-40 -20 0

20 40 60 80 100 120

SOURCE CURRENT (mA)

TEMPERATURE (°C)

Current

vs. Temperature

= 5V

February 2005

M9999-092004

MIC5162

Micrel, Inc.

Applications Information

High performance memory requires high speed signaling.
This increase in speed requires special attention to maintain
signal integrity. Bus termination provides a means to in-
crease signaling speed while maintaining good signal integ-
rity. An example of bus termination is the Series Stub Termi-
nation Logic or SSTL. Figure 1 is an example of an SSTL 2
single ended series parallel terminated output. SSTL 2 is a
JEDEC signaling standard operating off of a 2.5V supply. It
consists of a series resistor (R

) and a terminating resistor

). Values of R

will range between 10 to 30 with a

typical of 22, while R

will range from 22 to 28 with a

typical value of 25. V

REF

must maintain 1/2 V

with a ±1%

tolerance, while V

will dynamically sink and source current

to maintain a termination voltage of ±40mV from the V

REF

line

under all conditions. This method of bus termination reduces
common mode noise, settling time, voltage swings, EMI/RFI
and improves slew rates.

DDQ

VREF

MEMORY

Figure 1.

The MIC5162 is a high performance linear controller, utilizing
scalable N-Channel MOSFETs to provide JEDEC compliant
bus termination. Termination is achieved by dividing down
the V

DDQ

voltage by half, providing the reference (V

REF

)

voltage. An internal error amplifier compares the termination
voltage (V

) and V

REF

, controlling 2 external N-Channel

MOSFETs to sink and/or source current to maintain a termi-
nation voltage (V

) equal to V

REF

. The N-Channels receive

their enhancement voltage from a separate V

pin on the

device.

Although the general discussion is focused on SSTL, the
MIC5162 is also capable of providing bus terminations for
SCSI, GTL, HSTL, LV-TTL, Rambus, LV-PECL and other
systems.

DDQ

The V

DDQ

pin on the MIC5162 provides the source current

through the high side N-Channel and the reference voltage to
the device. The MIC5162 can operate at V

DDQ

voltages as

low as 1.35V. Due to the possibility of large transient currents
being sourced from this line, significant bypass capacitance
will aid in performance by improving the source impedance at
higher frequencies. Since the reference is simply V

DDQ

/2,

perturbations on the V

DDQ

will also appear at half the ampli-

tude on the reference. For this reason, low ESR capacitors
such as ceramics or Oscons are recommended on V

DDQ

is the actual termination point. V

is regulated to V

REF

Due to high speed signaling, the load current seen by V

constantly changing. To maintain adequate large signal
transient response, large Oscons ceramics are recommended
on V

. The proper combination and placement of the Oscon

and ceramic capacitors is important to reduce both ESR and
ESL such that high-current high-speed transients do not
exceed the dynamic voltage tolerance requirement of V

The larger Oscon capacitors provide bulk charge storage
while the smaller ceramic capacitors provide current during
the fast edges of the bus transition. Using several smaller
ceramic capacitors distributed near the termination resistors
is typically important to reduce the effects of PCB trace
inductance.

REF

Two resistors dividing down the V

DDQ

voltage provide V

REF

(Figure 3). The resistors are valued at around 17k. A
minimum capacitor value of 120pF from V

REF

to ground is

required to remove high frequency signals reflected from the
source. Large capacitance values (>1500pF) should be
avoided. Values greater than 1500pF slow down V

REF

and

detract from the reference voltage's ability to track V

DDQ

during high speed load transients.

330µF
Oscon

Vishay

SUD50N02-06

120pF

1µF
Ceramic

100µF

Oscon

Vishay

SUD50N02-06

MIC5162BMM

VDDQ

VCC

VREF

COMP

GND

220pF

Figure 2.

MIC5162

Micrel, Inc.

M9999-092004

February 2005

120pF

VDDQ

VREF

GND

Figure 3.

REF

can also be manipulated for different applications. A

separate voltage source can be used to externally set the
reference point, bypassing the divider network. Also, external
resistors can be added from V

REF

to ground or V

REF

to V

DDQ

to shift the reference point up or down.

supplies the internal circuitry of the MIC5162 and pro-

vides the drive voltage to enhance the external N-Channel
MOSFETs. A small 1µF capacitor is recommended for by-
passing the V

pin. The minimum V

voltage should be a

gate-source voltage above V

without exceeding 6V. For

example, on an SSTL compliant terminator, V

DDQ

equals

2.5V and V

equals 1.25V. If the N-Channel MOSFET

selected requires a gate source voltage of 2.5V, V

should

be a minimum of 3.75V.

Feedback and Compensation

The feedback provides the path for the error amplifier to
regulate V

. An external resistor must be placed between

the feedback and V

. This allows the error amplifier to be

correctly externally compensated.

For most applications, a 3k resistor is recommended.
The COMP pin on the MIC5162 is the output of the internal
error amplifier. By placing a capacitor between the COMP pin
and the feedback pin, this coupled with the feedback resistor
places an external pole on the error amplifier. With a 3k
feedback resistor, a minimum 220pF capacitor is recom-
mended for a 3A peak termination circuit. Increases in load,
multiple N-Channel MOSFETs and/or increase in output
capacitance may require feedback and/or compensation
capacitor values to be increased to maintain stability. Feed-
back resistor values should not exceed 100k and compen-
sation capacitors should not be less than 40pF.

Enable

The MIC5162 features an active high enable input. In the off
mode state, leakage currents are reduced to microamperes.
The enable input has thresholds compatible with TTL/CMOS
for simple logic interfacing. The enable pin can be tied directly
to V

DDQ

or V

for functionality. Do not float the enable pin.

Floating this pin causes the enable to be in an indeterminate
state.

Input Capacitance

Although the MIC5162 does not require an input capacitor for
stability, using one greatly improves device performance.
Due to the high-speed nature of the MIC5162, low ESR
capacitors such as Oscon and ceramics are recommended
for bypassing the input. The recommended value of capaci-
tance will depend greatly on the proximity to the bulk capaci-

tance. Although a 10µF ceramic capacitor will suffice for most
applications, input capacitance may need to be increased in
cases where the termination circuit is greater than 1" away
from the bulk capacitance.

Output Capacitance

Large, low ESR capacitors are recommended for the output
(V

) of the MIC5162. Although low ESR capacitors are not

required for stability, they are recommended to reduce the
effects of high-speed current transients on V

. The change

in voltage during the transient condition will be the effect of the
peak current multiplied by the output capacitor's ESR. For
that reason, Oscon type capacitors are excellent for this
application. They have extremely low ESR and large capaci-
tance-to-size ratio. Ceramic capacitors are also well suited to
termination due to their low ESR. These capacitors should
have a dielectric rating of X5R or X7R. Y5V and Z5U type
capacitors are not recommended, due to their poor perfor-
mance at high frequencies and over temperature. The mini-
mum recommended capacitance for a 3 amp peak circuit is
100µF. Output capacitance can be increased to achieve
greater transient performance.

MOSFET Selection

The MIC5162 utilizes external N-Channel MOSFETs to sink
and source current. MOSFET selection will settle to two main
categories: size and gate threshold (V

MOSFET Power Requirements

One of the most important factors is to determine the amount
of power the MOSFET is going to be required to dissipate.
Power dissipation in an SSTL circuit will be identical for both
the high side and low side MOSFETs. Since the supply
voltage is divided by half to supply V

, both MOSFETs have

the same voltage dropped across them. They are also
required to be able to sink and source the same amount of
current (for either all 0's or all 1's). This equates to each side
being able to dissipate the same amount of power. Power
dissipation calculation for the high-side driver is as follows:

I SOURCE

DDQ

(

)

× _

Where I_source is the average source current.

Power dissipation for the low-side MOSFET is as follows;

I SINK

× _

Where I_sink is the average sink current.

In a typical 3 amp peak SSTL_2 circuit, power considerations
for MOSFET selection would occur as follows.

I SOURCE

DDQ

(

)

(

)

2 5

1 25

1 6

This typical SSTL_2 application would require both high-side
and low-side N-Channel MOSFETs to be able to handle 2
Watts each. In applications where there is excessive power
dissipation, multiple N-Channel MOSFETs may be placed in
parallel. These MOSFETs will share current, distributing
power dissipation across each device.

February 2005

M9999-092004

MIC5162

Micrel, Inc.

The maximum MOSFET die (junction) temperature limits
maximum power dissipation. The ability of the device to
dissipate heat away from the junction is specified by the
junction-to-ambient (

) thermal resistance. This is the sum

of junction-to-case (

) thermal resistance, case-to-sink

(

) thermal resistance and sink-to-ambient (

) thermal

resistance;

In our example of a 3A peak SSTL_2 termination circuit, we
have selected a D-pack N-Channel MOSFET that has a
maximum junction temperature of 150°C. The device has a
junction-to-case thermal resistance of 1.5°C/Watt. Our appli-
cation has a maximum ambient temperature of 60°C. The
required junction-to-ambient thermal resistance can be cal-
culated as follows;

Where T

is the maximum junction temperature, T

is the

maximum ambient temperature and P

is the power dissipa-

tion.

In our example;

C W

° -

150

This shows that our total thermal resistance must be better
than 45°C/W. Since the total thermal resistance is a combi-
nation of all the individual thermal resistances, the amount of
heat sink required can be calculated as follows;

(

)

In our example;

C W

(

)

1 5

0 5

In most cases, case-to-sink thermal resistance can be as-
sumed to be about 0.5°C/W.
The SSTL termination circuit for our example, using 2 D-pack
N-Channel MOSFETs (one high side and one on the low side)
will require at least a 43°C/W heat sink per MOSFET. This
may be accomplished with an external heat sink or even just
the copper area that the MOSFET is soldered to. In some
cases, airflow may also be required to reduce thermal resis-
tance.

MOSFET Gate Threshold

N-Channel MOSFETs require an enhancement voltage
greater than its source voltage. Typical N-Channel MOS-
FETs have a gate-source threshold (V

) of 1.8V and higher.

Since the source of the high side N-Channel is connected to
V

, the MIC5162 V

pin requires a voltage equal to or

greater than the V

voltage. For example, our SSTL_2

termination circuit has a V

voltage of 1.25V. For an N-

Channel that has a V

rating of 2.5V, the V

voltage can

be as low as 3.75V. With an N-Channel that has a 4.5V V

the minimum V

required is 5.75V. Although these N-

Channels are driven below their full enhancement threshold,
it is recommended that the V

voltage has enough margin

to be able to fully enhance the MOSFETs for large signal
transient response. In addition, low gate thresholds MOS-
FETs are recommended to reduce the V

requirements.

February 2005

M9999-092004

MIC5162

Micrel, Inc.

Package Information

0.15 (0.006)
0.05 (0.002)

0.50 BSC (0.020)

6° MAX

0° MIN

3.15 (0.122)
2.85 (0.114)

3.10 (0.122)
2.90 (0.114)

0.30 (0.012)
0.15 (0.006)

0.26 (0.010)
0.10 (0.004)

1.10 (0.043)
0.94 (0.037)

DIMENSIONS:

MM (INCH)

0.70 (0.028)
0.40 (0.016)

4.90 BSC (0.193)

10-Pin SOP (M)

MICREL INC.

2180 FORTUNE DRIVE

SAN JOSE, CA 95131

USA

TEL

+ 1 (408) 944-0800

FAX

+ 1 (408) 474-1000

WEB

http://www.micrel.com

This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can

reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's

use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify

Micrel for any damages resulting from such use or sale.

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