October 1998
1
MIC5821/5822
Micrel
MIC5821/5822
MIC5821/5822
8-Bit Serial-Input Latched Drivers
Final Information
General Description
BiCMOS technology gives the MIC5821/5822 family flexibil-
ity beyond the reach of standard logic buffers and power
driver arrays. These devices each have an eight-bit CMOS
shift register, CMOS control circuitry, eight CMOS data
latches, and eight bipolar current-sink Darlington output
drivers. The 500mA outputs are suitable for use with incan-
descent bulbs and other moderate to high current loads. The
drivers can be operated with a split supply where the negative
supply is down to 20V. Except for maximum driver output
voltage ratings, the MIC5821 and MIC5822 are identical.
These devices have greatly improved data-input rates. With
a 5V logic supply they will typically operate faster than 5
MHz. With a 12V supply significantly higher speeds are
obtained. The CMOS inputs are compatible with standard
CMOS, PMOS, and NMOS logic levels. TTL and DTL circuits
may require the use of appropriate pull-up resistors. By using
the serial data output, the drivers can be cascaded for
interface applications requiring additional drive lines.
Features
3.3 MHz Minimum Data-Input Rate
CMOS, PMOS, NMOS, TTL Compatible
Internal Pull-Down or Pull-Up Resistors
Low-Power CMOS Logic and Latches
High-Voltage Current-Sink Outputs
Single or Split Supply Operation
Ordering Information
Part Number
Temperature Range
Package
MIC5821BN
40
C to +85
C
16-Pin Plastic DIP
MIC5822BN
40
C to +85
C
16-Pin Plastic DIP
8-BIT SERIAL-PARALLEL SHIFT REGISTER
5
SERIAL
DATA OUT
CLK
1
2
3
SERIAL
DATA IN
V
SS
9
V
DD
STROBE
OUTPUT ENABLE
(ACTIVE LOW)
Bipolar
MOS
LATCHES
OUT
8
10
11
12
13
14
15
16
OUT
7
OUT
6
OUT
5
OUT
4
OUT
3
OUT
2
OUT
1
4
6
7
Sub
GND
V
EE
8
Functional Diagram
Pin Configuration
1
2
3
4
5
6
7
12
11
10
9
VDD
1
OUT
2
OUT
3
OUT
4
OUT
CLOCK
SERIAL DATA OUT
SS
V
8
13
14
15
5
OUT
6
OUT
7
OUT
8
OUT
SERIAL DATA IN
STROBE
OUTPUT ENABLE
SUB
VEE
16
LATCHES
SHIFT REGISTER
(Plastic DIP)
Micrel, Inc. 1849 Fortune Drive San Jose, CA 95131 USA tel + 1 (408) 944-0800 fax + 1 (408) 944-0970 http://www.micrel.com
Micrel
MIC5821/5822
MIC5821/5822
2
October 1998
Absolute Maximum Ratings (Note 1)
at 25
C Free-Air Temperature and V
SS
= 0V
Output Voltage, V
CE
(MIC5821)
50V
(MIC5822)
80V
Output Voltage, V
CE SUS
(MIC5821)(Note 3)
35V
(MIC5822)(Note 3)
50V
Logic Supply Voltage, V
DD
15V
Input Voltage Range, V
IN
0.3V to V
DD
+ 0.3V
V
DD
V
EE
25V
Emitter Supply Voltage, V
EE
20V
Continuous Output Current, I
OUT
500mA
Package Power Dissipation, P
D(Note 1)
1.67W
Operating Temperature Range, T
A
55
C to +85
C
Storage Temperature Range, T
S
65
C to +150
C
Note 1: Derate at the rate of 16.7mW/
C above T
A
= 25
C.
Note 2: CMOS devices have input static protection but are susceptible to
damage when exposed to extremely high static electrical
charges.
Note 3: For inductive load applications.
Note 4: Specification for packaged product only.
Maximum Allowable Duty Cycle (Plastic DIP)
Number of Outputs ON
(I
OUT
= 200mA
Maximum Allowable Duty Cycle at Ambient Temperature of
V
DD
= 12V)
25
C
40
C
50
C
60
C
70
C
8
73%
62%
55%
47%
40%
7
83%
71%
62%
54%
46%
6
97%
82%
72%
63%
53%
5
100%
98%
87%
75%
63%
4
100%
100%
100%
93%
79%
3
100%
100%
100%
100%
100%
2
100%
100%
100%
100%
100%
1
100%
100%
100%
100%
100%
SUB
3k
7.2k
V
EE
OUT
N
Typical Output Driver
CLOCK
SERIAL
DATA IN
V
DD
V
SS
Typical Input Circuits
STROBE
OUTPUT
ENABLE
V
DD
V
SS
October 1998
3
MIC5821/5822
Micrel
MIC5821/5822
Electrical Characteristics
(Note 4)
T
A
= 55
C, V
DD
= 5V, V
SS
= V
EE
= 0V (unless otherwise noted)
Limits
Characteristic
Symbol
Test Conditions
Min.
Max.
Unit
Output Leakage Current
I
CEX
V
OUT
= 80V
50
A
Collector-Emitter
V
CE(SAT)
I
OUT
= 100mA
1.3
V
Saturation Voltage
I
OUT
= 200mA
1.5
I
OUT
= 350mA, V
DD
= 7.0V
1.8
Input Voltage
V
IN0)
0.8
V
V
IN(1)
V
DD
= 12V
10.5
V
DD
= 5.0V
3.5
Input Resistance
RIN
V
DD
= 12V
35
k
V
DD
= 10V
35
V
DD
= 5.0V
35
Supply Current
I
DD(ON)
One Driver ON, V
DD
= 12V
5.5
mA
One Driver ON, V
DD
= 10V
4.5
One Driver ON, V
DD
= 5.0V
3.0
All Drivers ON, V
DD
= 12V
16
All Drivers ON, V
DD
= 10V
14
All Drivers ON, V
DD
= 5.0V
10
I
DD(OFF)
All Drivers OFF, V
DD
= 12V
3.5
All Drivers OFF, V
DD
= 5.0V
2.0
Electrical Characteristics
(Note 4)
at T
A
= 25
C V
DD
= 5V, V
EE
= V
SS
= 0V (unless otherwise specified)
Applicable
Limits
Characteristic
Symbol
Devices
Test Conditions
Min.
Max.
Unit
Output Leakage Current
I
CEX
MIC5821
V
OUT
= 50V
50
A
V
OUT
= 50V, T
A
= +70
C
100
MIC5822
V
OUT
= 80V
50
V
OUT
= 80V, T
A
= +70
C
100
Collector-Emitter
V
CE(SAT)
Both
I
OUT
= 100mA
1.1
V
Saturation Voltage
I
OUT
= 200mA
1.3
I
OUT
= 350mA, V
DD
= 7.0V
1.6
Input Voltage
V
IN(0)
Both
0.8
V
V
IN(1)
Both
V
DD
= 12V
10.5
V
DD
= 10V
8.5
V
DD
= 5.0V
3.5
Input Resistance
R
IN
Both
V
DD
= 12V
50
k
V
DD
= 10V
50
V
DD
= 5.0V
50
Supply Current
I
DD(ON)
Both
One Driver ON, V
DD
= 12V
4.5
mA
One Driver ON, V
DD
= 10V
3.9
One Driver ON, V
DD
= 5.0V
2.4
All Drivers ON, V
DD
= 12V
16
All Drivers ON, V
DD
= 10V
14
All Drivers ON, V
DD
= 5.0V
8
I
DD(OFF)
Both
All Drivers OFF, V
DD
= 5.0V,
1.6
All Inputs = 0V
All Drivers OFF, V
DD
= 12V,
2.9
All Inputs= 0V
Micrel
MIC5821/5822
MIC5821/5822
4
October 1998
Electrical Characteristics
(Note 4)
T
A
= +125
C, V
DD
= 5V, V
SS
= V
EE
= 0V (unless otherwise noted)
Limits
Characteristic
Symbol
Test Conditions
Min.
Max.
Unit
Output Leakage Current
I
CEX
V
OUT
= 80V
500
A
Collector-Emitter
V
CE(SAT)
I
OUT
= 100mA
1.3
V
Saturation Voltage
I
OUT
= 200mA
1.5
I
OUT
= 350mA, V
DD
= 7.0V
1.8
Input Voltage
V
IN(0)
0.8
V
V
IN(1)
V
DD
= 12V
10.5
V
DD
= 5.0V
3.5
Input Resistance
R
IN
V
DD
= 12V
50
k
V
DD
= 10V
50
V
DD
= 5.0V
50
Supply Current
I
DD(ON)
One Driver ON, V
DD
= 12V
4.5
mA
One Driver ON, V
DD
= 10V
3.9
One Driver ON, V
DD
= 5.0V
2.4
All Drivers ON, V
DD
= 12V
16
All Drivers ON, V
DD
= 10V
14
All Drivers ON, V
DD
= 5.0V
8
I
DD(OFF)
All Drivers OFF, V
DD
= 12V
2.9
All Drivers OFF, V
DD
= 5.0V
1.6
MIC5821/5822 Family Truth Table
Serial
Shift Register Contents
Serial
Latch Contents
Output Contents
Data
Clock
Data
Strobe
Output
Input
Input
I
1
I
2
I
3
......
I
8
Output
Input
I
1
I
2
I
3
......
I
8
Enable
I
1
I
2
I
3
......
I
8
H
H
R
1
R
2
......
R
7
R
7
L
L
R
1
R
2
......
R
7
R
7
X
R
1
R
2
R
3
......
R
8
R
8
X
X
X
......
X
X
L
R
1
R
2
R
3
......
R
8
P
1
P
2
P
3
......
P
8
P
8
H
P
1
P
2
P
3
......
P
8
L
P
1
P
2
P
3
......
P
8
X
X
X
......
X
H
H
H
H
......
H
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
Timing Diagram
D
CLOCK
DATA IN
STROBE
OUTPUT
ENABLE
OUT
N
B
C
A
F
E
G
October 1998
5
MIC5821/5822
Micrel
MIC5821/5822
Timing Conditions
(T
A
= +25
C, Logic Levels are V
DD
and V
SS
)
V
DD
= 5.0V
A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) ....................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width .................................................................................................................................... 150 ns
D. Minimum Clock Pulse Width ................................................................................................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ............................................................................................ 300 ns
F. Minimum Strobe Pulse Width .................................................................................................................................. 100 ns
G. Typical Time Between Strobe Activation and Output Transition ............................................................................. 500 ns
SERIAL DATA present at the input is transferred to the shift register on the logic "0" to logic "1" transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL
DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion).
The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed
(STROBE tied high) will require that the ENABLE input be high during serial entry.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting the information stored in the
latches or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches.
Typical Applications
MIC5822 Level Shifting Lamp Driver with Darlington Emitters Tied to a Negative Supply
-9V
+5V
100
0.1
SERIAL DATA CLOCK
+
1
2
3
4
5
6
7
12
11
10
9
8
13
14
15
SUB
LATCHES
16
SHIFT REGISTER
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