DESCRIPTION
FEATURES
D FLIP-FLOP
WITH SET AND RESET
PIN NAMES
Pin
Function
D
Data Inputs
Q
Data Outputs
S
Set
R
Reset
CLK
Clock Input
PIN CONFIGURATION/BLOCK DIAGRAM
Rev.: E
Amendment: /0
Issue Date: August, 1998
SY10EL31
SY100EL31
s
475ps propagation delay
s
2.8GHz toggle frequency
s
Internal 75K
input pull-down resistors
s
Available in 8-pin SOIC package
The SY10/100EL31 are D flip-flops with set and reset.
The devices are functionally equivalent to the E131
devices, with higher performance capabilities. With
propagation delays and output transition times
significantly faster than the E131, the EL31 is ideally
suited for those applications which require the ultimate
in AC performance.
Both the set and reset inputs are asynchronous, level
triggered signals. Data enters the master portion of the
flip-flop when the clock is LOW and is transferred to the
slave, and thus the outputs, upon a positive transition of
the clock.
TRUTH TABLE
(1)
D
S
R
CLK
Q
L
L
L
Z
L
H
L
L
Z
H
X
H
L
X
H
X
L
H
X
L
X
H
H
X
Undef
NOTE:
1. Z = LOW-to-HIGH transition.
SOIC
TOP VIEW
1
2
3
4
5
6
7
8
S
V
CC
Q
V
EE
D
R
CLK
Q
S
D
R
Flip-Flop
1
4
SY10EL31
SY100EL31
Micrel
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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