BLOCK DIAGRAM
D
1a
D
2a
D
3a
D
4a
D
5a
D
1b
D
2b
D
3b
D
4b
O
O
D
1c
D
2c
D
3c
D
4c
D
1d
D
2d
D
3d
D
4d
D
1e
D
2e
SY100S318
5-WIDE 5, 4, 4, 4, 2
OA/OAI GATE
FEATURES
PIN CONFIGURATIONS
DESCRIPTION
Pin
Function
D
na
D
ne
Data Inputs (n = 1...5)
O O
Data Outputs
V
EES
V
EE
Substrate
V
CCA
V
CCO
for ECL Outputs
PIN NAMES
O
O
V
CCA
V
CC
D
2e
V
CC
D
2b
V
EE
D
4b
D
3b
D
1c
V
EES
4
3
2
1
28
27
12
13
14
15
16
17
19
11
20
10
21
9
22
8
23
7
24
6
Top View
PLCC
J28-1
D
1e
D
2c
26
18
25
5
D
1b
D
5a
D
4a
V
EE
S
D
3a
D
2a
D
1a
D
1d
V
EES
D
4c
D
2d
D
3c
D
3d
D
4d
D
2c
D
1c
D
4b
V
EE
D
3b
D
2b
D
1b
D
5a
D
4a
D
3a
D
1a
D
2a
D
3c
D
1d
D
3d
D
4c
D
4d
D
2d
18
17
16
15
14
13
1
2
3
4
5
6
7
24
8
23
9
22
10
21
11
20
12
19
Top View
Flatpack
F24-1
V
CC
V
CCA
D
2e
O
D
1e
O
Rev.: G
Amendment: /0
Issue Date:
July, 1999
s
Max. propagation delay of 800ps
s
I
EE
min. of 55mA
s
Extended supply voltage option:
V
EE
= 4.2V to 5.5V
s
Voltage and temperature compensation for
improved noise immunity
s
Internal 75K
input pull-down resistors
s
70% faster than Fairchild
s
40% lower power than Fairchild
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
The SY100S318 is an ultra-fast 5-wide 5, 4, 4, 4, 2 OR/
AND gate with both true and complementary outputs,
designed for use in high-performance ECL systems. The
inputs on this device have 75K
pull-down resistors.
1
2
SY100S318
Micrel
LOGIC EQUATION
O = (D
1a
+ D
2a
+ D
3a
+ D
4
a + D
5a
)
(D
1b
+ D
2b
+ D
3b
+ D
4
b)
(D
1c
+ D
2c
+ D
3c
+ D
4
c)
(D
1d
+ D
2d
+ D
3d
+ D
4
d)
(D
1e
+ D
2e
)
DC ELECTRICAL CHARACTERISTICS
V
EE
= 4.2V to 5.5V unless otherwise specified, V
CC
= V
CCA
= GND
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
I
IH
Input HIGH Current, All Inputs
--
--
200
A
V
IN
= V
IH
(Max.)
I
EE
Power Supply Current
55
41
25
mA
Inputs Open
AC ELECTRICAL CHARACTERISTICS
CERPACK
V
EE
= 4.2V to 5.5V unless otherwise specified, V
CC
= V
CCA
= GND
PLCC
V
EE
= 4.2V to 5.5V unless otherwise specified, V
CC
= V
CCA
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
t
PLH
Propagation Delay
300
800
300
800
300
800
ps
t
PHL
Data to Output
t
TLH
Transition Time
200
900
200
900
200
900
ps
t
THL
20% to 80%, 80% to 20%
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
t
PLH
Propagation Delay
300
900
300
900
300
900
ps
t
PHL
Data to Output
t
TLH
Transition Time
200
900
200
900
200
900
ps
t
THL
20% to 80%, 80% to 20%
3
SY100S318
Micrel
TIMING DIAGRAM
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY100S318FC
F24-1
Commercial
SY100S318JC
J28-1
Commercial
SY100S318JCTR
J28-1
Commercial
Propagation Delay and Transition Times
20%
80%
OUTPUT
INPUT
50%
t
PLH
t
PHL
50%
20%
80%
50%
t
PHL
t
PLH
t
TLH
t
THL
TRUE
COMPLEMENT
0.7
0.1 ns
0.7
0.1 ns
0.95V
1.69V
NOTE:
V
EE
= 4.2V to 5.5V unless otherwise specified, V
CC
= V
CCA
= GND
5
SY100S318
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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