HEX D-LATCH
SY100S350
s
Max. transparent propagation delay of 900ps
s
Min. Master Reset and Enable pulse widths of 100ps
s
I
EE
min. of 98mA
s
Industry standard 100K ECL levels
s
Extended supply voltage option:
V
EE
= 4.2V to 5.5V
s
Voltage and temperature compensation for improved
noise immunity
s
Internal 75K
input pull-down resistors
s
More than 40% faster than Fairchild
s
Approximately 30% lower power than Fairchild
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
FEATURES
DESCRIPTION
The SY100S350 offers six high-speed D-Latches with
both true and complement outputs, and is performance
compatible for use with high-performance ECL systems.
When both enable signals (E
a
and E
b
) are at a logic LOW,
the latches are transparent and the input signals( D
0
D
5
)
appear at the outputs (Q
0
Q
5
) after a propagation delay. If
either or both of the enable signals are at a logic HIGH, then
the latches store the last valid data present on its inputs
before E
a
or E
b
went to a logic HIGH. The Master Reset
(MR) overrides all other input signals and takes the outputs
to a logic LOW state. All inputs have 75K
pull-down
resistors.
Rev.: G
Amendment: /0
Issue Date:
July, 1999
PIN CONFIGURATIONS
E
b
E
a
M
R
V
EE
D
3
D
2
D
1
D
0
Q
0
Q
0
Q
1
Q
1
D
4
Q
5
Q
4
D
5
Q
4
Q
5
18
17
16
15
14
13
1
2
3
4
5
6
7
24
8
23
9
22
10
21
11
20
12
19
Top View
Flatpack
F24-1
V
CC
V
CCA
Q
3
Q
2
Q
3
Q
2
Q
2
Q
2
V
CCA
V
CC
Q
3
V
CC
D
2
V
EE
MR
D
3
E
a
V
EES
4
3
2
1
28
27
12
13
14
15
16
17
19
11
20
10
21
9
22
8
23
7
24
6
Top View
PLCC
J28-1
Q
3
E
b
26
18
25
5
D
1
D
0
Q
0
V
EES
Q
0
Q
1
Q
1
Q
5
V
EES
D
5
Q
5
D
4
Q
4
Q
4
BLOCK DIAGRAM
D
R
D
5
Q
5
E
Q
5
D
R
D
4
Q
4
E
Q
4
D
R
D
3
Q
3
E
Q
3
D
R
D
2
Q
2
E
Q
2
D
R
D
1
Q
1
E
Q
1
D
R
D
0
Q
0
E
Q
0
E
b
MR
E
a
1
2
SY100S350
Micrel
Each Latch
TRUTH TABLE
(1)
Inputs
Outputs
D
n
E
a
E
b
MR
Q
n
Q
n
Operating Mode
H
L
L
L
H
L
Latch
L
L
L
L
L
H
X
X
H
L
Latched
(2)
Latched
(2)
X
H
X
L
Latched
(2)
Latched
(2)
X
X
X
H
L
H
Asynchronous
NOTES:
1. H = HIGH State
L = LOW State
X = Don't Care
2. Retains data that is present before E positive transition.
DC ELECTRICAL CHARACTERISTICS
V
EE
= 4.2V to 5.5V unless otherwise specified; V
CC
= V
CCA
= GND
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
I
IH
Input HIGH Current
A
V
IN
= V
IH
(Max.)
MR
--
--
250
Dn
--
--
250
Ea, Eb
--
--
250
I
EE
Power Supply Current
98
78
49
mA
Inputs Open
Pin
Function
D
0
-- D
5
Data Inputs
E
a
, E
b
Common Enable Inputs (Active LOW)
MR
Asynchronous Master Reset Input
Q
0
-- Q
5
Data Outputs
Q
0
-- Q
5
Complementary Data Outputs
V
EES
V
EE
Substrate
V
CCA
V
CCO
for ECL Outputs
PIN NAMES
3
SY100S350
Micrel
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
t
PLH
Propagation Delay
300
900
300
900
300
900
ps
t
PHL
D
n
to Output
t
PLH
Propagation Delay
300
1000
300
1000
300
1000
ps
t
PHL
E
a
, E
b
to Output
t
PLH
Propagation Delay
300
1200
300
1200
300
1200
ps
t
PHL
MR to Output
t
TLH
Transition Time
300
900
300
900
300
900
ps
t
THL
20% to 80%, 80% to 20%
t
S
Set-up Time, D
n
to E
n
500
--
500
--
500
--
ps
t
H
Hold Time, D
n
to E
n
500
--
500
--
500
--
ps
t
r
Release Time, MR to E
n
1000
--
1000
--
1000
--
ps
t
PW
(L)
Pulse Width, E
a
, E
b
1000
--
1000
--
1000
--
ps
t
PW
(H)
Pulse Width, MR
1000
--
1000
--
1000
--
ps
AC ELECTRICAL CHARACTERISTICS
CERPACK
V
EE
= 4.2V to 5.5V unless otherwise specified; V
CC
= V
CCA
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
t
PLH
Propagation Delay
300
1000
300
1000
300
1000
ps
t
PHL
D
n
to Output
t
PLH
Propagation Delay
300
1100
300
1100
300
1100
ps
t
PHL
E
a
, E
b
to Output
t
PLH
Propagation Delay
300
1250
300
1250
300
1250
ps
t
PHL
MR to Output
t
TLH
Transition Time
300
900
300
900
300
900
ps
t
THL
20% to 80%, 80% to 20%
t
S
Set-up Time, D
n
to E
n
500
--
500
--
500
--
ps
t
H
Hold Time, D
n
to E
n
500
--
500
--
500
--
ps
t
r
Release Time, MR to E
n
1000
--
1000
--
1000
--
ps
t
PW
(L)
Pulse Width, E
a
, E
b
1000
--
1000
--
1000
--
ps
t
PW
(H)
Pulse Width, MR
1000
--
1000
--
1000
--
ps
PLCC
V
EE
= 4.2V to 5.5V unless otherwise specified; V
CC
= V
CCA
= GND
5
SY100S350
Micrel
TIMING DIAGRAMS
ENABLE
DATA
t
S
t
h
Data Set-up and Hold Times
NOTES:
t
S
is the minimum time before the transition of the clock that information must be present at the data input.
t
H
is the minimum time after the transition of the clock that information must remain unchanged at the data input.
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY100S350FC
F24-1
Commercial
SY100S350JC
J28-1
Commercial
SY100S350JCTR
J28-1
Commercial
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