BLOCK DIAGRAM
I
0a
Z
a
I
1a
C
Z
b
I
2a
I
3a
I
4a
I
5a
I
6a
I
7a
I
a
I
0b
I
1b
I
2b
I
3b
I
4b
I
5b
I
6b
I
7b
I
b
SY100S360
DUAL PARITY
CHECKER/
GENERATOR
s
Max. propagation delay of 2200ps
s
I
EE
min. of 70mA
s
Industry standard 100K ECL levels
s
Extended supply voltage option:
V
EE
= 4.2V to 5.5V
s
Voltage and temperature compensation for improved
noise immunity
s
Internal 75K
input pull-down resistors
s
15% faster than Fairchild 300K
s
Approximately 30% lower power than Fairchild 300K
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
FEATURES
DESCRIPTION
The SY100S360 is a dual parity checker/generator and
is designed for use in high-performance ECL systems. The
inputs are segmented into two groups of nine inputs each
and the parity output is at a logic LOW when an even
number of inputs are at a logic HIGH. In each group, one of
the nine inputs (Ia, Ib) has a shorter propagation delay and,
therefore, is ideal as the expansion input for parity
generation of wider data.
A Compare output (C) is also provided which allows
comparison of two 8-bit words. A logic LOW on the C output
indicates a match. The inputs on this device have 75K
pull-down resistors.
Rev.: G
Amendment: /0
Issue Date:
July, 1999
I
a
Z
a
V
CCA
V
CC
C
V
CC
I
6a
V
EE
I
0b
I
7a
I
1b
V
EES
4
3
2
1
28
27
12
13
14
15
16
17
19
11
20
10
21
9
22
8
23
7
24
6
Top View
PLCC
J28-1
Z
b
I
2b
26
18
25
5
I
5a
I
4a
I
3a
V
EES
I
2a
I
1a
I
0a
I
5b
V
EES
I
4b
I
6b
I
3b
I
7b
I
b
I
2b
I
1b
I
0b
V
EE
I
7a
I
6a
I
5a
I
4a
I
3a
I
2a
I
0a
I
1a
I
3b
I
5b
I
7b
I
4b
I
b
I
6b
18
17
16
15
14
13
1
2
3
4
5
6
7
24
8
23
9
22
10
21
11
20
12
19
Top View
Flatpack
F24-1
V
CC
V
CCA
C
Z
a
Z
b
I
a
PIN CONFIGURATIONS
1
2
SY100S360
Micrel
Sum of
Output
High Inputs
Z
Even
HIGH
Odd
LOW
TRUTH TABLE
(1)
NOTE:
1. Comparator Function:
C = (I
0a
I
1a
) + (I
2a
I
3a
) + (I
4a
I
5a
) + (I
6a
I
7a
) +
(I
0b
I
1b
) + (I
2b
I
3b
) + (I
4b
I
5b
) + (I
6b
I
7b
)
AC ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
V
EE
= 4.2V to 5.5V unless otherwise specified; V
CC
= V
CCA
= GND
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
I
IH
Input HIGH Current
A
V
IN
= V
IH
(Max.)
I
a
, I
b
--
--
300
I
na
, I
nb
--
--
200
I
EE
Power Supply Current
70
45
30
mA
Inputs Open
Pin
Function
I
a
, I
b
, I
na
, I
nb
Data Inputs (n = 1...7)
Z
a
Z
b
Parity Odd Outputs
C
Compare Output
V
EES
V
EE
Substrate
V
CCA
V
CCO
for ECL Outputs
PIN NAMES
CERPACK
V
EE
= 4.2V to 5.5V unless otherwise specified; V
CC
= V
CCA
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
t
PLH
Propagation Delay
500
2300
500
2300
500
2300
ps
t
PHL
I
na
, I
nb
to Z
a
, Z
b
t
PLH
Propagation Delay
500
1800
500
1800
500
1800
ps
t
PHL
Ina, Inb to C
t
PLH
Propagation Delay
300
1000
300
1000
300
1000
ps
t
PHL
I
a
, I
b
to Z
a
, Z
b
t
TLH
Transition Time
300
900
300
900
300
900
ps
t
THL
20% to 80%, 80% to 20%
PLCC
V
EE
= 4.2V to 5.5V unless otherwise specified; V
CC
= V
CCA
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
t
PLH
Propagation Delay
500
2200
500
2200
500
2200
ps
t
PHL
I
na
, I
nb
to Z
a
, Z
b
t
PLH
Propagation Delay
500
1700
500
1700
500
1700
ps
t
PHL
Ina, Inb to C
t
PLH
Propagation Delay
300
900
300
900
300
900
ps
t
PHL
I
a
, I
b
to Z
a
, Z
b
t
TLH
Transition Time
300
900
300
900
300
900
ps
t
THL
20% to 80%, 80% to 20%
5
SY100S360
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
PDF 
ZIP
